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powerpc: Delete __cpuinit usage from all users
[linux/fpc-iii.git] / arch / arm / mach-msm / devices-qsd8x50.c
blob2e1b3ec9dfc7c2da5489baac857389b6942efb37
1 /*
2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clkdev.h>
19 #include <linux/dma-mapping.h>
20
21 #include <mach/irqs.h>
22 #include <mach/msm_iomap.h>
23 #include <mach/dma.h>
24 #include <mach/board.h>
25
26 #include "devices.h"
27
28 #include <asm/mach/flash.h>
29
30 #include <linux/platform_data/mmc-msm_sdcc.h>
31 #include "clock-pcom.h"
32
33 static struct resource msm_gpio_resources[] = {
34 {
35 .start = 64 + 165 + 9,
36 .end = 64 + 165 + 9,
37 .flags = IORESOURCE_IRQ,
38 },
39 {
40 .start = 64 + 165 + 10,
41 .end = 64 + 165 + 10,
42 .flags = IORESOURCE_IRQ,
43 },
44 {
45 .start = 0xa9000800,
46 .end = 0xa9000800 + SZ_4K - 1,
47 .flags = IORESOURCE_MEM,
48 .name = "gpio1"
49 },
50 {
51 .start = 0xa9100C00,
52 .end = 0xa9100C00 + SZ_4K - 1,
53 .flags = IORESOURCE_MEM,
54 .name = "gpio2"
55 },
56 };
57
58 struct platform_device msm_device_gpio_8x50 = {
59 .name = "gpio-msm-8x50",
60 .num_resources = ARRAY_SIZE(msm_gpio_resources),
61 .resource = msm_gpio_resources,
62 };
63
64 static struct resource resources_uart3[] = {
65 {
66 .start = INT_UART3,
67 .end = INT_UART3,
68 .flags = IORESOURCE_IRQ,
69 },
70 {
71 .start = MSM_UART3_PHYS,
72 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
73 .flags = IORESOURCE_MEM,
74 .name = "uart_resource"
75 },
76 };
77
78 struct platform_device msm_device_uart3 = {
79 .name = "msm_serial",
80 .id = 2,
81 .num_resources = ARRAY_SIZE(resources_uart3),
82 .resource = resources_uart3,
83 };
84
85 struct platform_device msm_device_smd = {
86 .name = "msm_smd",
87 .id = -1,
88 };
89
90 static struct resource resources_otg[] = {
91 {
92 .start = MSM_HSUSB_PHYS,
93 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
94 .flags = IORESOURCE_MEM,
95 },
96 {
97 .start = INT_USB_HS,
98 .end = INT_USB_HS,
99 .flags = IORESOURCE_IRQ,
100 },
101 };
102
103 struct platform_device msm_device_otg = {
104 .name = "msm_otg",
105 .id = -1,
106 .num_resources = ARRAY_SIZE(resources_otg),
107 .resource = resources_otg,
108 .dev = {
109 .coherent_dma_mask = 0xffffffff,
110 },
111 };
112
113 static struct resource resources_hsusb[] = {
114 {
115 .start = MSM_HSUSB_PHYS,
116 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .start = INT_USB_HS,
121 .end = INT_USB_HS,
122 .flags = IORESOURCE_IRQ,
123 },
124 };
125
126 struct platform_device msm_device_hsusb = {
127 .name = "msm_hsusb",
128 .id = -1,
129 .num_resources = ARRAY_SIZE(resources_hsusb),
130 .resource = resources_hsusb,
131 .dev = {
132 .coherent_dma_mask = 0xffffffff,
133 },
134 };
135
136 static u64 dma_mask = 0xffffffffULL;
137 static struct resource resources_hsusb_host[] = {
138 {
139 .start = MSM_HSUSB_PHYS,
140 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
141 .flags = IORESOURCE_MEM,
142 },
143 {
144 .start = INT_USB_HS,
145 .end = INT_USB_HS,
146 .flags = IORESOURCE_IRQ,
147 },
148 };
149
150 struct platform_device msm_device_hsusb_host = {
151 .name = "msm_hsusb_host",
152 .id = -1,
153 .num_resources = ARRAY_SIZE(resources_hsusb_host),
154 .resource = resources_hsusb_host,
155 .dev = {
156 .dma_mask = &dma_mask,
157 .coherent_dma_mask = 0xffffffffULL,
158 },
159 };
160
161 static struct resource resources_sdc1[] = {
162 {
163 .start = MSM_SDC1_PHYS,
164 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
165 .flags = IORESOURCE_MEM,
166 },
167 {
168 .start = INT_SDC1_0,
169 .end = INT_SDC1_0,
170 .flags = IORESOURCE_IRQ,
171 .name = "cmd_irq",
172 },
173 {
174 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
175 .name = "status_irq"
176 },
177 {
178 .start = 8,
179 .end = 8,
180 .flags = IORESOURCE_DMA,
181 },
182 };
183
184 static struct resource resources_sdc2[] = {
185 {
186 .start = MSM_SDC2_PHYS,
187 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
188 .flags = IORESOURCE_MEM,
189 },
190 {
191 .start = INT_SDC2_0,
192 .end = INT_SDC2_0,
193 .flags = IORESOURCE_IRQ,
194 .name = "cmd_irq",
195 },
196 {
197 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
198 .name = "status_irq"
199 },
200 {
201 .start = 8,
202 .end = 8,
203 .flags = IORESOURCE_DMA,
204 },
205 };
206
207 static struct resource resources_sdc3[] = {
208 {
209 .start = MSM_SDC3_PHYS,
210 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
211 .flags = IORESOURCE_MEM,
212 },
213 {
214 .start = INT_SDC3_0,
215 .end = INT_SDC3_0,
216 .flags = IORESOURCE_IRQ,
217 .name = "cmd_irq",
218 },
219 {
220 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
221 .name = "status_irq"
222 },
223 {
224 .start = 8,
225 .end = 8,
226 .flags = IORESOURCE_DMA,
227 },
228 };
229
230 static struct resource resources_sdc4[] = {
231 {
232 .start = MSM_SDC4_PHYS,
233 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 {
237 .start = INT_SDC4_0,
238 .end = INT_SDC4_0,
239 .flags = IORESOURCE_IRQ,
240 .name = "cmd_irq",
241 },
242 {
243 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
244 .name = "status_irq"
245 },
246 {
247 .start = 8,
248 .end = 8,
249 .flags = IORESOURCE_DMA,
250 },
251 };
252
253 struct platform_device msm_device_sdc1 = {
254 .name = "msm_sdcc",
255 .id = 1,
256 .num_resources = ARRAY_SIZE(resources_sdc1),
257 .resource = resources_sdc1,
258 .dev = {
259 .coherent_dma_mask = 0xffffffff,
260 },
261 };
262
263 struct platform_device msm_device_sdc2 = {
264 .name = "msm_sdcc",
265 .id = 2,
266 .num_resources = ARRAY_SIZE(resources_sdc2),
267 .resource = resources_sdc2,
268 .dev = {
269 .coherent_dma_mask = 0xffffffff,
270 },
271 };
272
273 struct platform_device msm_device_sdc3 = {
274 .name = "msm_sdcc",
275 .id = 3,
276 .num_resources = ARRAY_SIZE(resources_sdc3),
277 .resource = resources_sdc3,
278 .dev = {
279 .coherent_dma_mask = 0xffffffff,
280 },
281 };
282
283 struct platform_device msm_device_sdc4 = {
284 .name = "msm_sdcc",
285 .id = 4,
286 .num_resources = ARRAY_SIZE(resources_sdc4),
287 .resource = resources_sdc4,
288 .dev = {
289 .coherent_dma_mask = 0xffffffff,
290 },
291 };
292
293 static struct platform_device *msm_sdcc_devices[] __initdata = {
294 &msm_device_sdc1,
295 &msm_device_sdc2,
296 &msm_device_sdc3,
297 &msm_device_sdc4,
298 };
299
300 int __init msm_add_sdcc(unsigned int controller,
301 struct msm_mmc_platform_data *plat,
302 unsigned int stat_irq, unsigned long stat_irq_flags)
303 {
304 struct platform_device *pdev;
305 struct resource *res;
306
307 if (controller < 1 || controller > 4)
308 return -EINVAL;
309
310 pdev = msm_sdcc_devices[controller-1];
311 pdev->dev.platform_data = plat;
312
313 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
314 if (!res)
315 return -EINVAL;
316 else if (stat_irq) {
317 res->start = res->end = stat_irq;
318 res->flags &= ~IORESOURCE_DISABLED;
319 res->flags |= stat_irq_flags;
320 }
321
322 return platform_device_register(pdev);
323 }
324
325 struct clk_lookup msm_clocks_8x50[] = {
326 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
327 CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
328 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
329 CLK_PCOM("ebi2_clk", EBI2_CLK, NULL, 0),
330 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
331 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
332 CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
333 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
334 CLK_PCOM("i2c_clk", I2C_CLK, NULL, 0),
335 CLK_PCOM("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
336 CLK_PCOM("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
337 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
338 CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
339 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
340 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
341 CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
342 CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
343 CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
344 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
345 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
346 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
347 CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
348 CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
349 CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
350 CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
351 CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
352 CLK_PCOM("sdc_pclk", SDC3_P_CLK, "msm_sdcc.3", OFF),
353 CLK_PCOM("sdc_clk", SDC4_CLK, "msm_sdcc.4", OFF),
354 CLK_PCOM("sdc_pclk", SDC4_P_CLK, "msm_sdcc.4", OFF),
355 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
356 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
357 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
358 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
359 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
360 CLK_PCOM("uart_clk", UART1_CLK, NULL, OFF),
361 CLK_PCOM("uart_clk", UART2_CLK, NULL, 0),
362 CLK_PCOM("uart_clk", UART3_CLK, "msm_serial.2", OFF),
363 CLK_PCOM("uartdm_clk", UART1DM_CLK, NULL, OFF),
364 CLK_PCOM("uartdm_clk", UART2DM_CLK, NULL, 0),
365 CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
366 CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
367 CLK_PCOM("usb_otg_clk", USB_OTG_CLK, NULL, 0),
368 CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
369 CLK_PCOM("vfe_clk", VFE_CLK, NULL, OFF),
370 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
371 CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
372 CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
373 CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
374 CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
375 CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
376 CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
377 };
378
379 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
380
Linux with added FPC-III support