arch/arm/mach-socfpga/socfpga.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <linux/dw_apb_timer.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/irqchip.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of_platform.h>
  23
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27
  28 #include "core.h"
  29
  30 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
  31 void __iomem *sys_manager_base_addr;
  32 void __iomem *rst_manager_base_addr;
  33 void __iomem *clk_mgr_base_addr;
  34 unsigned long cpu1start_addr;
  35
  36 static struct map_desc scu_io_desc __initdata = {
  37         .virtual        = SOCFPGA_SCU_VIRT_BASE,
  38         .pfn            = 0, /* run-time */
  39         .length         = SZ_8K,
  40         .type           = MT_DEVICE,
  41 };
  42
  43 static struct map_desc uart_io_desc __initdata = {
  44         .virtual        = 0xfec02000,
  45         .pfn            = __phys_to_pfn(0xffc02000),
  46         .length         = SZ_8K,
  47         .type           = MT_DEVICE,
  48 };
  49
  50 static void __init socfpga_scu_map_io(void)
  51 {
  52         unsigned long base;
  53
  54         /* Get SCU base */
  55         asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
  56
  57         scu_io_desc.pfn = __phys_to_pfn(base);
  58         iotable_init(&scu_io_desc, 1);
  59 }
  60
  61 static void __init socfpga_map_io(void)
  62 {
  63         socfpga_scu_map_io();
  64         iotable_init(&uart_io_desc, 1);
  65         early_printk("Early printk initialized\n");
  66 }
  67
  68 void __init socfpga_sysmgr_init(void)
  69 {
  70         struct device_node *np;
  71
  72         np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
  73
  74         if (of_property_read_u32(np, "cpu1-start-addr",
  75                         (u32 *) &cpu1start_addr))
  76                 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
  77
  78         sys_manager_base_addr = of_iomap(np, 0);
  79
  80         np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
  81         rst_manager_base_addr = of_iomap(np, 0);
  82
  83         np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
  84         clk_mgr_base_addr = of_iomap(np, 0);
  85 }
  86
  87 static void __init socfpga_init_irq(void)
  88 {
  89         irqchip_init();
  90         socfpga_sysmgr_init();
  91 }
  92
  93 static void socfpga_cyclone5_restart(char mode, const char *cmd)
  94 {
  95         u32 temp;
  96
  97         temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  98
  99         if (mode == 'h')
 100                 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
 101         else
 102                 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
 103         writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 104 }
 105
 106 static void __init socfpga_cyclone5_init(void)
 107 {
 108         l2x0_of_init(0, ~0UL);
 109         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 110         of_clk_init(NULL);
 111         socfpga_init_clocks();
 112 }
 113
 114 static const char *altera_dt_match[] = {
 115         "altr,socfpga",
 116         NULL
 117 };
 118
 119 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 120         .smp            = smp_ops(socfpga_smp_ops),
 121         .map_io         = socfpga_map_io,
 122         .init_irq       = socfpga_init_irq,
 123         .init_time      = dw_apb_timer_init,
 124         .init_machine   = socfpga_cyclone5_init,
 125         .restart        = socfpga_cyclone5_restart,
 126         .dt_compat      = altera_dt_match,
 127 MACHINE_END