arch/arm/plat-versatile/platsmp.c

   1 /*
   2  *  linux/arch/arm/plat-versatile/platsmp.c
   3  *
   4  *  Copyright (C) 2002 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/smp.h>
  17
  18 #include <asm/cacheflush.h>
  19 #include <asm/smp_plat.h>
  20
  21 /*
  22  * Write pen_release in a way that is guaranteed to be visible to all
  23  * observers, irrespective of whether they're taking part in coherency
  24  * or not.  This is necessary for the hotplug code to work reliably.
  25  */
  26 static void __cpuinit write_pen_release(int val)
  27 {
  28         pen_release = val;
  29         smp_wmb();
  30         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  31         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  32 }
  33
  34 static DEFINE_SPINLOCK(boot_lock);
  35
  36 void __cpuinit versatile_secondary_init(unsigned int cpu)
  37 {
  38         /*
  39          * let the primary processor know we're out of the
  40          * pen, then head off into the C entry point
  41          */
  42         write_pen_release(-1);
  43
  44         /*
  45          * Synchronise with the boot thread.
  46          */
  47         spin_lock(&boot_lock);
  48         spin_unlock(&boot_lock);
  49 }
  50
  51 int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
  52 {
  53         unsigned long timeout;
  54
  55         /*
  56          * Set synchronisation state between this boot processor
  57          * and the secondary one
  58          */
  59         spin_lock(&boot_lock);
  60
  61         /*
  62          * This is really belt and braces; we hold unintended secondary
  63          * CPUs in the holding pen until we're ready for them.  However,
  64          * since we haven't sent them a soft interrupt, they shouldn't
  65          * be there.
  66          */
  67         write_pen_release(cpu_logical_map(cpu));
  68
  69         /*
  70          * Send the secondary CPU a soft interrupt, thereby causing
  71          * the boot monitor to read the system wide flags register,
  72          * and branch to the address found there.
  73          */
  74         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  75
  76         timeout = jiffies + (1 * HZ);
  77         while (time_before(jiffies, timeout)) {
  78                 smp_rmb();
  79                 if (pen_release == -1)
  80                         break;
  81
  82                 udelay(10);
  83         }
  84
  85         /*
  86          * now the secondary core is starting up let it run its
  87          * calibrations, then wait for it to finish
  88          */
  89         spin_unlock(&boot_lock);
  90
  91         return pen_release != -1 ? -ENOSYS : 0;
  92 }