| blob | 9be4e497f3d3c253aa36c87459cdb4830a9e4fa7 |
1 /*
2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
6 * entry point.
7 *
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
20 */
23 #include <asm/asmmacro.h>
24 #include <asm/fpu.h>
25 #include <asm/kregs.h>
26 #include <asm/mmu_context.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/pal.h>
29 #include <asm/paravirt.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/ptrace.h>
33 #include <asm/mca_asm.h>
34 #include <linux/init.h>
35 #include <linux/linkage.h>
37 #ifdef CONFIG_HOTPLUG_CPU
38 #define SAL_PSR_BITS_TO_SET \
39 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
41 #define SAVE_FROM_REG(src, ptr, dest) \
42 mov dest=src;; \
43 st8 [ptr]=dest,0x08
45 #define RESTORE_REG(reg, ptr, _tmp) \
46 ld8 _tmp=[ptr],0x08;; \
47 mov reg=_tmp
49 #define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
50 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
51 mov _idx=0;; \
52 1: \
53 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
54 add _idx=1,_idx;; \
55 br.cloop.sptk.many 1b
57 #define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
58 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
59 mov _idx=0;; \
60 _lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
61 add _idx=1, _idx;; \
62 br.cloop.sptk.many _lbl
64 #define SAVE_ONE_RR(num, _reg, _tmp) \
65 movl _tmp=(num<<61);; \
66 mov _reg=rr[_tmp]
68 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
69 SAVE_ONE_RR(0,_r0, _tmp);; \
70 SAVE_ONE_RR(1,_r1, _tmp);; \
71 SAVE_ONE_RR(2,_r2, _tmp);; \
72 SAVE_ONE_RR(3,_r3, _tmp);; \
73 SAVE_ONE_RR(4,_r4, _tmp);; \
74 SAVE_ONE_RR(5,_r5, _tmp);; \
75 SAVE_ONE_RR(6,_r6, _tmp);; \
76 SAVE_ONE_RR(7,_r7, _tmp);;
78 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
79 st8 [ptr]=_r0, 8;; \
80 st8 [ptr]=_r1, 8;; \
81 st8 [ptr]=_r2, 8;; \
82 st8 [ptr]=_r3, 8;; \
83 st8 [ptr]=_r4, 8;; \
84 st8 [ptr]=_r5, 8;; \
85 st8 [ptr]=_r6, 8;; \
86 st8 [ptr]=_r7, 8;;
88 #define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
89 mov ar.lc=0x08-1;; \
90 movl _idx1=0x00;; \
91 RestRR: \
92 dep.z _idx2=_idx1,61,3;; \
93 ld8 _tmp=[ptr],8;; \
94 mov rr[_idx2]=_tmp;; \
95 srlz.d;; \
96 add _idx1=1,_idx1;; \
97 br.cloop.sptk.few RestRR
99 #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
100 movl reg1=sal_state_for_booting_cpu;; \
101 ld8 reg2=[reg1];;
103 /*
104 * Adjust region registers saved before starting to save
105 * break regs and rest of the states that need to be preserved.
106 */
107 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
108 SAVE_FROM_REG(b0,_reg1,_reg2);; \
109 SAVE_FROM_REG(b1,_reg1,_reg2);; \
110 SAVE_FROM_REG(b2,_reg1,_reg2);; \
111 SAVE_FROM_REG(b3,_reg1,_reg2);; \
112 SAVE_FROM_REG(b4,_reg1,_reg2);; \
113 SAVE_FROM_REG(b5,_reg1,_reg2);; \
114 st8 [_reg1]=r1,0x08;; \
115 st8 [_reg1]=r12,0x08;; \
116 st8 [_reg1]=r13,0x08;; \
117 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
118 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
119 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
120 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
121 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
122 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
123 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
128 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
129 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
130 st8 [_reg1]=r4,0x08;; \
131 st8 [_reg1]=r5,0x08;; \
132 st8 [_reg1]=r6,0x08;; \
133 st8 [_reg1]=r7,0x08;; \
134 st8 [_reg1]=_pred,0x08;; \
135 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
136 stf.spill.nta [_reg1]=f2,16;; \
137 stf.spill.nta [_reg1]=f3,16;; \
138 stf.spill.nta [_reg1]=f4,16;; \
139 stf.spill.nta [_reg1]=f5,16;; \
140 stf.spill.nta [_reg1]=f16,16;; \
141 stf.spill.nta [_reg1]=f17,16;; \
142 stf.spill.nta [_reg1]=f18,16;; \
143 stf.spill.nta [_reg1]=f19,16;; \
144 stf.spill.nta [_reg1]=f20,16;; \
145 stf.spill.nta [_reg1]=f21,16;; \
146 stf.spill.nta [_reg1]=f22,16;; \
147 stf.spill.nta [_reg1]=f23,16;; \
148 stf.spill.nta [_reg1]=f24,16;; \
149 stf.spill.nta [_reg1]=f25,16;; \
150 stf.spill.nta [_reg1]=f26,16;; \
151 stf.spill.nta [_reg1]=f27,16;; \
152 stf.spill.nta [_reg1]=f28,16;; \
153 stf.spill.nta [_reg1]=f29,16;; \
154 stf.spill.nta [_reg1]=f30,16;; \
155 stf.spill.nta [_reg1]=f31,16;;
157 #else
158 #define SET_AREA_FOR_BOOTING_CPU(a1, a2)
159 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
160 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
161 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
162 #endif
164 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
165 movl _tmp1=(num << 61);; \
166 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
167 mov rr[_tmp1]=_tmp2
169 __PAGE_ALIGNED_DATA
171 .global empty_zero_page
172 empty_zero_page:
173 .skip PAGE_SIZE
175 .global swapper_pg_dir
176 swapper_pg_dir:
177 .skip PAGE_SIZE
179 .rodata
180 halt_msg:
181 stringz "Halting kernel\n"
183 __REF
185 .global start_ap
187 /*
188 * Start the kernel. When the bootloader passes control to _start(), r28
189 * points to the address of the boot parameter area. Execution reaches
190 * here in physical mode.
191 */
192 GLOBAL_ENTRY(_start)
193 start_ap:
194 .prologue
195 .save rp, r0 // terminate unwind chain with a NULL rp
196 .body
198 rsm psr.i | psr.ic
199 ;;
200 srlz.i
201 ;;
202 {
203 flushrs // must be first insn in group
204 srlz.i
205 }
206 ;;
207 /*
208 * Save the region registers, predicate before they get clobbered
209 */
210 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
211 mov r25=pr;;
213 /*
214 * Initialize kernel region registers:
215 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
216 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
217 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
218 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
219 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
220 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
221 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
222 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
223 * We initialize all of them to prevent inadvertently assuming
224 * something about the state of address translation early in boot.
225 */
226 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
227 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
228 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
229 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
230 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
231 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
232 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
233 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
234 /*
235 * Now pin mappings into the TLB for kernel text and data
236 */
237 mov r18=KERNEL_TR_PAGE_SHIFT<<2
238 movl r17=KERNEL_START
239 ;;
240 mov cr.itir=r18
241 mov cr.ifa=r17
242 mov r16=IA64_TR_KERNEL
243 mov r3=ip
244 movl r18=PAGE_KERNEL
245 ;;
246 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
247 ;;
248 or r18=r2,r18
249 ;;
250 srlz.i
251 ;;
252 itr.i itr[r16]=r18
253 ;;
254 itr.d dtr[r16]=r18
255 ;;
256 srlz.i
258 /*
259 * Switch into virtual mode:
260 */
261 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
262 |IA64_PSR_DI|IA64_PSR_AC)
263 ;;
264 mov cr.ipsr=r16
265 movl r17=1f
266 ;;
267 mov cr.iip=r17
268 mov cr.ifs=r0
269 ;;
270 rfi
271 ;;
272 1: // now we are in virtual mode
274 SET_AREA_FOR_BOOTING_CPU(r2, r16);
276 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
277 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
278 ;;
280 // set IVT entry point---can't access I/O ports without it
281 movl r3=ia64_ivt
282 ;;
283 mov cr.iva=r3
284 movl r2=FPSR_DEFAULT
285 ;;
286 srlz.i
287 movl gp=__gp
289 mov ar.fpsr=r2
290 ;;
292 #define isAP p2 // are we an Application Processor?
293 #define isBP p3 // are we the Bootstrap Processor?
295 #ifdef CONFIG_SMP
296 /*
297 * Find the init_task for the currently booting CPU. At poweron, and in
298 * UP mode, task_for_booting_cpu is NULL.
299 */
300 movl r3=task_for_booting_cpu
301 ;;
302 ld8 r3=[r3]
303 movl r2=init_task
304 ;;
305 cmp.eq isBP,isAP=r3,r0
306 ;;
307 (isAP) mov r2=r3
308 #else
309 movl r2=init_task
310 cmp.eq isBP,isAP=r0,r0
311 #endif
312 ;;
313 tpa r3=r2 // r3 == phys addr of task struct
314 mov r16=-1
315 (isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
317 // load mapping for stack (virtaddr in r2, physaddr in r3)
318 rsm psr.ic
319 movl r17=PAGE_KERNEL
320 ;;
321 srlz.d
322 dep r18=0,r3,0,12
323 ;;
324 or r18=r17,r18
325 dep r2=-1,r3,61,3 // IMVA of task
326 ;;
327 mov r17=rr[r2]
328 shr.u r16=r3,IA64_GRANULE_SHIFT
329 ;;
330 dep r17=0,r17,8,24
331 ;;
332 mov cr.itir=r17
333 mov cr.ifa=r2
335 mov r19=IA64_TR_CURRENT_STACK
336 ;;
337 itr.d dtr[r19]=r18
338 ;;
339 ssm psr.ic
340 srlz.d
341 ;;
343 .load_current:
344 // load the "current" pointer (r13) and ar.k6 with the current task
345 mov IA64_KR(CURRENT)=r2 // virtual address
346 mov IA64_KR(CURRENT_STACK)=r16
347 mov r13=r2
348 /*
349 * Reserve space at the top of the stack for "struct pt_regs". Kernel
350 * threads don't store interesting values in that structure, but the space
351 * still needs to be there because time-critical stuff such as the context
352 * switching can be implemented more efficiently (for example, __switch_to()
353 * always sets the psr.dfh bit of the task it is switching to).
354 */
356 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
357 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
358 mov ar.rsc=0 // place RSE in enforced lazy mode
359 ;;
360 loadrs // clear the dirty partition
361 movl r19=__phys_per_cpu_start
362 mov r18=PERCPU_PAGE_SIZE
363 ;;
364 #ifndef CONFIG_SMP
365 add r19=r19,r18
366 ;;
367 #else
368 (isAP) br.few 2f
369 movl r20=__cpu0_per_cpu
370 ;;
371 shr.u r18=r18,3
372 1:
373 ld8 r21=[r19],8;;
374 st8[r20]=r21,8
375 adds r18=-1,r18;;
376 cmp4.lt p7,p6=0,r18
377 (p7) br.cond.dptk.few 1b
378 mov r19=r20
379 ;;
380 2:
381 #endif
382 tpa r19=r19
383 ;;
384 .pred.rel.mutex isBP,isAP
385 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
386 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
387 ;;
388 mov ar.bspstore=r2 // establish the new RSE stack
389 ;;
390 mov ar.rsc=0x3 // place RSE in eager mode
392 (isBP) dep r28=-1,r28,61,3 // make address virtual
393 (isBP) movl r2=ia64_boot_param
394 ;;
395 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
397 #ifdef CONFIG_PARAVIRT
399 movl r14=hypervisor_setup_hooks
400 movl r15=hypervisor_type
401 mov r16=num_hypervisor_hooks
402 ;;
403 ld8 r2=[r15]
404 ;;
405 cmp.ltu p7,p0=r2,r16 // array size check
406 shladd r8=r2,3,r14
407 ;;
408 (p7) ld8 r9=[r8]
409 ;;
410 (p7) mov b1=r9
411 (p7) cmp.ne.unc p7,p0=r9,r0 // no actual branch to NULL
412 ;;
413 (p7) br.call.sptk.many rp=b1
415 __INITDATA
417 default_setup_hook = 0 // Currently nothing needs to be done.
419 .weak xen_setup_hook
421 .global hypervisor_type
422 hypervisor_type:
423 data8 PARAVIRT_HYPERVISOR_TYPE_DEFAULT
425 // must have the same order with PARAVIRT_HYPERVISOR_TYPE_xxx
427 hypervisor_setup_hooks:
428 data8 default_setup_hook
429 data8 xen_setup_hook
430 num_hypervisor_hooks = (. - hypervisor_setup_hooks) / 8
431 .previous
433 #endif
435 #ifdef CONFIG_SMP
436 (isAP) br.call.sptk.many rp=start_secondary
437 .ret0:
438 (isAP) br.cond.sptk self
439 #endif
441 // This is executed by the bootstrap processor (bsp) only:
443 #ifdef CONFIG_IA64_FW_EMU
444 // initialize PAL & SAL emulator:
445 br.call.sptk.many rp=sys_fw_init
446 .ret1:
447 #endif
448 br.call.sptk.many rp=start_kernel
449 .ret2: addl r3=@ltoff(halt_msg),gp
450 ;;
451 alloc r2=ar.pfs,8,0,2,0
452 ;;
453 ld8 out0=[r3]
454 br.call.sptk.many b0=console_print
456 self: hint @pause
457 br.sptk.many self // endless loop
458 END(_start)
460 .text
462 GLOBAL_ENTRY(ia64_save_debug_regs)
463 alloc r16=ar.pfs,1,0,0,0
464 mov r20=ar.lc // preserve ar.lc
465 mov ar.lc=IA64_NUM_DBG_REGS-1
466 mov r18=0
467 add r19=IA64_NUM_DBG_REGS*8,in0
468 ;;
469 1: mov r16=dbr[r18]
470 #ifdef CONFIG_ITANIUM
471 ;;
472 srlz.d
473 #endif
474 mov r17=ibr[r18]
475 add r18=1,r18
476 ;;
477 st8.nta [in0]=r16,8
478 st8.nta [r19]=r17,8
479 br.cloop.sptk.many 1b
480 ;;
481 mov ar.lc=r20 // restore ar.lc
482 br.ret.sptk.many rp
483 END(ia64_save_debug_regs)
485 GLOBAL_ENTRY(ia64_load_debug_regs)
486 alloc r16=ar.pfs,1,0,0,0
487 lfetch.nta [in0]
488 mov r20=ar.lc // preserve ar.lc
489 add r19=IA64_NUM_DBG_REGS*8,in0
490 mov ar.lc=IA64_NUM_DBG_REGS-1
491 mov r18=-1
492 ;;
493 1: ld8.nta r16=[in0],8
494 ld8.nta r17=[r19],8
495 add r18=1,r18
496 ;;
497 mov dbr[r18]=r16
498 #ifdef CONFIG_ITANIUM
499 ;;
500 srlz.d // Errata 132 (NoFix status)
501 #endif
502 mov ibr[r18]=r17
503 br.cloop.sptk.many 1b
504 ;;
505 mov ar.lc=r20 // restore ar.lc
506 br.ret.sptk.many rp
507 END(ia64_load_debug_regs)
509 GLOBAL_ENTRY(__ia64_save_fpu)
510 alloc r2=ar.pfs,1,4,0,0
511 adds loc0=96*16-16,in0
512 adds loc1=96*16-16-128,in0
513 ;;
514 stf.spill.nta [loc0]=f127,-256
515 stf.spill.nta [loc1]=f119,-256
516 ;;
517 stf.spill.nta [loc0]=f111,-256
518 stf.spill.nta [loc1]=f103,-256
519 ;;
520 stf.spill.nta [loc0]=f95,-256
521 stf.spill.nta [loc1]=f87,-256
522 ;;
523 stf.spill.nta [loc0]=f79,-256
524 stf.spill.nta [loc1]=f71,-256
525 ;;
526 stf.spill.nta [loc0]=f63,-256
527 stf.spill.nta [loc1]=f55,-256
528 adds loc2=96*16-32,in0
529 ;;
530 stf.spill.nta [loc0]=f47,-256
531 stf.spill.nta [loc1]=f39,-256
532 adds loc3=96*16-32-128,in0
533 ;;
534 stf.spill.nta [loc2]=f126,-256
535 stf.spill.nta [loc3]=f118,-256
536 ;;
537 stf.spill.nta [loc2]=f110,-256
538 stf.spill.nta [loc3]=f102,-256
539 ;;
540 stf.spill.nta [loc2]=f94,-256
541 stf.spill.nta [loc3]=f86,-256
542 ;;
543 stf.spill.nta [loc2]=f78,-256
544 stf.spill.nta [loc3]=f70,-256
545 ;;
546 stf.spill.nta [loc2]=f62,-256
547 stf.spill.nta [loc3]=f54,-256
548 adds loc0=96*16-48,in0
549 ;;
550 stf.spill.nta [loc2]=f46,-256
551 stf.spill.nta [loc3]=f38,-256
552 adds loc1=96*16-48-128,in0
553 ;;
554 stf.spill.nta [loc0]=f125,-256
555 stf.spill.nta [loc1]=f117,-256
556 ;;
557 stf.spill.nta [loc0]=f109,-256
558 stf.spill.nta [loc1]=f101,-256
559 ;;
560 stf.spill.nta [loc0]=f93,-256
561 stf.spill.nta [loc1]=f85,-256
562 ;;
563 stf.spill.nta [loc0]=f77,-256
564 stf.spill.nta [loc1]=f69,-256
565 ;;
566 stf.spill.nta [loc0]=f61,-256
567 stf.spill.nta [loc1]=f53,-256
568 adds loc2=96*16-64,in0
569 ;;
570 stf.spill.nta [loc0]=f45,-256
571 stf.spill.nta [loc1]=f37,-256
572 adds loc3=96*16-64-128,in0
573 ;;
574 stf.spill.nta [loc2]=f124,-256
575 stf.spill.nta [loc3]=f116,-256
576 ;;
577 stf.spill.nta [loc2]=f108,-256
578 stf.spill.nta [loc3]=f100,-256
579 ;;
580 stf.spill.nta [loc2]=f92,-256
581 stf.spill.nta [loc3]=f84,-256
582 ;;
583 stf.spill.nta [loc2]=f76,-256
584 stf.spill.nta [loc3]=f68,-256
585 ;;
586 stf.spill.nta [loc2]=f60,-256
587 stf.spill.nta [loc3]=f52,-256
588 adds loc0=96*16-80,in0
589 ;;
590 stf.spill.nta [loc2]=f44,-256
591 stf.spill.nta [loc3]=f36,-256
592 adds loc1=96*16-80-128,in0
593 ;;
594 stf.spill.nta [loc0]=f123,-256
595 stf.spill.nta [loc1]=f115,-256
596 ;;
597 stf.spill.nta [loc0]=f107,-256
598 stf.spill.nta [loc1]=f99,-256
599 ;;
600 stf.spill.nta [loc0]=f91,-256
601 stf.spill.nta [loc1]=f83,-256
602 ;;
603 stf.spill.nta [loc0]=f75,-256
604 stf.spill.nta [loc1]=f67,-256
605 ;;
606 stf.spill.nta [loc0]=f59,-256
607 stf.spill.nta [loc1]=f51,-256
608 adds loc2=96*16-96,in0
609 ;;
610 stf.spill.nta [loc0]=f43,-256
611 stf.spill.nta [loc1]=f35,-256
612 adds loc3=96*16-96-128,in0
613 ;;
614 stf.spill.nta [loc2]=f122,-256
615 stf.spill.nta [loc3]=f114,-256
616 ;;
617 stf.spill.nta [loc2]=f106,-256
618 stf.spill.nta [loc3]=f98,-256
619 ;;
620 stf.spill.nta [loc2]=f90,-256
621 stf.spill.nta [loc3]=f82,-256
622 ;;
623 stf.spill.nta [loc2]=f74,-256
624 stf.spill.nta [loc3]=f66,-256
625 ;;
626 stf.spill.nta [loc2]=f58,-256
627 stf.spill.nta [loc3]=f50,-256
628 adds loc0=96*16-112,in0
629 ;;
630 stf.spill.nta [loc2]=f42,-256
631 stf.spill.nta [loc3]=f34,-256
632 adds loc1=96*16-112-128,in0
633 ;;
634 stf.spill.nta [loc0]=f121,-256
635 stf.spill.nta [loc1]=f113,-256
636 ;;
637 stf.spill.nta [loc0]=f105,-256
638 stf.spill.nta [loc1]=f97,-256
639 ;;
640 stf.spill.nta [loc0]=f89,-256
641 stf.spill.nta [loc1]=f81,-256
642 ;;
643 stf.spill.nta [loc0]=f73,-256
644 stf.spill.nta [loc1]=f65,-256
645 ;;
646 stf.spill.nta [loc0]=f57,-256
647 stf.spill.nta [loc1]=f49,-256
648 adds loc2=96*16-128,in0
649 ;;
650 stf.spill.nta [loc0]=f41,-256
651 stf.spill.nta [loc1]=f33,-256
652 adds loc3=96*16-128-128,in0
653 ;;
654 stf.spill.nta [loc2]=f120,-256
655 stf.spill.nta [loc3]=f112,-256
656 ;;
657 stf.spill.nta [loc2]=f104,-256
658 stf.spill.nta [loc3]=f96,-256
659 ;;
660 stf.spill.nta [loc2]=f88,-256
661 stf.spill.nta [loc3]=f80,-256
662 ;;
663 stf.spill.nta [loc2]=f72,-256
664 stf.spill.nta [loc3]=f64,-256
665 ;;
666 stf.spill.nta [loc2]=f56,-256
667 stf.spill.nta [loc3]=f48,-256
668 ;;
669 stf.spill.nta [loc2]=f40
670 stf.spill.nta [loc3]=f32
671 br.ret.sptk.many rp
672 END(__ia64_save_fpu)
674 GLOBAL_ENTRY(__ia64_load_fpu)
675 alloc r2=ar.pfs,1,2,0,0
676 adds r3=128,in0
677 adds r14=256,in0
678 adds r15=384,in0
679 mov loc0=512
680 mov loc1=-1024+16
681 ;;
682 ldf.fill.nta f32=[in0],loc0
683 ldf.fill.nta f40=[ r3],loc0
684 ldf.fill.nta f48=[r14],loc0
685 ldf.fill.nta f56=[r15],loc0
686 ;;
687 ldf.fill.nta f64=[in0],loc0
688 ldf.fill.nta f72=[ r3],loc0
689 ldf.fill.nta f80=[r14],loc0
690 ldf.fill.nta f88=[r15],loc0
691 ;;
692 ldf.fill.nta f96=[in0],loc1
693 ldf.fill.nta f104=[ r3],loc1
694 ldf.fill.nta f112=[r14],loc1
695 ldf.fill.nta f120=[r15],loc1
696 ;;
697 ldf.fill.nta f33=[in0],loc0
698 ldf.fill.nta f41=[ r3],loc0
699 ldf.fill.nta f49=[r14],loc0
700 ldf.fill.nta f57=[r15],loc0
701 ;;
702 ldf.fill.nta f65=[in0],loc0
703 ldf.fill.nta f73=[ r3],loc0
704 ldf.fill.nta f81=[r14],loc0
705 ldf.fill.nta f89=[r15],loc0
706 ;;
707 ldf.fill.nta f97=[in0],loc1
708 ldf.fill.nta f105=[ r3],loc1
709 ldf.fill.nta f113=[r14],loc1
710 ldf.fill.nta f121=[r15],loc1
711 ;;
712 ldf.fill.nta f34=[in0],loc0
713 ldf.fill.nta f42=[ r3],loc0
714 ldf.fill.nta f50=[r14],loc0
715 ldf.fill.nta f58=[r15],loc0
716 ;;
717 ldf.fill.nta f66=[in0],loc0
718 ldf.fill.nta f74=[ r3],loc0
719 ldf.fill.nta f82=[r14],loc0
720 ldf.fill.nta f90=[r15],loc0
721 ;;
722 ldf.fill.nta f98=[in0],loc1
723 ldf.fill.nta f106=[ r3],loc1
724 ldf.fill.nta f114=[r14],loc1
725 ldf.fill.nta f122=[r15],loc1
726 ;;
727 ldf.fill.nta f35=[in0],loc0
728 ldf.fill.nta f43=[ r3],loc0
729 ldf.fill.nta f51=[r14],loc0
730 ldf.fill.nta f59=[r15],loc0
731 ;;
732 ldf.fill.nta f67=[in0],loc0
733 ldf.fill.nta f75=[ r3],loc0
734 ldf.fill.nta f83=[r14],loc0
735 ldf.fill.nta f91=[r15],loc0
736 ;;
737 ldf.fill.nta f99=[in0],loc1
738 ldf.fill.nta f107=[ r3],loc1
739 ldf.fill.nta f115=[r14],loc1
740 ldf.fill.nta f123=[r15],loc1
741 ;;
742 ldf.fill.nta f36=[in0],loc0
743 ldf.fill.nta f44=[ r3],loc0
744 ldf.fill.nta f52=[r14],loc0
745 ldf.fill.nta f60=[r15],loc0
746 ;;
747 ldf.fill.nta f68=[in0],loc0
748 ldf.fill.nta f76=[ r3],loc0
749 ldf.fill.nta f84=[r14],loc0
750 ldf.fill.nta f92=[r15],loc0
751 ;;
752 ldf.fill.nta f100=[in0],loc1
753 ldf.fill.nta f108=[ r3],loc1
754 ldf.fill.nta f116=[r14],loc1
755 ldf.fill.nta f124=[r15],loc1
756 ;;
757 ldf.fill.nta f37=[in0],loc0
758 ldf.fill.nta f45=[ r3],loc0
759 ldf.fill.nta f53=[r14],loc0
760 ldf.fill.nta f61=[r15],loc0
761 ;;
762 ldf.fill.nta f69=[in0],loc0
763 ldf.fill.nta f77=[ r3],loc0
764 ldf.fill.nta f85=[r14],loc0
765 ldf.fill.nta f93=[r15],loc0
766 ;;
767 ldf.fill.nta f101=[in0],loc1
768 ldf.fill.nta f109=[ r3],loc1
769 ldf.fill.nta f117=[r14],loc1
770 ldf.fill.nta f125=[r15],loc1
771 ;;
772 ldf.fill.nta f38 =[in0],loc0
773 ldf.fill.nta f46 =[ r3],loc0
774 ldf.fill.nta f54 =[r14],loc0
775 ldf.fill.nta f62 =[r15],loc0
776 ;;
777 ldf.fill.nta f70 =[in0],loc0
778 ldf.fill.nta f78 =[ r3],loc0
779 ldf.fill.nta f86 =[r14],loc0
780 ldf.fill.nta f94 =[r15],loc0
781 ;;
782 ldf.fill.nta f102=[in0],loc1
783 ldf.fill.nta f110=[ r3],loc1
784 ldf.fill.nta f118=[r14],loc1
785 ldf.fill.nta f126=[r15],loc1
786 ;;
787 ldf.fill.nta f39 =[in0],loc0
788 ldf.fill.nta f47 =[ r3],loc0
789 ldf.fill.nta f55 =[r14],loc0
790 ldf.fill.nta f63 =[r15],loc0
791 ;;
792 ldf.fill.nta f71 =[in0],loc0
793 ldf.fill.nta f79 =[ r3],loc0
794 ldf.fill.nta f87 =[r14],loc0
795 ldf.fill.nta f95 =[r15],loc0
796 ;;
797 ldf.fill.nta f103=[in0]
798 ldf.fill.nta f111=[ r3]
799 ldf.fill.nta f119=[r14]
800 ldf.fill.nta f127=[r15]
801 br.ret.sptk.many rp
802 END(__ia64_load_fpu)
804 GLOBAL_ENTRY(__ia64_init_fpu)
805 stf.spill [sp]=f0 // M3
806 mov f32=f0 // F
807 nop.b 0
809 ldfps f33,f34=[sp] // M0
810 ldfps f35,f36=[sp] // M1
811 mov f37=f0 // F
812 ;;
814 setf.s f38=r0 // M2
815 setf.s f39=r0 // M3
816 mov f40=f0 // F
818 ldfps f41,f42=[sp] // M0
819 ldfps f43,f44=[sp] // M1
820 mov f45=f0 // F
822 setf.s f46=r0 // M2
823 setf.s f47=r0 // M3
824 mov f48=f0 // F
826 ldfps f49,f50=[sp] // M0
827 ldfps f51,f52=[sp] // M1
828 mov f53=f0 // F
830 setf.s f54=r0 // M2
831 setf.s f55=r0 // M3
832 mov f56=f0 // F
834 ldfps f57,f58=[sp] // M0
835 ldfps f59,f60=[sp] // M1
836 mov f61=f0 // F
838 setf.s f62=r0 // M2
839 setf.s f63=r0 // M3
840 mov f64=f0 // F
842 ldfps f65,f66=[sp] // M0
843 ldfps f67,f68=[sp] // M1
844 mov f69=f0 // F
846 setf.s f70=r0 // M2
847 setf.s f71=r0 // M3
848 mov f72=f0 // F
850 ldfps f73,f74=[sp] // M0
851 ldfps f75,f76=[sp] // M1
852 mov f77=f0 // F
854 setf.s f78=r0 // M2
855 setf.s f79=r0 // M3
856 mov f80=f0 // F
858 ldfps f81,f82=[sp] // M0
859 ldfps f83,f84=[sp] // M1
860 mov f85=f0 // F
862 setf.s f86=r0 // M2
863 setf.s f87=r0 // M3
864 mov f88=f0 // F
866 /*
867 * When the instructions are cached, it would be faster to initialize
868 * the remaining registers with simply mov instructions (F-unit).
869 * This gets the time down to ~29 cycles. However, this would use up
870 * 33 bundles, whereas continuing with the above pattern yields
871 * 10 bundles and ~30 cycles.
872 */
874 ldfps f89,f90=[sp] // M0
875 ldfps f91,f92=[sp] // M1
876 mov f93=f0 // F
878 setf.s f94=r0 // M2
879 setf.s f95=r0 // M3
880 mov f96=f0 // F
882 ldfps f97,f98=[sp] // M0
883 ldfps f99,f100=[sp] // M1
884 mov f101=f0 // F
886 setf.s f102=r0 // M2
887 setf.s f103=r0 // M3
888 mov f104=f0 // F
890 ldfps f105,f106=[sp] // M0
891 ldfps f107,f108=[sp] // M1
892 mov f109=f0 // F
894 setf.s f110=r0 // M2
895 setf.s f111=r0 // M3
896 mov f112=f0 // F
898 ldfps f113,f114=[sp] // M0
899 ldfps f115,f116=[sp] // M1
900 mov f117=f0 // F
902 setf.s f118=r0 // M2
903 setf.s f119=r0 // M3
904 mov f120=f0 // F
906 ldfps f121,f122=[sp] // M0
907 ldfps f123,f124=[sp] // M1
908 mov f125=f0 // F
910 setf.s f126=r0 // M2
911 setf.s f127=r0 // M3
912 br.ret.sptk.many rp // F
913 END(__ia64_init_fpu)
915 /*
916 * Switch execution mode from virtual to physical
917 *
918 * Inputs:
919 * r16 = new psr to establish
920 * Output:
921 * r19 = old virtual address of ar.bsp
922 * r20 = old virtual address of sp
923 *
924 * Note: RSE must already be in enforced lazy mode
925 */
926 GLOBAL_ENTRY(ia64_switch_mode_phys)
927 {
928 rsm psr.i | psr.ic // disable interrupts and interrupt collection
929 mov r15=ip
930 }
931 ;;
932 {
933 flushrs // must be first insn in group
934 srlz.i
935 }
936 ;;
937 mov cr.ipsr=r16 // set new PSR
938 add r3=1f-ia64_switch_mode_phys,r15
940 mov r19=ar.bsp
941 mov r20=sp
942 mov r14=rp // get return address into a general register
943 ;;
945 // going to physical mode, use tpa to translate virt->phys
946 tpa r17=r19
947 tpa r3=r3
948 tpa sp=sp
949 tpa r14=r14
950 ;;
952 mov r18=ar.rnat // save ar.rnat
953 mov ar.bspstore=r17 // this steps on ar.rnat
954 mov cr.iip=r3
955 mov cr.ifs=r0
956 ;;
957 mov ar.rnat=r18 // restore ar.rnat
958 rfi // must be last insn in group
959 ;;
960 1: mov rp=r14
961 br.ret.sptk.many rp
962 END(ia64_switch_mode_phys)
964 /*
965 * Switch execution mode from physical to virtual
966 *
967 * Inputs:
968 * r16 = new psr to establish
969 * r19 = new bspstore to establish
970 * r20 = new sp to establish
971 *
972 * Note: RSE must already be in enforced lazy mode
973 */
974 GLOBAL_ENTRY(ia64_switch_mode_virt)
975 {
976 rsm psr.i | psr.ic // disable interrupts and interrupt collection
977 mov r15=ip
978 }
979 ;;
980 {
981 flushrs // must be first insn in group
982 srlz.i
983 }
984 ;;
985 mov cr.ipsr=r16 // set new PSR
986 add r3=1f-ia64_switch_mode_virt,r15
988 mov r14=rp // get return address into a general register
989 ;;
991 // going to virtual
992 // - for code addresses, set upper bits of addr to KERNEL_START
993 // - for stack addresses, copy from input argument
994 movl r18=KERNEL_START
995 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
996 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
997 mov sp=r20
998 ;;
999 or r3=r3,r18
1000 or r14=r14,r18
1001 ;;
1003 mov r18=ar.rnat // save ar.rnat
1004 mov ar.bspstore=r19 // this steps on ar.rnat
1005 mov cr.iip=r3
1006 mov cr.ifs=r0
1007 ;;
1008 mov ar.rnat=r18 // restore ar.rnat
1009 rfi // must be last insn in group
1010 ;;
1011 1: mov rp=r14
1012 br.ret.sptk.many rp
1013 END(ia64_switch_mode_virt)
1015 GLOBAL_ENTRY(ia64_delay_loop)
1016 .prologue
1017 { nop 0 // work around GAS unwind info generation bug...
1018 .save ar.lc,r2
1019 mov r2=ar.lc
1020 .body
1021 ;;
1022 mov ar.lc=r32
1023 }
1024 ;;
1025 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
1026 // inside function body without corrupting unwind info).
1027 { nop 0 }
1028 1: br.cloop.sptk.few 1b
1029 ;;
1030 mov ar.lc=r2
1031 br.ret.sptk.many rp
1032 END(ia64_delay_loop)
1034 /*
1035 * Return a CPU-local timestamp in nano-seconds. This timestamp is
1036 * NOT synchronized across CPUs its return value must never be
1037 * compared against the values returned on another CPU. The usage in
1038 * kernel/sched.c ensures that.
1039 *
1040 * The return-value of sched_clock() is NOT supposed to wrap-around.
1041 * If it did, it would cause some scheduling hiccups (at the worst).
1042 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1043 * that would happen only once every 5+ years.
1044 *
1045 * The code below basically calculates:
1046 *
1047 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1048 *
1049 * except that the multiplication and the shift are done with 128-bit
1050 * intermediate precision so that we can produce a full 64-bit result.
1051 */
1052 GLOBAL_ENTRY(ia64_native_sched_clock)
1053 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1054 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1055 ;;
1056 ldf8 f8=[r8]
1057 ;;
1058 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
1059 ;;
1060 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1061 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1062 ;;
1063 getf.sig r8=f10 // (5 cyc)
1064 getf.sig r9=f11
1065 ;;
1066 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1067 br.ret.sptk.many rp
1068 END(ia64_native_sched_clock)
1069 #ifndef CONFIG_PARAVIRT
1070 //unsigned long long
1071 //sched_clock(void) __attribute__((alias("ia64_native_sched_clock")));
1072 .global sched_clock
1073 sched_clock = ia64_native_sched_clock
1074 #endif
1076 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
1077 GLOBAL_ENTRY(cycle_to_cputime)
1078 alloc r16=ar.pfs,1,0,0,0
1079 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1080 ;;
1081 ldf8 f8=[r8]
1082 ;;
1083 setf.sig f9=r32
1084 ;;
1085 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1086 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1087 ;;
1088 getf.sig r8=f10 // (5 cyc)
1089 getf.sig r9=f11
1090 ;;
1091 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1092 br.ret.sptk.many rp
1093 END(cycle_to_cputime)
1094 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
1096 #ifdef CONFIG_IA64_BRL_EMU
1098 /*
1099 * Assembly routines used by brl_emu.c to set preserved register state.
1100 */
1102 #define SET_REG(reg) \
1103 GLOBAL_ENTRY(ia64_set_##reg); \
1104 alloc r16=ar.pfs,1,0,0,0; \
1105 mov reg=r32; \
1106 ;; \
1107 br.ret.sptk.many rp; \
1108 END(ia64_set_##reg)
1110 SET_REG(b1);
1111 SET_REG(b2);
1112 SET_REG(b3);
1113 SET_REG(b4);
1114 SET_REG(b5);
1116 #endif /* CONFIG_IA64_BRL_EMU */
1118 #ifdef CONFIG_SMP
1120 #ifdef CONFIG_HOTPLUG_CPU
1121 GLOBAL_ENTRY(ia64_jump_to_sal)
1122 alloc r16=ar.pfs,1,0,0,0;;
1123 rsm psr.i | psr.ic
1124 {
1125 flushrs
1126 srlz.i
1127 }
1128 tpa r25=in0
1129 movl r18=tlb_purge_done;;
1130 DATA_VA_TO_PA(r18);;
1131 mov b1=r18 // Return location
1132 movl r18=ia64_do_tlb_purge;;
1133 DATA_VA_TO_PA(r18);;
1134 mov b2=r18 // doing tlb_flush work
1135 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1136 movl r17=1f;;
1137 DATA_VA_TO_PA(r17);;
1138 mov cr.iip=r17
1139 movl r16=SAL_PSR_BITS_TO_SET;;
1140 mov cr.ipsr=r16
1141 mov cr.ifs=r0;;
1142 rfi;; // note: this unmask MCA/INIT (psr.mc)
1143 1:
1144 /*
1145 * Invalidate all TLB data/inst
1146 */
1147 br.sptk.many b2;; // jump to tlb purge code
1149 tlb_purge_done:
1150 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1151 RESTORE_REG(b0, r25, r17);;
1152 RESTORE_REG(b1, r25, r17);;
1153 RESTORE_REG(b2, r25, r17);;
1154 RESTORE_REG(b3, r25, r17);;
1155 RESTORE_REG(b4, r25, r17);;
1156 RESTORE_REG(b5, r25, r17);;
1157 ld8 r1=[r25],0x08;;
1158 ld8 r12=[r25],0x08;;
1159 ld8 r13=[r25],0x08;;
1160 RESTORE_REG(ar.fpsr, r25, r17);;
1161 RESTORE_REG(ar.pfs, r25, r17);;
1162 RESTORE_REG(ar.rnat, r25, r17);;
1163 RESTORE_REG(ar.unat, r25, r17);;
1164 RESTORE_REG(ar.bspstore, r25, r17);;
1165 RESTORE_REG(cr.dcr, r25, r17);;
1166 RESTORE_REG(cr.iva, r25, r17);;
1167 RESTORE_REG(cr.pta, r25, r17);;
1168 srlz.d;; // required not to violate RAW dependency
1169 RESTORE_REG(cr.itv, r25, r17);;
1170 RESTORE_REG(cr.pmv, r25, r17);;
1171 RESTORE_REG(cr.cmcv, r25, r17);;
1172 RESTORE_REG(cr.lrr0, r25, r17);;
1173 RESTORE_REG(cr.lrr1, r25, r17);;
1174 ld8 r4=[r25],0x08;;
1175 ld8 r5=[r25],0x08;;
1176 ld8 r6=[r25],0x08;;
1177 ld8 r7=[r25],0x08;;
1178 ld8 r17=[r25],0x08;;
1179 mov pr=r17,-1;;
1180 RESTORE_REG(ar.lc, r25, r17);;
1181 /*
1182 * Now Restore floating point regs
1183 */
1184 ldf.fill.nta f2=[r25],16;;
1185 ldf.fill.nta f3=[r25],16;;
1186 ldf.fill.nta f4=[r25],16;;
1187 ldf.fill.nta f5=[r25],16;;
1188 ldf.fill.nta f16=[r25],16;;
1189 ldf.fill.nta f17=[r25],16;;
1190 ldf.fill.nta f18=[r25],16;;
1191 ldf.fill.nta f19=[r25],16;;
1192 ldf.fill.nta f20=[r25],16;;
1193 ldf.fill.nta f21=[r25],16;;
1194 ldf.fill.nta f22=[r25],16;;
1195 ldf.fill.nta f23=[r25],16;;
1196 ldf.fill.nta f24=[r25],16;;
1197 ldf.fill.nta f25=[r25],16;;
1198 ldf.fill.nta f26=[r25],16;;
1199 ldf.fill.nta f27=[r25],16;;
1200 ldf.fill.nta f28=[r25],16;;
1201 ldf.fill.nta f29=[r25],16;;
1202 ldf.fill.nta f30=[r25],16;;
1203 ldf.fill.nta f31=[r25],16;;
1205 /*
1206 * Now that we have done all the register restores
1207 * we are now ready for the big DIVE to SAL Land
1208 */
1209 ssm psr.ic;;
1210 srlz.d;;
1211 br.ret.sptk.many b0;;
1212 END(ia64_jump_to_sal)
1213 #endif /* CONFIG_HOTPLUG_CPU */
1215 #endif /* CONFIG_SMP */