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powerpc: Delete __cpuinit usage from all users
[linux/fpc-iii.git] / arch / mips / cavium-octeon / octeon-platform.c
blob389512e2abd6198d7ce16851f6ef7f0c6b36c127
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2011 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10 #include <linux/init.h>
11 #include <linux/irq.h>
12 #include <linux/i2c.h>
13 #include <linux/usb.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/platform_device.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_fdt.h>
20 #include <linux/libfdt.h>
21
22 #include <asm/octeon/octeon.h>
23 #include <asm/octeon/cvmx-rnm-defs.h>
24 #include <asm/octeon/cvmx-helper.h>
25 #include <asm/octeon/cvmx-helper-board.h>
26
27 /* Octeon Random Number Generator. */
28 static int __init octeon_rng_device_init(void)
29 {
30 struct platform_device *pd;
31 int ret = 0;
32
33 struct resource rng_resources[] = {
34 {
35 .flags = IORESOURCE_MEM,
36 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
37 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
38 }, {
39 .flags = IORESOURCE_MEM,
40 .start = cvmx_build_io_address(8, 0),
41 .end = cvmx_build_io_address(8, 0) + 0x7
42 }
43 };
44
45 pd = platform_device_alloc("octeon_rng", -1);
46 if (!pd) {
47 ret = -ENOMEM;
48 goto out;
49 }
50
51 ret = platform_device_add_resources(pd, rng_resources,
52 ARRAY_SIZE(rng_resources));
53 if (ret)
54 goto fail;
55
56 ret = platform_device_add(pd);
57 if (ret)
58 goto fail;
59
60 return ret;
61 fail:
62 platform_device_put(pd);
63
64 out:
65 return ret;
66 }
67 device_initcall(octeon_rng_device_init);
68
69 #ifdef CONFIG_USB
70
71 static int __init octeon_ehci_device_init(void)
72 {
73 struct platform_device *pd;
74 int ret = 0;
75
76 struct resource usb_resources[] = {
77 {
78 .flags = IORESOURCE_MEM,
79 }, {
80 .flags = IORESOURCE_IRQ,
81 }
82 };
83
84 /* Only Octeon2 has ehci/ohci */
85 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
86 return 0;
87
88 if (octeon_is_simulation() || usb_disabled())
89 return 0; /* No USB in the simulator. */
90
91 pd = platform_device_alloc("octeon-ehci", 0);
92 if (!pd) {
93 ret = -ENOMEM;
94 goto out;
95 }
96
97 usb_resources[0].start = 0x00016F0000000000ULL;
98 usb_resources[0].end = usb_resources[0].start + 0x100;
99
100 usb_resources[1].start = OCTEON_IRQ_USB0;
101 usb_resources[1].end = OCTEON_IRQ_USB0;
102
103 ret = platform_device_add_resources(pd, usb_resources,
104 ARRAY_SIZE(usb_resources));
105 if (ret)
106 goto fail;
107
108 ret = platform_device_add(pd);
109 if (ret)
110 goto fail;
111
112 return ret;
113 fail:
114 platform_device_put(pd);
115 out:
116 return ret;
117 }
118 device_initcall(octeon_ehci_device_init);
119
120 static int __init octeon_ohci_device_init(void)
121 {
122 struct platform_device *pd;
123 int ret = 0;
124
125 struct resource usb_resources[] = {
126 {
127 .flags = IORESOURCE_MEM,
128 }, {
129 .flags = IORESOURCE_IRQ,
130 }
131 };
132
133 /* Only Octeon2 has ehci/ohci */
134 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
135 return 0;
136
137 if (octeon_is_simulation() || usb_disabled())
138 return 0; /* No USB in the simulator. */
139
140 pd = platform_device_alloc("octeon-ohci", 0);
141 if (!pd) {
142 ret = -ENOMEM;
143 goto out;
144 }
145
146 usb_resources[0].start = 0x00016F0000000400ULL;
147 usb_resources[0].end = usb_resources[0].start + 0x100;
148
149 usb_resources[1].start = OCTEON_IRQ_USB0;
150 usb_resources[1].end = OCTEON_IRQ_USB0;
151
152 ret = platform_device_add_resources(pd, usb_resources,
153 ARRAY_SIZE(usb_resources));
154 if (ret)
155 goto fail;
156
157 ret = platform_device_add(pd);
158 if (ret)
159 goto fail;
160
161 return ret;
162 fail:
163 platform_device_put(pd);
164 out:
165 return ret;
166 }
167 device_initcall(octeon_ohci_device_init);
168
169 #endif /* CONFIG_USB */
170
171 static struct of_device_id __initdata octeon_ids[] = {
172 { .compatible = "simple-bus", },
173 { .compatible = "cavium,octeon-6335-uctl", },
174 { .compatible = "cavium,octeon-3860-bootbus", },
175 { .compatible = "cavium,mdio-mux", },
176 { .compatible = "gpio-leds", },
177 {},
178 };
179
180 static bool __init octeon_has_88e1145(void)
181 {
182 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
183 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
184 !OCTEON_IS_MODEL(OCTEON_CN56XX);
185 }
186
187 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
188 {
189 const __be32 *phy_handle;
190 const __be32 *alt_phy_handle;
191 const __be32 *reg;
192 u32 phandle;
193 int phy;
194 int alt_phy;
195 const char *p;
196 int current_len;
197 char new_name[20];
198
199 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
200 if (!phy_handle)
201 return;
202
203 phandle = be32_to_cpup(phy_handle);
204 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
205
206 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
207 if (alt_phy_handle) {
208 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
209 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
210 } else {
211 alt_phy = -1;
212 }
213
214 if (phy_addr < 0 || phy < 0) {
215 /* Delete the PHY things */
216 fdt_nop_property(initial_boot_params, eth, "phy-handle");
217 /* This one may fail */
218 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
219 if (phy >= 0)
220 fdt_nop_node(initial_boot_params, phy);
221 if (alt_phy >= 0)
222 fdt_nop_node(initial_boot_params, alt_phy);
223 return;
224 }
225
226 if (phy_addr >= 256 && alt_phy > 0) {
227 const struct fdt_property *phy_prop;
228 struct fdt_property *alt_prop;
229 u32 phy_handle_name;
230
231 /* Use the alt phy node instead.*/
232 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
233 phy_handle_name = phy_prop->nameoff;
234 fdt_nop_node(initial_boot_params, phy);
235 fdt_nop_property(initial_boot_params, eth, "phy-handle");
236 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
237 alt_prop->nameoff = phy_handle_name;
238 phy = alt_phy;
239 }
240
241 phy_addr &= 0xff;
242
243 if (octeon_has_88e1145()) {
244 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
245 memset(new_name, 0, sizeof(new_name));
246 strcpy(new_name, "marvell,88e1145");
247 p = fdt_getprop(initial_boot_params, phy, "compatible",
248 &current_len);
249 if (p && current_len >= strlen(new_name))
250 fdt_setprop_inplace(initial_boot_params, phy,
251 "compatible", new_name, current_len);
252 }
253
254 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
255 if (phy_addr == be32_to_cpup(reg))
256 return;
257
258 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
259
260 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
261
262 p = fdt_get_name(initial_boot_params, phy, &current_len);
263 if (p && current_len == strlen(new_name))
264 fdt_set_name(initial_boot_params, phy, new_name);
265 else
266 pr_err("Error: could not rename ethernet phy: <%s>", p);
267 }
268
269 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
270 {
271 u8 new_mac[6];
272 u64 mac = *pmac;
273 int r;
274
275 new_mac[0] = (mac >> 40) & 0xff;
276 new_mac[1] = (mac >> 32) & 0xff;
277 new_mac[2] = (mac >> 24) & 0xff;
278 new_mac[3] = (mac >> 16) & 0xff;
279 new_mac[4] = (mac >> 8) & 0xff;
280 new_mac[5] = mac & 0xff;
281
282 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
283 new_mac, sizeof(new_mac));
284
285 if (r) {
286 pr_err("Setting \"local-mac-address\" failed %d", r);
287 return;
288 }
289 *pmac = mac + 1;
290 }
291
292 static void __init octeon_fdt_rm_ethernet(int node)
293 {
294 const __be32 *phy_handle;
295
296 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
297 if (phy_handle) {
298 u32 ph = be32_to_cpup(phy_handle);
299 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
300 if (p >= 0)
301 fdt_nop_node(initial_boot_params, p);
302 }
303 fdt_nop_node(initial_boot_params, node);
304 }
305
306 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
307 {
308 char name_buffer[20];
309 int eth;
310 int phy_addr;
311 int ipd_port;
312
313 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
314 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
315 if (eth < 0)
316 return;
317 if (p > max) {
318 pr_debug("Deleting port %x:%x\n", i, p);
319 octeon_fdt_rm_ethernet(eth);
320 return;
321 }
322 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
323 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
324 else
325 ipd_port = 16 * i + p;
326
327 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
328 octeon_fdt_set_phy(eth, phy_addr);
329 octeon_fdt_set_mac_addr(eth, pmac);
330 }
331
332 static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
333 {
334 char name_buffer[20];
335 int iface;
336 int p;
337 int count;
338
339 count = cvmx_helper_interface_enumerate(idx);
340
341 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
342 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
343 if (iface < 0)
344 return;
345
346 for (p = 0; p < 16; p++)
347 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
348 }
349
350 int __init octeon_prune_device_tree(void)
351 {
352 int i, max_port, uart_mask;
353 const char *pip_path;
354 const char *alias_prop;
355 char name_buffer[20];
356 int aliases;
357 u64 mac_addr_base;
358
359 if (fdt_check_header(initial_boot_params))
360 panic("Corrupt Device Tree.");
361
362 aliases = fdt_path_offset(initial_boot_params, "/aliases");
363 if (aliases < 0) {
364 pr_err("Error: No /aliases node in device tree.");
365 return -EINVAL;
366 }
367
368
369 mac_addr_base =
370 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
371 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
372 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
373 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
374 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
375 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
376
377 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
378 max_port = 2;
379 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
380 max_port = 1;
381 else
382 max_port = 0;
383
384 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
385 max_port = 0;
386
387 for (i = 0; i < 2; i++) {
388 int mgmt;
389 snprintf(name_buffer, sizeof(name_buffer),
390 "mix%d", i);
391 alias_prop = fdt_getprop(initial_boot_params, aliases,
392 name_buffer, NULL);
393 if (alias_prop) {
394 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
395 if (mgmt < 0)
396 continue;
397 if (i >= max_port) {
398 pr_debug("Deleting mix%d\n", i);
399 octeon_fdt_rm_ethernet(mgmt);
400 fdt_nop_property(initial_boot_params, aliases,
401 name_buffer);
402 } else {
403 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
404 octeon_fdt_set_phy(mgmt, phy_addr);
405 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
406 }
407 }
408 }
409
410 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
411 if (pip_path) {
412 int pip = fdt_path_offset(initial_boot_params, pip_path);
413 if (pip >= 0)
414 for (i = 0; i <= 4; i++)
415 octeon_fdt_pip_iface(pip, i, &mac_addr_base);
416 }
417
418 /* I2C */
419 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
420 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
421 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
422 OCTEON_IS_MODEL(OCTEON_CN56XX))
423 max_port = 2;
424 else
425 max_port = 1;
426
427 for (i = 0; i < 2; i++) {
428 int i2c;
429 snprintf(name_buffer, sizeof(name_buffer),
430 "twsi%d", i);
431 alias_prop = fdt_getprop(initial_boot_params, aliases,
432 name_buffer, NULL);
433
434 if (alias_prop) {
435 i2c = fdt_path_offset(initial_boot_params, alias_prop);
436 if (i2c < 0)
437 continue;
438 if (i >= max_port) {
439 pr_debug("Deleting twsi%d\n", i);
440 fdt_nop_node(initial_boot_params, i2c);
441 fdt_nop_property(initial_boot_params, aliases,
442 name_buffer);
443 }
444 }
445 }
446
447 /* SMI/MDIO */
448 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
449 max_port = 4;
450 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
451 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
452 OCTEON_IS_MODEL(OCTEON_CN56XX))
453 max_port = 2;
454 else
455 max_port = 1;
456
457 for (i = 0; i < 2; i++) {
458 int i2c;
459 snprintf(name_buffer, sizeof(name_buffer),
460 "smi%d", i);
461 alias_prop = fdt_getprop(initial_boot_params, aliases,
462 name_buffer, NULL);
463
464 if (alias_prop) {
465 i2c = fdt_path_offset(initial_boot_params, alias_prop);
466 if (i2c < 0)
467 continue;
468 if (i >= max_port) {
469 pr_debug("Deleting smi%d\n", i);
470 fdt_nop_node(initial_boot_params, i2c);
471 fdt_nop_property(initial_boot_params, aliases,
472 name_buffer);
473 }
474 }
475 }
476
477 /* Serial */
478 uart_mask = 3;
479
480 /* Right now CN52XX is the only chip with a third uart */
481 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
482 uart_mask |= 4; /* uart2 */
483
484 for (i = 0; i < 3; i++) {
485 int uart;
486 snprintf(name_buffer, sizeof(name_buffer),
487 "uart%d", i);
488 alias_prop = fdt_getprop(initial_boot_params, aliases,
489 name_buffer, NULL);
490
491 if (alias_prop) {
492 uart = fdt_path_offset(initial_boot_params, alias_prop);
493 if (uart_mask & (1 << i))
494 continue;
495 pr_debug("Deleting uart%d\n", i);
496 fdt_nop_node(initial_boot_params, uart);
497 fdt_nop_property(initial_boot_params, aliases,
498 name_buffer);
499 }
500 }
501
502 /* Compact Flash */
503 alias_prop = fdt_getprop(initial_boot_params, aliases,
504 "cf0", NULL);
505 if (alias_prop) {
506 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
507 unsigned long base_ptr, region_base, region_size;
508 unsigned long region1_base = 0;
509 unsigned long region1_size = 0;
510 int cs, bootbus;
511 bool is_16bit = false;
512 bool is_true_ide = false;
513 __be32 new_reg[6];
514 __be32 *ranges;
515 int len;
516
517 int cf = fdt_path_offset(initial_boot_params, alias_prop);
518 base_ptr = 0;
519 if (octeon_bootinfo->major_version == 1
520 && octeon_bootinfo->minor_version >= 1) {
521 if (octeon_bootinfo->compact_flash_common_base_addr)
522 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
523 } else {
524 base_ptr = 0x1d000800;
525 }
526
527 if (!base_ptr)
528 goto no_cf;
529
530 /* Find CS0 region. */
531 for (cs = 0; cs < 8; cs++) {
532 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
533 region_base = mio_boot_reg_cfg.s.base << 16;
534 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
535 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
536 && base_ptr < region_base + region_size) {
537 is_16bit = mio_boot_reg_cfg.s.width;
538 break;
539 }
540 }
541 if (cs >= 7) {
542 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
543 goto no_cf;
544 }
545
546 if (!(base_ptr & 0xfffful)) {
547 /*
548 * Boot loader signals availability of DMA (true_ide
549 * mode) by setting low order bits of base_ptr to
550 * zero.
551 */
552
553 /* Asume that CS1 immediately follows. */
554 mio_boot_reg_cfg.u64 =
555 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
556 region1_base = mio_boot_reg_cfg.s.base << 16;
557 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
558 if (!mio_boot_reg_cfg.s.en)
559 goto no_cf;
560 is_true_ide = true;
561
562 } else {
563 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
564 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
565 if (!is_16bit) {
566 __be32 width = cpu_to_be32(8);
567 fdt_setprop_inplace(initial_boot_params, cf,
568 "cavium,bus-width", &width, sizeof(width));
569 }
570 }
571 new_reg[0] = cpu_to_be32(cs);
572 new_reg[1] = cpu_to_be32(0);
573 new_reg[2] = cpu_to_be32(0x10000);
574 new_reg[3] = cpu_to_be32(cs + 1);
575 new_reg[4] = cpu_to_be32(0);
576 new_reg[5] = cpu_to_be32(0x10000);
577 fdt_setprop_inplace(initial_boot_params, cf,
578 "reg", new_reg, sizeof(new_reg));
579
580 bootbus = fdt_parent_offset(initial_boot_params, cf);
581 if (bootbus < 0)
582 goto no_cf;
583 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
584 if (!ranges || len < (5 * 8 * sizeof(__be32)))
585 goto no_cf;
586
587 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
588 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
589 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
590 if (is_true_ide) {
591 cs++;
592 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
593 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
594 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
595 }
596 goto end_cf;
597 no_cf:
598 fdt_nop_node(initial_boot_params, cf);
599
600 end_cf:
601 ;
602 }
603
604 /* 8 char LED */
605 alias_prop = fdt_getprop(initial_boot_params, aliases,
606 "led0", NULL);
607 if (alias_prop) {
608 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
609 unsigned long base_ptr, region_base, region_size;
610 int cs, bootbus;
611 __be32 new_reg[6];
612 __be32 *ranges;
613 int len;
614 int led = fdt_path_offset(initial_boot_params, alias_prop);
615
616 base_ptr = octeon_bootinfo->led_display_base_addr;
617 if (base_ptr == 0)
618 goto no_led;
619 /* Find CS0 region. */
620 for (cs = 0; cs < 8; cs++) {
621 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
622 region_base = mio_boot_reg_cfg.s.base << 16;
623 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
624 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
625 && base_ptr < region_base + region_size)
626 break;
627 }
628
629 if (cs > 7)
630 goto no_led;
631
632 new_reg[0] = cpu_to_be32(cs);
633 new_reg[1] = cpu_to_be32(0x20);
634 new_reg[2] = cpu_to_be32(0x20);
635 new_reg[3] = cpu_to_be32(cs);
636 new_reg[4] = cpu_to_be32(0);
637 new_reg[5] = cpu_to_be32(0x20);
638 fdt_setprop_inplace(initial_boot_params, led,
639 "reg", new_reg, sizeof(new_reg));
640
641 bootbus = fdt_parent_offset(initial_boot_params, led);
642 if (bootbus < 0)
643 goto no_led;
644 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
645 if (!ranges || len < (5 * 8 * sizeof(__be32)))
646 goto no_led;
647
648 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
649 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
650 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
651 goto end_led;
652
653 no_led:
654 fdt_nop_node(initial_boot_params, led);
655 end_led:
656 ;
657 }
658
659 /* OHCI/UHCI USB */
660 alias_prop = fdt_getprop(initial_boot_params, aliases,
661 "uctl", NULL);
662 if (alias_prop) {
663 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
664
665 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
666 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
667 pr_debug("Deleting uctl\n");
668 fdt_nop_node(initial_boot_params, uctl);
669 fdt_nop_property(initial_boot_params, aliases, "uctl");
670 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
671 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
672 /* Missing "refclk-type" defaults to crystal. */
673 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
674 }
675 }
676
677 return 0;
678 }
679
680 static int __init octeon_publish_devices(void)
681 {
682 return of_platform_bus_probe(NULL, octeon_ids, NULL);
683 }
684 device_initcall(octeon_publish_devices);
685
686 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
687 MODULE_LICENSE("GPL");
688 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
Linux with added FPC-III support