2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39 #include <linux/perf_event.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
49 #include <asm/uaccess.h>
50 #include <asm/branch.h>
54 /* Strap kernel emulator for full MIPS IV emulation */
61 /* Function which emulates a floating point instruction. */
63 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
66 #if __mips >= 4 && __mips != 32
67 static int fpux_emu(struct pt_regs
*,
68 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
71 /* Further private data for which no space exists in mips_fpu_struct */
73 #ifdef CONFIG_DEBUG_FS
74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats
, fpuemustats
);
77 /* Control registers */
79 #define FPCREG_RID 0 /* $0 = revision id */
80 #define FPCREG_CSR 31 /* $31 = csr */
82 /* Determine rounding mode from the RM bits of the FCSR */
83 #define modeindex(v) ((v) & FPU_CSR_RM)
85 /* microMIPS bitfields */
86 #define MM_POOL32A_MINOR_MASK 0x3f
87 #define MM_POOL32A_MINOR_SHIFT 0x6
88 #define MM_MIPS32_COND_FC 0x30
90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
91 static const unsigned char ieee_rm
[4] = {
92 [FPU_CSR_RN
] = IEEE754_RN
,
93 [FPU_CSR_RZ
] = IEEE754_RZ
,
94 [FPU_CSR_RU
] = IEEE754_RU
,
95 [FPU_CSR_RD
] = IEEE754_RD
,
97 /* Convert IEEE library modes to Mips rounding mode (0..3). */
98 static const unsigned char mips_rm
[4] = {
99 [IEEE754_RN
] = FPU_CSR_RN
,
100 [IEEE754_RZ
] = FPU_CSR_RZ
,
101 [IEEE754_RD
] = FPU_CSR_RD
,
102 [IEEE754_RU
] = FPU_CSR_RU
,
106 /* convert condition code register number to csr bit */
107 static const unsigned int fpucondbit
[8] = {
119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
120 static const unsigned int reg16to32map
[8] = {16, 17, 2, 3, 4, 5, 6, 7};
122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
123 static const int sd_format
[] = {16, 17, 0, 0, 0, 0, 0, 0};
124 static const int sdps_format
[] = {16, 17, 22, 0, 0, 0, 0, 0};
125 static const int dwl_format
[] = {17, 20, 21, 0, 0, 0, 0, 0};
126 static const int swl_format
[] = {16, 20, 21, 0, 0, 0, 0, 0};
129 * This functions translates a 32-bit microMIPS instruction
130 * into a 32-bit MIPS32 instruction. Returns 0 on success
131 * and SIGILL otherwise.
133 static int microMIPS32_to_MIPS32(union mips_instruction
*insn_ptr
)
135 union mips_instruction insn
= *insn_ptr
;
136 union mips_instruction mips32_insn
= insn
;
139 switch (insn
.mm_i_format
.opcode
) {
141 mips32_insn
.mm_i_format
.opcode
= ldc1_op
;
142 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
143 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
146 mips32_insn
.mm_i_format
.opcode
= lwc1_op
;
147 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
148 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
151 mips32_insn
.mm_i_format
.opcode
= sdc1_op
;
152 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
153 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
156 mips32_insn
.mm_i_format
.opcode
= swc1_op
;
157 mips32_insn
.mm_i_format
.rt
= insn
.mm_i_format
.rs
;
158 mips32_insn
.mm_i_format
.rs
= insn
.mm_i_format
.rt
;
161 /* NOTE: offset is << by 1 if in microMIPS mode. */
162 if ((insn
.mm_i_format
.rt
== mm_bc1f_op
) ||
163 (insn
.mm_i_format
.rt
== mm_bc1t_op
)) {
164 mips32_insn
.fb_format
.opcode
= cop1_op
;
165 mips32_insn
.fb_format
.bc
= bc_op
;
166 mips32_insn
.fb_format
.flag
=
167 (insn
.mm_i_format
.rt
== mm_bc1t_op
) ? 1 : 0;
172 switch (insn
.mm_fp0_format
.func
) {
181 op
= insn
.mm_fp0_format
.func
;
182 if (op
== mm_32f_01_op
)
184 else if (op
== mm_32f_11_op
)
186 else if (op
== mm_32f_02_op
)
188 else if (op
== mm_32f_12_op
)
190 else if (op
== mm_32f_41_op
)
192 else if (op
== mm_32f_51_op
)
194 else if (op
== mm_32f_42_op
)
198 mips32_insn
.fp6_format
.opcode
= cop1x_op
;
199 mips32_insn
.fp6_format
.fr
= insn
.mm_fp6_format
.fr
;
200 mips32_insn
.fp6_format
.ft
= insn
.mm_fp6_format
.ft
;
201 mips32_insn
.fp6_format
.fs
= insn
.mm_fp6_format
.fs
;
202 mips32_insn
.fp6_format
.fd
= insn
.mm_fp6_format
.fd
;
203 mips32_insn
.fp6_format
.func
= func
;
206 func
= -1; /* Invalid */
207 op
= insn
.mm_fp5_format
.op
& 0x7;
208 if (op
== mm_ldxc1_op
)
210 else if (op
== mm_sdxc1_op
)
212 else if (op
== mm_lwxc1_op
)
214 else if (op
== mm_swxc1_op
)
218 mips32_insn
.r_format
.opcode
= cop1x_op
;
219 mips32_insn
.r_format
.rs
=
220 insn
.mm_fp5_format
.base
;
221 mips32_insn
.r_format
.rt
=
222 insn
.mm_fp5_format
.index
;
223 mips32_insn
.r_format
.rd
= 0;
224 mips32_insn
.r_format
.re
= insn
.mm_fp5_format
.fd
;
225 mips32_insn
.r_format
.func
= func
;
230 op
= -1; /* Invalid */
231 if (insn
.mm_fp2_format
.op
== mm_fmovt_op
)
233 else if (insn
.mm_fp2_format
.op
== mm_fmovf_op
)
236 mips32_insn
.fp0_format
.opcode
= cop1_op
;
237 mips32_insn
.fp0_format
.fmt
=
238 sdps_format
[insn
.mm_fp2_format
.fmt
];
239 mips32_insn
.fp0_format
.ft
=
240 (insn
.mm_fp2_format
.cc
<<2) + op
;
241 mips32_insn
.fp0_format
.fs
=
242 insn
.mm_fp2_format
.fs
;
243 mips32_insn
.fp0_format
.fd
=
244 insn
.mm_fp2_format
.fd
;
245 mips32_insn
.fp0_format
.func
= fmovc_op
;
250 func
= -1; /* Invalid */
251 if (insn
.mm_fp0_format
.op
== mm_fadd_op
)
253 else if (insn
.mm_fp0_format
.op
== mm_fsub_op
)
255 else if (insn
.mm_fp0_format
.op
== mm_fmul_op
)
257 else if (insn
.mm_fp0_format
.op
== mm_fdiv_op
)
260 mips32_insn
.fp0_format
.opcode
= cop1_op
;
261 mips32_insn
.fp0_format
.fmt
=
262 sdps_format
[insn
.mm_fp0_format
.fmt
];
263 mips32_insn
.fp0_format
.ft
=
264 insn
.mm_fp0_format
.ft
;
265 mips32_insn
.fp0_format
.fs
=
266 insn
.mm_fp0_format
.fs
;
267 mips32_insn
.fp0_format
.fd
=
268 insn
.mm_fp0_format
.fd
;
269 mips32_insn
.fp0_format
.func
= func
;
274 func
= -1; /* Invalid */
275 if (insn
.mm_fp0_format
.op
== mm_fmovn_op
)
277 else if (insn
.mm_fp0_format
.op
== mm_fmovz_op
)
280 mips32_insn
.fp0_format
.opcode
= cop1_op
;
281 mips32_insn
.fp0_format
.fmt
=
282 sdps_format
[insn
.mm_fp0_format
.fmt
];
283 mips32_insn
.fp0_format
.ft
=
284 insn
.mm_fp0_format
.ft
;
285 mips32_insn
.fp0_format
.fs
=
286 insn
.mm_fp0_format
.fs
;
287 mips32_insn
.fp0_format
.fd
=
288 insn
.mm_fp0_format
.fd
;
289 mips32_insn
.fp0_format
.func
= func
;
293 case mm_32f_73_op
: /* POOL32FXF */
294 switch (insn
.mm_fp1_format
.op
) {
299 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
304 mips32_insn
.r_format
.opcode
= spec_op
;
305 mips32_insn
.r_format
.rs
= insn
.mm_fp4_format
.fs
;
306 mips32_insn
.r_format
.rt
=
307 (insn
.mm_fp4_format
.cc
<< 2) + op
;
308 mips32_insn
.r_format
.rd
= insn
.mm_fp4_format
.rt
;
309 mips32_insn
.r_format
.re
= 0;
310 mips32_insn
.r_format
.func
= movc_op
;
316 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
319 fmt
= swl_format
[insn
.mm_fp3_format
.fmt
];
322 fmt
= dwl_format
[insn
.mm_fp3_format
.fmt
];
324 mips32_insn
.fp0_format
.opcode
= cop1_op
;
325 mips32_insn
.fp0_format
.fmt
= fmt
;
326 mips32_insn
.fp0_format
.ft
= 0;
327 mips32_insn
.fp0_format
.fs
=
328 insn
.mm_fp3_format
.fs
;
329 mips32_insn
.fp0_format
.fd
=
330 insn
.mm_fp3_format
.rt
;
331 mips32_insn
.fp0_format
.func
= func
;
339 if ((insn
.mm_fp1_format
.op
& 0x7f) ==
342 else if ((insn
.mm_fp1_format
.op
& 0x7f) ==
347 mips32_insn
.fp0_format
.opcode
= cop1_op
;
348 mips32_insn
.fp0_format
.fmt
=
349 sdps_format
[insn
.mm_fp3_format
.fmt
];
350 mips32_insn
.fp0_format
.ft
= 0;
351 mips32_insn
.fp0_format
.fs
=
352 insn
.mm_fp3_format
.fs
;
353 mips32_insn
.fp0_format
.fd
=
354 insn
.mm_fp3_format
.rt
;
355 mips32_insn
.fp0_format
.func
= func
;
367 if (insn
.mm_fp1_format
.op
== mm_ffloorl_op
)
369 else if (insn
.mm_fp1_format
.op
== mm_ffloorw_op
)
371 else if (insn
.mm_fp1_format
.op
== mm_fceill_op
)
373 else if (insn
.mm_fp1_format
.op
== mm_fceilw_op
)
375 else if (insn
.mm_fp1_format
.op
== mm_ftruncl_op
)
377 else if (insn
.mm_fp1_format
.op
== mm_ftruncw_op
)
379 else if (insn
.mm_fp1_format
.op
== mm_froundl_op
)
381 else if (insn
.mm_fp1_format
.op
== mm_froundw_op
)
383 else if (insn
.mm_fp1_format
.op
== mm_fcvtl_op
)
387 mips32_insn
.fp0_format
.opcode
= cop1_op
;
388 mips32_insn
.fp0_format
.fmt
=
389 sd_format
[insn
.mm_fp1_format
.fmt
];
390 mips32_insn
.fp0_format
.ft
= 0;
391 mips32_insn
.fp0_format
.fs
=
392 insn
.mm_fp1_format
.fs
;
393 mips32_insn
.fp0_format
.fd
=
394 insn
.mm_fp1_format
.rt
;
395 mips32_insn
.fp0_format
.func
= func
;
400 if (insn
.mm_fp1_format
.op
== mm_frsqrt_op
)
402 else if (insn
.mm_fp1_format
.op
== mm_fsqrt_op
)
406 mips32_insn
.fp0_format
.opcode
= cop1_op
;
407 mips32_insn
.fp0_format
.fmt
=
408 sdps_format
[insn
.mm_fp1_format
.fmt
];
409 mips32_insn
.fp0_format
.ft
= 0;
410 mips32_insn
.fp0_format
.fs
=
411 insn
.mm_fp1_format
.fs
;
412 mips32_insn
.fp0_format
.fd
=
413 insn
.mm_fp1_format
.rt
;
414 mips32_insn
.fp0_format
.func
= func
;
420 if (insn
.mm_fp1_format
.op
== mm_mfc1_op
)
422 else if (insn
.mm_fp1_format
.op
== mm_mtc1_op
)
424 else if (insn
.mm_fp1_format
.op
== mm_cfc1_op
)
428 mips32_insn
.fp1_format
.opcode
= cop1_op
;
429 mips32_insn
.fp1_format
.op
= op
;
430 mips32_insn
.fp1_format
.rt
=
431 insn
.mm_fp1_format
.rt
;
432 mips32_insn
.fp1_format
.fs
=
433 insn
.mm_fp1_format
.fs
;
434 mips32_insn
.fp1_format
.fd
= 0;
435 mips32_insn
.fp1_format
.func
= 0;
442 case mm_32f_74_op
: /* c.cond.fmt */
443 mips32_insn
.fp0_format
.opcode
= cop1_op
;
444 mips32_insn
.fp0_format
.fmt
=
445 sdps_format
[insn
.mm_fp4_format
.fmt
];
446 mips32_insn
.fp0_format
.ft
= insn
.mm_fp4_format
.rt
;
447 mips32_insn
.fp0_format
.fs
= insn
.mm_fp4_format
.fs
;
448 mips32_insn
.fp0_format
.fd
= insn
.mm_fp4_format
.cc
<< 2;
449 mips32_insn
.fp0_format
.func
=
450 insn
.mm_fp4_format
.cond
| MM_MIPS32_COND_FC
;
462 *insn_ptr
= mips32_insn
;
466 int mm_isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
467 unsigned long *contpc
)
469 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
474 switch (insn
.mm_i_format
.opcode
) {
476 if ((insn
.mm_i_format
.simmediate
& MM_POOL32A_MINOR_MASK
) ==
478 switch (insn
.mm_i_format
.simmediate
>>
479 MM_POOL32A_MINOR_SHIFT
) {
484 if (insn
.mm_i_format
.rt
!= 0) /* Not mm_jr */
485 regs
->regs
[insn
.mm_i_format
.rt
] =
488 dec_insn
.next_pc_inc
;
489 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
496 switch (insn
.mm_i_format
.rt
) {
499 regs
->regs
[31] = regs
->cp0_epc
+
501 dec_insn
.next_pc_inc
;
504 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] < 0)
505 *contpc
= regs
->cp0_epc
+
507 (insn
.mm_i_format
.simmediate
<< 1);
509 *contpc
= regs
->cp0_epc
+
511 dec_insn
.next_pc_inc
;
516 regs
->regs
[31] = regs
->cp0_epc
+
518 dec_insn
.next_pc_inc
;
521 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] >= 0)
522 *contpc
= regs
->cp0_epc
+
524 (insn
.mm_i_format
.simmediate
<< 1);
526 *contpc
= regs
->cp0_epc
+
528 dec_insn
.next_pc_inc
;
532 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
533 *contpc
= regs
->cp0_epc
+
535 (insn
.mm_i_format
.simmediate
<< 1);
537 *contpc
= regs
->cp0_epc
+
539 dec_insn
.next_pc_inc
;
543 if ((long)regs
->regs
[insn
.mm_i_format
.rs
] <= 0)
544 *contpc
= regs
->cp0_epc
+
546 (insn
.mm_i_format
.simmediate
<< 1);
548 *contpc
= regs
->cp0_epc
+
550 dec_insn
.next_pc_inc
;
561 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
563 fcr31
= current
->thread
.fpu
.fcr31
;
569 bit
= (insn
.mm_i_format
.rs
>> 2);
572 if (fcr31
& (1 << bit
))
573 *contpc
= regs
->cp0_epc
+
575 (insn
.mm_i_format
.simmediate
<< 1);
577 *contpc
= regs
->cp0_epc
+
578 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
584 switch (insn
.mm_i_format
.rt
) {
587 regs
->regs
[31] = regs
->cp0_epc
+
588 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
591 *contpc
= regs
->regs
[insn
.mm_i_format
.rs
];
597 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] == 0)
598 *contpc
= regs
->cp0_epc
+
600 (insn
.mm_b1_format
.simmediate
<< 1);
602 *contpc
= regs
->cp0_epc
+
603 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
607 if ((long)regs
->regs
[reg16to32map
[insn
.mm_b1_format
.rs
]] != 0)
608 *contpc
= regs
->cp0_epc
+
610 (insn
.mm_b1_format
.simmediate
<< 1);
612 *contpc
= regs
->cp0_epc
+
613 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
617 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
+
618 (insn
.mm_b0_format
.simmediate
<< 1);
622 if (regs
->regs
[insn
.mm_i_format
.rs
] ==
623 regs
->regs
[insn
.mm_i_format
.rt
])
624 *contpc
= regs
->cp0_epc
+
626 (insn
.mm_i_format
.simmediate
<< 1);
628 *contpc
= regs
->cp0_epc
+
630 dec_insn
.next_pc_inc
;
634 if (regs
->regs
[insn
.mm_i_format
.rs
] !=
635 regs
->regs
[insn
.mm_i_format
.rt
])
636 *contpc
= regs
->cp0_epc
+
638 (insn
.mm_i_format
.simmediate
<< 1);
640 *contpc
= regs
->cp0_epc
+
641 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
645 regs
->regs
[31] = regs
->cp0_epc
+
646 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
647 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
650 *contpc
|= (insn
.j_format
.target
<< 2);
655 regs
->regs
[31] = regs
->cp0_epc
+
656 dec_insn
.pc_inc
+ dec_insn
.next_pc_inc
;
659 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
662 *contpc
|= (insn
.j_format
.target
<< 1);
663 set_isa16_mode(*contpc
);
671 * Redundant with logic already in kernel/branch.c,
672 * embedded in compute_return_epc. At some point,
673 * a single subroutine should be used across both
676 static int isBranchInstr(struct pt_regs
*regs
, struct mm_decoded_insn dec_insn
,
677 unsigned long *contpc
)
679 union mips_instruction insn
= (union mips_instruction
)dec_insn
.insn
;
681 unsigned int bit
= 0;
683 switch (insn
.i_format
.opcode
) {
685 switch (insn
.r_format
.func
) {
687 regs
->regs
[insn
.r_format
.rd
] =
688 regs
->cp0_epc
+ dec_insn
.pc_inc
+
689 dec_insn
.next_pc_inc
;
692 *contpc
= regs
->regs
[insn
.r_format
.rs
];
698 switch (insn
.i_format
.rt
) {
701 regs
->regs
[31] = regs
->cp0_epc
+
703 dec_insn
.next_pc_inc
;
707 if ((long)regs
->regs
[insn
.i_format
.rs
] < 0)
708 *contpc
= regs
->cp0_epc
+
710 (insn
.i_format
.simmediate
<< 2);
712 *contpc
= regs
->cp0_epc
+
714 dec_insn
.next_pc_inc
;
719 regs
->regs
[31] = regs
->cp0_epc
+
721 dec_insn
.next_pc_inc
;
725 if ((long)regs
->regs
[insn
.i_format
.rs
] >= 0)
726 *contpc
= regs
->cp0_epc
+
728 (insn
.i_format
.simmediate
<< 2);
730 *contpc
= regs
->cp0_epc
+
732 dec_insn
.next_pc_inc
;
740 regs
->regs
[31] = regs
->cp0_epc
+
742 dec_insn
.next_pc_inc
;
745 *contpc
= regs
->cp0_epc
+ dec_insn
.pc_inc
;
748 *contpc
|= (insn
.j_format
.target
<< 2);
749 /* Set microMIPS mode bit: XOR for jalx. */
755 if (regs
->regs
[insn
.i_format
.rs
] ==
756 regs
->regs
[insn
.i_format
.rt
])
757 *contpc
= regs
->cp0_epc
+
759 (insn
.i_format
.simmediate
<< 2);
761 *contpc
= regs
->cp0_epc
+
763 dec_insn
.next_pc_inc
;
768 if (regs
->regs
[insn
.i_format
.rs
] !=
769 regs
->regs
[insn
.i_format
.rt
])
770 *contpc
= regs
->cp0_epc
+
772 (insn
.i_format
.simmediate
<< 2);
774 *contpc
= regs
->cp0_epc
+
776 dec_insn
.next_pc_inc
;
781 if ((long)regs
->regs
[insn
.i_format
.rs
] <= 0)
782 *contpc
= regs
->cp0_epc
+
784 (insn
.i_format
.simmediate
<< 2);
786 *contpc
= regs
->cp0_epc
+
788 dec_insn
.next_pc_inc
;
793 if ((long)regs
->regs
[insn
.i_format
.rs
] > 0)
794 *contpc
= regs
->cp0_epc
+
796 (insn
.i_format
.simmediate
<< 2);
798 *contpc
= regs
->cp0_epc
+
800 dec_insn
.next_pc_inc
;
807 if (insn
.i_format
.rs
== bc_op
) {
810 asm volatile("cfc1\t%0,$31" : "=r" (fcr31
));
812 fcr31
= current
->thread
.fpu
.fcr31
;
815 bit
= (insn
.i_format
.rt
>> 2);
818 switch (insn
.i_format
.rt
& 3) {
821 if (~fcr31
& (1 << bit
))
822 *contpc
= regs
->cp0_epc
+
824 (insn
.i_format
.simmediate
<< 2);
826 *contpc
= regs
->cp0_epc
+
828 dec_insn
.next_pc_inc
;
833 if (fcr31
& (1 << bit
))
834 *contpc
= regs
->cp0_epc
+
836 (insn
.i_format
.simmediate
<< 2);
838 *contpc
= regs
->cp0_epc
+
840 dec_insn
.next_pc_inc
;
851 * In the Linux kernel, we support selection of FPR format on the
852 * basis of the Status.FR bit. If an FPU is not present, the FR bit
853 * is hardwired to zero, which would imply a 32-bit FPU even for
854 * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
855 * FPU emu is slow and bulky and optimizing this function offers fairly
856 * sizeable benefits so we try to be clever and make this function return
857 * a constant whenever possible, that is on 64-bit kernels without O32
858 * compatibility enabled and on 32-bit kernels.
860 static inline int cop1_64bit(struct pt_regs
*xcp
)
862 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
864 #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
865 return !test_thread_flag(TIF_32BIT_REGS
);
871 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
872 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
874 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
875 cop1_64bit(xcp) || !(x & 1) ? \
876 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
877 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
879 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
880 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
882 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
883 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
884 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
885 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
888 * Emulate the single floating point instruction pointed at by EPC.
889 * Two instructions if the instruction is in a branch delay slot.
892 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
893 struct mm_decoded_insn dec_insn
, void *__user
*fault_addr
)
896 unsigned long contpc
= xcp
->cp0_epc
+ dec_insn
.pc_inc
;
900 /* XXX NEC Vr54xx bug workaround */
901 if (xcp
->cp0_cause
& CAUSEF_BD
) {
902 if (dec_insn
.micro_mips_mode
) {
903 if (!mm_isBranchInstr(xcp
, dec_insn
, &contpc
))
904 xcp
->cp0_cause
&= ~CAUSEF_BD
;
906 if (!isBranchInstr(xcp
, dec_insn
, &contpc
))
907 xcp
->cp0_cause
&= ~CAUSEF_BD
;
911 if (xcp
->cp0_cause
& CAUSEF_BD
) {
913 * The instruction to be emulated is in a branch delay slot
914 * which means that we have to emulate the branch instruction
915 * BEFORE we do the cop1 instruction.
917 * This branch could be a COP1 branch, but in that case we
918 * would have had a trap for that instruction, and would not
919 * come through this route.
921 * Linux MIPS branch emulator operates on context, updating the
924 ir
= dec_insn
.next_insn
; /* process delay slot instr */
925 pc_inc
= dec_insn
.next_pc_inc
;
927 ir
= dec_insn
.insn
; /* process current instr */
928 pc_inc
= dec_insn
.pc_inc
;
932 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
933 * instructions, we want to convert microMIPS FPU instructions
934 * into MIPS32 instructions so that we could reuse all of the
935 * FPU emulation code.
937 * NOTE: We cannot do this for branch instructions since they
938 * are not a subset. Example: Cannot emulate a 16-bit
939 * aligned target address with a MIPS32 instruction.
941 if (dec_insn
.micro_mips_mode
) {
943 * If next instruction is a 16-bit instruction, then it
944 * it cannot be a FPU instruction. This could happen
945 * since we can be called for non-FPU instructions.
948 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
)
954 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
, 1, xcp
, 0);
955 MIPS_FPU_EMU_INC_STATS(emulated
);
956 switch (MIPSInst_OPCODE(ir
)) {
958 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
962 MIPS_FPU_EMU_INC_STATS(loads
);
964 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
965 MIPS_FPU_EMU_INC_STATS(errors
);
969 if (__get_user(val
, va
)) {
970 MIPS_FPU_EMU_INC_STATS(errors
);
974 DITOREG(val
, MIPSInst_RT(ir
));
979 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
983 MIPS_FPU_EMU_INC_STATS(stores
);
984 DIFROMREG(val
, MIPSInst_RT(ir
));
985 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
986 MIPS_FPU_EMU_INC_STATS(errors
);
990 if (__put_user(val
, va
)) {
991 MIPS_FPU_EMU_INC_STATS(errors
);
999 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1003 MIPS_FPU_EMU_INC_STATS(loads
);
1004 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1005 MIPS_FPU_EMU_INC_STATS(errors
);
1009 if (__get_user(val
, va
)) {
1010 MIPS_FPU_EMU_INC_STATS(errors
);
1014 SITOREG(val
, MIPSInst_RT(ir
));
1019 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
1023 MIPS_FPU_EMU_INC_STATS(stores
);
1024 SIFROMREG(val
, MIPSInst_RT(ir
));
1025 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1026 MIPS_FPU_EMU_INC_STATS(errors
);
1030 if (__put_user(val
, va
)) {
1031 MIPS_FPU_EMU_INC_STATS(errors
);
1039 switch (MIPSInst_RS(ir
)) {
1041 #if defined(__mips64)
1043 /* copregister fs -> gpr[rt] */
1044 if (MIPSInst_RT(ir
) != 0) {
1045 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1051 /* copregister fs <- rt */
1052 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1057 /* copregister rd -> gpr[rt] */
1058 if (MIPSInst_RT(ir
) != 0) {
1059 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
1065 /* copregister rd <- rt */
1066 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
1070 /* cop control register rd -> gpr[rt] */
1073 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1075 value
= (value
& ~FPU_CSR_RM
) |
1076 mips_rm
[modeindex(value
)];
1078 printk("%p gpr[%d]<-csr=%08x\n",
1079 (void *) (xcp
->cp0_epc
),
1080 MIPSInst_RT(ir
), value
);
1083 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
1087 if (MIPSInst_RT(ir
))
1088 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
1093 /* copregister rd <- rt */
1096 if (MIPSInst_RT(ir
) == 0)
1099 value
= xcp
->regs
[MIPSInst_RT(ir
)];
1101 /* we only have one writable control reg
1103 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
1105 printk("%p gpr[%d]->csr=%08x\n",
1106 (void *) (xcp
->cp0_epc
),
1107 MIPSInst_RT(ir
), value
);
1111 * Don't write reserved bits,
1112 * and convert to ieee library modes
1114 ctx
->fcr31
= (value
&
1115 ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
1116 ieee_rm
[modeindex(value
)];
1118 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1127 if (xcp
->cp0_cause
& CAUSEF_BD
)
1131 cond
= ctx
->fcr31
& fpucondbit
[MIPSInst_RT(ir
) >> 2];
1133 cond
= ctx
->fcr31
& FPU_CSR_COND
;
1135 switch (MIPSInst_RT(ir
) & 3) {
1146 /* thats an illegal instruction */
1150 xcp
->cp0_cause
|= CAUSEF_BD
;
1152 /* branch taken: emulate dslot
1155 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1157 contpc
= MIPSInst_SIMM(ir
);
1158 ir
= dec_insn
.next_insn
;
1159 if (dec_insn
.micro_mips_mode
) {
1160 contpc
= (xcp
->cp0_epc
+ (contpc
<< 1));
1162 /* If 16-bit instruction, not FPU. */
1163 if ((dec_insn
.next_pc_inc
== 2) ||
1164 (microMIPS32_to_MIPS32((union mips_instruction
*)&ir
) == SIGILL
)) {
1167 * Since this instruction will
1168 * be put on the stack with
1169 * 32-bit words, get around
1170 * this problem by putting a
1171 * NOP16 as the second one.
1173 if (dec_insn
.next_pc_inc
== 2)
1174 ir
= (ir
& (~0xffff)) | MM_NOP16
;
1177 * Single step the non-CP1
1178 * instruction in the dslot.
1180 return mips_dsemul(xcp
, ir
, contpc
);
1183 contpc
= (xcp
->cp0_epc
+ (contpc
<< 2));
1185 switch (MIPSInst_OPCODE(ir
)) {
1188 #if (__mips >= 2 || defined(__mips64))
1193 #if __mips >= 4 && __mips != 32
1196 /* its one of ours */
1200 if (MIPSInst_FUNC(ir
) == movc_op
)
1207 * Single step the non-cp1
1208 * instruction in the dslot
1210 return mips_dsemul(xcp
, ir
, contpc
);
1213 /* branch not taken */
1216 * branch likely nullifies
1217 * dslot if not taken
1219 xcp
->cp0_epc
+= dec_insn
.pc_inc
;
1220 contpc
+= dec_insn
.pc_inc
;
1222 * else continue & execute
1223 * dslot as normal insn
1231 if (!(MIPSInst_RS(ir
) & 0x10))
1236 /* a real fpu computation instruction */
1237 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
1243 #if __mips >= 4 && __mips != 32
1245 int sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
1254 if (MIPSInst_FUNC(ir
) != movc_op
)
1256 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
1257 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
1258 xcp
->regs
[MIPSInst_RD(ir
)] =
1259 xcp
->regs
[MIPSInst_RS(ir
)];
1268 xcp
->cp0_epc
= contpc
;
1269 xcp
->cp0_cause
&= ~CAUSEF_BD
;
1275 * Conversion table from MIPS compare ops 48-63
1276 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1278 static const unsigned char cmptab
[8] = {
1279 0, /* cmp_0 (sig) cmp_sf */
1280 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
1281 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
1282 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
1283 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
1284 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
1285 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
1286 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
1290 #if __mips >= 4 && __mips != 32
1293 * Additional MIPS4 instructions
1296 #define DEF3OP(name, p, f1, f2, f3) \
1297 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1300 struct _ieee754_csr ieee754_csr_save; \
1302 ieee754_csr_save = ieee754_csr; \
1304 ieee754_csr_save.cx |= ieee754_csr.cx; \
1305 ieee754_csr_save.sx |= ieee754_csr.sx; \
1307 ieee754_csr.cx |= ieee754_csr_save.cx; \
1308 ieee754_csr.sx |= ieee754_csr_save.sx; \
1312 static ieee754dp
fpemu_dp_recip(ieee754dp d
)
1314 return ieee754dp_div(ieee754dp_one(0), d
);
1317 static ieee754dp
fpemu_dp_rsqrt(ieee754dp d
)
1319 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
1322 static ieee754sp
fpemu_sp_recip(ieee754sp s
)
1324 return ieee754sp_div(ieee754sp_one(0), s
);
1327 static ieee754sp
fpemu_sp_rsqrt(ieee754sp s
)
1329 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
1332 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
, );
1333 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
, );
1334 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
1335 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
1336 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
, );
1337 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
, );
1338 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
1339 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
1341 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1342 mips_instruction ir
, void *__user
*fault_addr
)
1344 unsigned rcsr
= 0; /* resulting csr */
1346 MIPS_FPU_EMU_INC_STATS(cp1xops
);
1348 switch (MIPSInst_FMA_FFMT(ir
)) {
1349 case s_fmt
:{ /* 0 */
1351 ieee754sp(*handler
) (ieee754sp
, ieee754sp
, ieee754sp
);
1352 ieee754sp fd
, fr
, fs
, ft
;
1356 switch (MIPSInst_FUNC(ir
)) {
1358 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1359 xcp
->regs
[MIPSInst_FT(ir
)]);
1361 MIPS_FPU_EMU_INC_STATS(loads
);
1362 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
1363 MIPS_FPU_EMU_INC_STATS(errors
);
1367 if (__get_user(val
, va
)) {
1368 MIPS_FPU_EMU_INC_STATS(errors
);
1372 SITOREG(val
, MIPSInst_FD(ir
));
1376 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1377 xcp
->regs
[MIPSInst_FT(ir
)]);
1379 MIPS_FPU_EMU_INC_STATS(stores
);
1381 SIFROMREG(val
, MIPSInst_FS(ir
));
1382 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
1383 MIPS_FPU_EMU_INC_STATS(errors
);
1387 if (put_user(val
, va
)) {
1388 MIPS_FPU_EMU_INC_STATS(errors
);
1395 handler
= fpemu_sp_madd
;
1398 handler
= fpemu_sp_msub
;
1401 handler
= fpemu_sp_nmadd
;
1404 handler
= fpemu_sp_nmsub
;
1408 SPFROMREG(fr
, MIPSInst_FR(ir
));
1409 SPFROMREG(fs
, MIPSInst_FS(ir
));
1410 SPFROMREG(ft
, MIPSInst_FT(ir
));
1411 fd
= (*handler
) (fr
, fs
, ft
);
1412 SPTOREG(fd
, MIPSInst_FD(ir
));
1415 if (ieee754_cxtest(IEEE754_INEXACT
))
1416 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1417 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1418 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1419 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1420 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1421 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1422 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1424 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1425 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1426 /*printk ("SIGFPE: fpu csr = %08x\n",
1439 case d_fmt
:{ /* 1 */
1440 ieee754dp(*handler
) (ieee754dp
, ieee754dp
, ieee754dp
);
1441 ieee754dp fd
, fr
, fs
, ft
;
1445 switch (MIPSInst_FUNC(ir
)) {
1447 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1448 xcp
->regs
[MIPSInst_FT(ir
)]);
1450 MIPS_FPU_EMU_INC_STATS(loads
);
1451 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
1452 MIPS_FPU_EMU_INC_STATS(errors
);
1456 if (__get_user(val
, va
)) {
1457 MIPS_FPU_EMU_INC_STATS(errors
);
1461 DITOREG(val
, MIPSInst_FD(ir
));
1465 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
1466 xcp
->regs
[MIPSInst_FT(ir
)]);
1468 MIPS_FPU_EMU_INC_STATS(stores
);
1469 DIFROMREG(val
, MIPSInst_FS(ir
));
1470 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
1471 MIPS_FPU_EMU_INC_STATS(errors
);
1475 if (__put_user(val
, va
)) {
1476 MIPS_FPU_EMU_INC_STATS(errors
);
1483 handler
= fpemu_dp_madd
;
1486 handler
= fpemu_dp_msub
;
1489 handler
= fpemu_dp_nmadd
;
1492 handler
= fpemu_dp_nmsub
;
1496 DPFROMREG(fr
, MIPSInst_FR(ir
));
1497 DPFROMREG(fs
, MIPSInst_FS(ir
));
1498 DPFROMREG(ft
, MIPSInst_FT(ir
));
1499 fd
= (*handler
) (fr
, fs
, ft
);
1500 DPTOREG(fd
, MIPSInst_FD(ir
));
1510 if (MIPSInst_FUNC(ir
) != pfetch_op
) {
1513 /* ignore prefx operation */
1527 * Emulate a single COP1 arithmetic instruction.
1529 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1530 mips_instruction ir
)
1532 int rfmt
; /* resulting format */
1533 unsigned rcsr
= 0; /* resulting csr */
1542 } rv
; /* resulting value */
1544 MIPS_FPU_EMU_INC_STATS(cp1ops
);
1545 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
1546 case s_fmt
:{ /* 0 */
1548 ieee754sp(*b
) (ieee754sp
, ieee754sp
);
1549 ieee754sp(*u
) (ieee754sp
);
1552 switch (MIPSInst_FUNC(ir
)) {
1555 handler
.b
= ieee754sp_add
;
1558 handler
.b
= ieee754sp_sub
;
1561 handler
.b
= ieee754sp_mul
;
1564 handler
.b
= ieee754sp_div
;
1568 #if __mips >= 2 || defined(__mips64)
1570 handler
.u
= ieee754sp_sqrt
;
1573 #if __mips >= 4 && __mips != 32
1575 handler
.u
= fpemu_sp_rsqrt
;
1578 handler
.u
= fpemu_sp_recip
;
1583 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1584 if (((ctx
->fcr31
& cond
) != 0) !=
1585 ((MIPSInst_FT(ir
) & 1) != 0))
1587 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1590 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1592 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1595 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1597 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1601 handler
.u
= ieee754sp_abs
;
1604 handler
.u
= ieee754sp_neg
;
1608 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
1611 /* binary op on handler */
1616 SPFROMREG(fs
, MIPSInst_FS(ir
));
1617 SPFROMREG(ft
, MIPSInst_FT(ir
));
1619 rv
.s
= (*handler
.b
) (fs
, ft
);
1626 SPFROMREG(fs
, MIPSInst_FS(ir
));
1627 rv
.s
= (*handler
.u
) (fs
);
1631 if (ieee754_cxtest(IEEE754_INEXACT
))
1632 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
1633 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
1634 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
1635 if (ieee754_cxtest(IEEE754_OVERFLOW
))
1636 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
1637 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
))
1638 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
1639 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
1640 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1643 /* unary conv ops */
1645 return SIGILL
; /* not defined */
1649 SPFROMREG(fs
, MIPSInst_FS(ir
));
1650 rv
.d
= ieee754dp_fsp(fs
);
1657 SPFROMREG(fs
, MIPSInst_FS(ir
));
1658 rv
.w
= ieee754sp_tint(fs
);
1663 #if __mips >= 2 || defined(__mips64)
1668 unsigned int oldrm
= ieee754_csr
.rm
;
1671 SPFROMREG(fs
, MIPSInst_FS(ir
));
1672 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1673 rv
.w
= ieee754sp_tint(fs
);
1674 ieee754_csr
.rm
= oldrm
;
1678 #endif /* __mips >= 2 */
1680 #if defined(__mips64)
1684 SPFROMREG(fs
, MIPSInst_FS(ir
));
1685 rv
.l
= ieee754sp_tlong(fs
);
1694 unsigned int oldrm
= ieee754_csr
.rm
;
1697 SPFROMREG(fs
, MIPSInst_FS(ir
));
1698 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1699 rv
.l
= ieee754sp_tlong(fs
);
1700 ieee754_csr
.rm
= oldrm
;
1704 #endif /* defined(__mips64) */
1707 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1708 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1711 SPFROMREG(fs
, MIPSInst_FS(ir
));
1712 SPFROMREG(ft
, MIPSInst_FT(ir
));
1713 rv
.w
= ieee754sp_cmp(fs
, ft
,
1714 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1716 if ((cmpop
& 0x8) && ieee754_cxtest
1717 (IEEE754_INVALID_OPERATION
))
1718 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1733 ieee754dp(*b
) (ieee754dp
, ieee754dp
);
1734 ieee754dp(*u
) (ieee754dp
);
1737 switch (MIPSInst_FUNC(ir
)) {
1740 handler
.b
= ieee754dp_add
;
1743 handler
.b
= ieee754dp_sub
;
1746 handler
.b
= ieee754dp_mul
;
1749 handler
.b
= ieee754dp_div
;
1753 #if __mips >= 2 || defined(__mips64)
1755 handler
.u
= ieee754dp_sqrt
;
1758 #if __mips >= 4 && __mips != 32
1760 handler
.u
= fpemu_dp_rsqrt
;
1763 handler
.u
= fpemu_dp_recip
;
1768 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1769 if (((ctx
->fcr31
& cond
) != 0) !=
1770 ((MIPSInst_FT(ir
) & 1) != 0))
1772 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1775 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1777 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1780 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1782 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1786 handler
.u
= ieee754dp_abs
;
1790 handler
.u
= ieee754dp_neg
;
1795 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1798 /* binary op on handler */
1802 DPFROMREG(fs
, MIPSInst_FS(ir
));
1803 DPFROMREG(ft
, MIPSInst_FT(ir
));
1805 rv
.d
= (*handler
.b
) (fs
, ft
);
1811 DPFROMREG(fs
, MIPSInst_FS(ir
));
1812 rv
.d
= (*handler
.u
) (fs
);
1816 /* unary conv ops */
1820 DPFROMREG(fs
, MIPSInst_FS(ir
));
1821 rv
.s
= ieee754sp_fdp(fs
);
1826 return SIGILL
; /* not defined */
1831 DPFROMREG(fs
, MIPSInst_FS(ir
));
1832 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1837 #if __mips >= 2 || defined(__mips64)
1842 unsigned int oldrm
= ieee754_csr
.rm
;
1845 DPFROMREG(fs
, MIPSInst_FS(ir
));
1846 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1847 rv
.w
= ieee754dp_tint(fs
);
1848 ieee754_csr
.rm
= oldrm
;
1854 #if defined(__mips64)
1858 DPFROMREG(fs
, MIPSInst_FS(ir
));
1859 rv
.l
= ieee754dp_tlong(fs
);
1868 unsigned int oldrm
= ieee754_csr
.rm
;
1871 DPFROMREG(fs
, MIPSInst_FS(ir
));
1872 ieee754_csr
.rm
= ieee_rm
[modeindex(MIPSInst_FUNC(ir
))];
1873 rv
.l
= ieee754dp_tlong(fs
);
1874 ieee754_csr
.rm
= oldrm
;
1878 #endif /* __mips >= 3 */
1881 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1882 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1885 DPFROMREG(fs
, MIPSInst_FS(ir
));
1886 DPFROMREG(ft
, MIPSInst_FT(ir
));
1887 rv
.w
= ieee754dp_cmp(fs
, ft
,
1888 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1893 (IEEE754_INVALID_OPERATION
))
1894 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1910 switch (MIPSInst_FUNC(ir
)) {
1912 /* convert word to single precision real */
1913 SPFROMREG(fs
, MIPSInst_FS(ir
));
1914 rv
.s
= ieee754sp_fint(fs
.bits
);
1918 /* convert word to double precision real */
1919 SPFROMREG(fs
, MIPSInst_FS(ir
));
1920 rv
.d
= ieee754dp_fint(fs
.bits
);
1929 #if defined(__mips64)
1931 switch (MIPSInst_FUNC(ir
)) {
1933 /* convert long to single precision real */
1934 rv
.s
= ieee754sp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1938 /* convert long to double precision real */
1939 rv
.d
= ieee754dp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1954 * Update the fpu CSR register for this operation.
1955 * If an exception is required, generate a tidy SIGFPE exception,
1956 * without updating the result register.
1957 * Note: cause exception bits do not accumulate, they are rewritten
1958 * for each op; only the flag/sticky bits accumulate.
1960 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1961 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1962 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1967 * Now we can safely write the result back to the register file.
1972 cond
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
1974 cond
= FPU_CSR_COND
;
1979 ctx
->fcr31
&= ~cond
;
1983 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
1986 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
1989 SITOREG(rv
.w
, MIPSInst_FD(ir
));
1991 #if defined(__mips64)
1993 DITOREG(rv
.l
, MIPSInst_FD(ir
));
2003 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
2004 int has_fpu
, void *__user
*fault_addr
)
2006 unsigned long oldepc
, prevepc
;
2007 struct mm_decoded_insn dec_insn
;
2012 oldepc
= xcp
->cp0_epc
;
2014 prevepc
= xcp
->cp0_epc
;
2016 if (get_isa16_mode(prevepc
) && cpu_has_mmips
) {
2018 * Get next 2 microMIPS instructions and convert them
2019 * into 32-bit instructions.
2021 if ((get_user(instr
[0], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
))) ||
2022 (get_user(instr
[1], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 2))) ||
2023 (get_user(instr
[2], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 4))) ||
2024 (get_user(instr
[3], (u16 __user
*)msk_isa16_mode(xcp
->cp0_epc
+ 6)))) {
2025 MIPS_FPU_EMU_INC_STATS(errors
);
2030 /* Get first instruction. */
2031 if (mm_insn_16bit(*instr_ptr
)) {
2032 /* Duplicate the half-word. */
2033 dec_insn
.insn
= (*instr_ptr
<< 16) |
2035 /* 16-bit instruction. */
2036 dec_insn
.pc_inc
= 2;
2039 dec_insn
.insn
= (*instr_ptr
<< 16) |
2041 /* 32-bit instruction. */
2042 dec_insn
.pc_inc
= 4;
2045 /* Get second instruction. */
2046 if (mm_insn_16bit(*instr_ptr
)) {
2047 /* Duplicate the half-word. */
2048 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2050 /* 16-bit instruction. */
2051 dec_insn
.next_pc_inc
= 2;
2053 dec_insn
.next_insn
= (*instr_ptr
<< 16) |
2055 /* 32-bit instruction. */
2056 dec_insn
.next_pc_inc
= 4;
2058 dec_insn
.micro_mips_mode
= 1;
2060 if ((get_user(dec_insn
.insn
,
2061 (mips_instruction __user
*) xcp
->cp0_epc
)) ||
2062 (get_user(dec_insn
.next_insn
,
2063 (mips_instruction __user
*)(xcp
->cp0_epc
+4)))) {
2064 MIPS_FPU_EMU_INC_STATS(errors
);
2067 dec_insn
.pc_inc
= 4;
2068 dec_insn
.next_pc_inc
= 4;
2069 dec_insn
.micro_mips_mode
= 0;
2072 if ((dec_insn
.insn
== 0) ||
2073 ((dec_insn
.pc_inc
== 2) &&
2074 ((dec_insn
.insn
& 0xffff) == MM_NOP16
)))
2075 xcp
->cp0_epc
+= dec_insn
.pc_inc
; /* Skip NOPs */
2078 * The 'ieee754_csr' is an alias of
2079 * ctx->fcr31. No need to copy ctx->fcr31 to
2080 * ieee754_csr. But ieee754_csr.rm is ieee
2081 * library modes. (not mips rounding mode)
2083 /* convert to ieee library modes */
2084 ieee754_csr
.rm
= ieee_rm
[ieee754_csr
.rm
];
2085 sig
= cop1Emulate(xcp
, ctx
, dec_insn
, fault_addr
);
2086 /* revert to mips rounding mode */
2087 ieee754_csr
.rm
= mips_rm
[ieee754_csr
.rm
];
2096 } while (xcp
->cp0_epc
> prevepc
);
2098 /* SIGILL indicates a non-fpu instruction */
2099 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
2100 /* but if epc has advanced, then ignore it */
2106 #ifdef CONFIG_DEBUG_FS
2108 static int fpuemu_stat_get(void *data
, u64
*val
)
2111 unsigned long sum
= 0;
2112 for_each_online_cpu(cpu
) {
2113 struct mips_fpu_emulator_stats
*ps
;
2115 ps
= &per_cpu(fpuemustats
, cpu
);
2116 pv
= (void *)ps
+ (unsigned long)data
;
2117 sum
+= local_read(pv
);
2122 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat
, fpuemu_stat_get
, NULL
, "%llu\n");
2124 extern struct dentry
*mips_debugfs_dir
;
2125 static int __init
debugfs_fpuemu(void)
2127 struct dentry
*d
, *dir
;
2129 if (!mips_debugfs_dir
)
2131 dir
= debugfs_create_dir("fpuemustats", mips_debugfs_dir
);
2135 #define FPU_STAT_CREATE(M) \
2137 d = debugfs_create_file(#M , S_IRUGO, dir, \
2138 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2139 &fops_fpuemu_stat); \
2144 FPU_STAT_CREATE(emulated
);
2145 FPU_STAT_CREATE(loads
);
2146 FPU_STAT_CREATE(stores
);
2147 FPU_STAT_CREATE(cp1ops
);
2148 FPU_STAT_CREATE(cp1xops
);
2149 FPU_STAT_CREATE(errors
);
2153 __initcall(debugfs_fpuemu
);