arch/mips/pci/pci.c

   1 /*
   2  * This program is free software; you can redistribute  it and/or modify it
   3  * under  the terms of  the GNU General  Public License as published by the
   4  * Free Software Foundation;  either version 2 of the  License, or (at your
   5  * option) any later version.
   6  *
   7  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
   8  * Copyright (C) 2011 Wind River Systems,
   9  *   written by Ralf Baechle (ralf@linux-mips.org)
  10  */
  11 #include <linux/bug.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mm.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/export.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/of_address.h>
  20
  21 #include <asm/cpu-info.h>
  22
  23 /*
  24  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
  25  * assignments.
  26  */
  27
  28 /*
  29  * The PCI controller list.
  30  */
  31
  32 static struct pci_controller *hose_head, **hose_tail = &hose_head;
  33
  34 unsigned long PCIBIOS_MIN_IO;
  35 unsigned long PCIBIOS_MIN_MEM;
  36
  37 static int pci_initialized;
  38
  39 /*
  40  * We need to avoid collisions with `mirrored' VGA ports
  41  * and other strange ISA hardware, so we always want the
  42  * addresses to be allocated in the 0x000-0x0ff region
  43  * modulo 0x400.
  44  *
  45  * Why? Because some silly external IO cards only decode
  46  * the low 10 bits of the IO address. The 0x00-0xff region
  47  * is reserved for motherboard devices that decode all 16
  48  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  49  * but we want to try to avoid allocating at 0x2900-0x2bff
  50  * which might have be mirrored at 0x0100-0x03ff..
  51  */
  52 resource_size_t
  53 pcibios_align_resource(void *data, const struct resource *res,
  54                        resource_size_t size, resource_size_t align)
  55 {
  56         struct pci_dev *dev = data;
  57         struct pci_controller *hose = dev->sysdata;
  58         resource_size_t start = res->start;
  59
  60         if (res->flags & IORESOURCE_IO) {
  61                 /* Make sure we start at our min on all hoses */
  62                 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
  63                         start = PCIBIOS_MIN_IO + hose->io_resource->start;
  64
  65                 /*
  66                  * Put everything into 0x00-0xff region modulo 0x400
  67                  */
  68                 if (start & 0x300)
  69                         start = (start + 0x3ff) & ~0x3ff;
  70         } else if (res->flags & IORESOURCE_MEM) {
  71                 /* Make sure we start at our min on all hoses */
  72                 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
  73                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
  74         }
  75
  76         return start;
  77 }
  78
  79 static void pcibios_scanbus(struct pci_controller *hose)
  80 {
  81         static int next_busno;
  82         static int need_domain_info;
  83         LIST_HEAD(resources);
  84         struct pci_bus *bus;
  85
  86         if (!hose->iommu)
  87                 PCI_DMA_BUS_IS_PHYS = 1;
  88
  89         if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
  90                 next_busno = (*hose->get_busno)();
  91
  92         pci_add_resource_offset(&resources,
  93                                 hose->mem_resource, hose->mem_offset);
  94         pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
  95         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
  96                                 &resources);
  97         if (!bus)
  98                 pci_free_resource_list(&resources);
  99
 100         hose->bus = bus;
 101
 102         need_domain_info = need_domain_info || hose->index;
 103         hose->need_domain_info = need_domain_info;
 104         if (bus) {
 105                 next_busno = bus->busn_res.end + 1;
 106                 /* Don't allow 8-bit bus number overflow inside the hose -
 107                    reserve some space for bridges. */
 108                 if (next_busno > 224) {
 109                         next_busno = 0;
 110                         need_domain_info = 1;
 111                 }
 112
 113                 if (!pci_has_flag(PCI_PROBE_ONLY)) {
 114                         pci_bus_size_bridges(bus);
 115                         pci_bus_assign_resources(bus);
 116                         pci_enable_bridges(bus);
 117                 }
 118         }
 119 }
 120
 121 #ifdef CONFIG_OF
 122 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
 123 {
 124         const __be32 *ranges;
 125         int rlen;
 126         int pna = of_n_addr_cells(node);
 127         int np = pna + 5;
 128
 129         pr_info("PCI host bridge %s ranges:\n", node->full_name);
 130         ranges = of_get_property(node, "ranges", &rlen);
 131         if (ranges == NULL)
 132                 return;
 133         hose->of_node = node;
 134
 135         while ((rlen -= np * 4) >= 0) {
 136                 u32 pci_space;
 137                 struct resource *res = NULL;
 138                 u64 addr, size;
 139
 140                 pci_space = be32_to_cpup(&ranges[0]);
 141                 addr = of_translate_address(node, ranges + 3);
 142                 size = of_read_number(ranges + pna + 3, 2);
 143                 ranges += np;
 144                 switch ((pci_space >> 24) & 0x3) {
 145                 case 1:         /* PCI IO space */
 146                         pr_info("  IO 0x%016llx..0x%016llx\n",
 147                                         addr, addr + size - 1);
 148                         hose->io_map_base =
 149                                 (unsigned long)ioremap(addr, size);
 150                         res = hose->io_resource;
 151                         res->flags = IORESOURCE_IO;
 152                         break;
 153                 case 2:         /* PCI Memory space */
 154                 case 3:         /* PCI 64 bits Memory space */
 155                         pr_info(" MEM 0x%016llx..0x%016llx\n",
 156                                         addr, addr + size - 1);
 157                         res = hose->mem_resource;
 158                         res->flags = IORESOURCE_MEM;
 159                         break;
 160                 }
 161                 if (res != NULL) {
 162                         res->start = addr;
 163                         res->name = node->full_name;
 164                         res->end = res->start + size - 1;
 165                         res->parent = NULL;
 166                         res->sibling = NULL;
 167                         res->child = NULL;
 168                 }
 169         }
 170 }
 171
 172 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
 173 {
 174         struct pci_controller *hose = bus->sysdata;
 175
 176         return of_node_get(hose->of_node);
 177 }
 178 #endif
 179
 180 static DEFINE_MUTEX(pci_scan_mutex);
 181
 182 void register_pci_controller(struct pci_controller *hose)
 183 {
 184         struct resource *parent;
 185
 186         parent = hose->mem_resource->parent;
 187         if (!parent)
 188                 parent = &iomem_resource;
 189
 190         if (request_resource(parent, hose->mem_resource) < 0)
 191                 goto out;
 192
 193         parent = hose->io_resource->parent;
 194         if (!parent)
 195                 parent = &ioport_resource;
 196
 197         if (request_resource(parent, hose->io_resource) < 0) {
 198                 release_resource(hose->mem_resource);
 199                 goto out;
 200         }
 201
 202         *hose_tail = hose;
 203         hose_tail = &hose->next;
 204
 205         /*
 206          * Do not panic here but later - this might happen before console init.
 207          */
 208         if (!hose->io_map_base) {
 209                 printk(KERN_WARNING
 210                        "registering PCI controller with io_map_base unset\n");
 211         }
 212
 213         /*
 214          * Scan the bus if it is register after the PCI subsystem
 215          * initialization.
 216          */
 217         if (pci_initialized) {
 218                 mutex_lock(&pci_scan_mutex);
 219                 pcibios_scanbus(hose);
 220                 mutex_unlock(&pci_scan_mutex);
 221         }
 222
 223         return;
 224
 225 out:
 226         printk(KERN_WARNING
 227                "Skipping PCI bus scan due to resource conflict\n");
 228 }
 229
 230 static void __init pcibios_set_cache_line_size(void)
 231 {
 232         struct cpuinfo_mips *c = &current_cpu_data;
 233         unsigned int lsize;
 234
 235         /*
 236          * Set PCI cacheline size to that of the highest level in the
 237          * cache hierarchy.
 238          */
 239         lsize = c->dcache.linesz;
 240         lsize = c->scache.linesz ? : lsize;
 241         lsize = c->tcache.linesz ? : lsize;
 242
 243         BUG_ON(!lsize);
 244
 245         pci_dfl_cache_line_size = lsize >> 2;
 246
 247         pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
 248 }
 249
 250 static int __init pcibios_init(void)
 251 {
 252         struct pci_controller *hose;
 253
 254         pcibios_set_cache_line_size();
 255
 256         /* Scan all of the recorded PCI controllers.  */
 257         for (hose = hose_head; hose; hose = hose->next)
 258                 pcibios_scanbus(hose);
 259
 260         pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
 261
 262         pci_initialized = 1;
 263
 264         return 0;
 265 }
 266
 267 subsys_initcall(pcibios_init);
 268
 269 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 270 {
 271         u16 cmd, old_cmd;
 272         int idx;
 273         struct resource *r;
 274
 275         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 276         old_cmd = cmd;
 277         for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
 278                 /* Only set up the requested stuff */
 279                 if (!(mask & (1<<idx)))
 280                         continue;
 281
 282                 r = &dev->resource[idx];
 283                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 284                         continue;
 285                 if ((idx == PCI_ROM_RESOURCE) &&
 286                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 287                         continue;
 288                 if (!r->start && r->end) {
 289                         printk(KERN_ERR "PCI: Device %s not available "
 290                                "because of resource collisions\n",
 291                                pci_name(dev));
 292                         return -EINVAL;
 293                 }
 294                 if (r->flags & IORESOURCE_IO)
 295                         cmd |= PCI_COMMAND_IO;
 296                 if (r->flags & IORESOURCE_MEM)
 297                         cmd |= PCI_COMMAND_MEMORY;
 298         }
 299         if (cmd != old_cmd) {
 300                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
 301                        pci_name(dev), old_cmd, cmd);
 302                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 303         }
 304         return 0;
 305 }
 306
 307 unsigned int pcibios_assign_all_busses(void)
 308 {
 309         return 1;
 310 }
 311
 312 int pcibios_enable_device(struct pci_dev *dev, int mask)
 313 {
 314         int err;
 315
 316         if ((err = pcibios_enable_resources(dev, mask)) < 0)
 317                 return err;
 318
 319         return pcibios_plat_dev_init(dev);
 320 }
 321
 322 void pcibios_fixup_bus(struct pci_bus *bus)
 323 {
 324         struct pci_dev *dev = bus->self;
 325
 326         if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
 327             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 328                 pci_read_bridge_bases(bus);
 329         }
 330 }
 331
 332 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 333 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 334
 335 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 336                         enum pci_mmap_state mmap_state, int write_combine)
 337 {
 338         unsigned long prot;
 339
 340         /*
 341          * I/O space can be accessed via normal processor loads and stores on
 342          * this platform but for now we elect not to do this and portable
 343          * drivers should not do this anyway.
 344          */
 345         if (mmap_state == pci_mmap_io)
 346                 return -EINVAL;
 347
 348         /*
 349          * Ignore write-combine; for now only return uncached mappings.
 350          */
 351         prot = pgprot_val(vma->vm_page_prot);
 352         prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
 353         vma->vm_page_prot = __pgprot(prot);
 354
 355         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 356                 vma->vm_end - vma->vm_start, vma->vm_page_prot);
 357 }
 358
 359 char * (*pcibios_plat_setup)(char *str) __initdata;
 360
 361 char *__init pcibios_setup(char *str)
 362 {
 363         if (pcibios_plat_setup)
 364                 return pcibios_plat_setup(str);
 365         return str;
 366 }