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doc: Update rcu_assign_pointer() definition in whatisRCU.txt
[linux/fpc-iii.git] / drivers / usb / gadget / udc / mv_u3d_core.c
blobd365449a295a8ab823f9358146a0a910bcabba2d
1 /*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmapool.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/ioport.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/errno.h>
18 #include <linux/timer.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/interrupt.h>
22 #include <linux/moduleparam.h>
23 #include <linux/device.h>
24 #include <linux/usb/ch9.h>
25 #include <linux/usb/gadget.h>
26 #include <linux/pm.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/platform_device.h>
30 #include <linux/platform_data/mv_usb.h>
31 #include <linux/clk.h>
32
33 #include "mv_u3d.h"
34
35 #define DRIVER_DESC "Marvell PXA USB3.0 Device Controller driver"
36
37 static const char driver_name[] = "mv_u3d";
38 static const char driver_desc[] = DRIVER_DESC;
39
40 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status);
41 static void mv_u3d_stop_activity(struct mv_u3d *u3d,
42 struct usb_gadget_driver *driver);
43
44 /* for endpoint 0 operations */
45 static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = {
46 .bLength = USB_DT_ENDPOINT_SIZE,
47 .bDescriptorType = USB_DT_ENDPOINT,
48 .bEndpointAddress = 0,
49 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
50 .wMaxPacketSize = MV_U3D_EP0_MAX_PKT_SIZE,
51 };
52
53 static void mv_u3d_ep0_reset(struct mv_u3d *u3d)
54 {
55 struct mv_u3d_ep *ep;
56 u32 epxcr;
57 int i;
58
59 for (i = 0; i < 2; i++) {
60 ep = &u3d->eps[i];
61 ep->u3d = u3d;
62
63 /* ep0 ep context, ep0 in and out share the same ep context */
64 ep->ep_context = &u3d->ep_context[1];
65 }
66
67 /* reset ep state machine */
68 /* reset ep0 out */
69 epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
70 epxcr |= MV_U3D_EPXCR_EP_INIT;
71 iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
72 udelay(5);
73 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
74 iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
75
76 epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
77 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
78 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
79 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
80 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
81 iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1);
82
83 /* reset ep0 in */
84 epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
85 epxcr |= MV_U3D_EPXCR_EP_INIT;
86 iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
87 udelay(5);
88 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
89 iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
90
91 epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
92 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
93 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
94 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
95 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
96 iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1);
97 }
98
99 static void mv_u3d_ep0_stall(struct mv_u3d *u3d)
100 {
101 u32 tmp;
102 dev_dbg(u3d->dev, "%s\n", __func__);
103
104 /* set TX and RX to stall */
105 tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
106 tmp |= MV_U3D_EPXCR_EP_HALT;
107 iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
108
109 tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
110 tmp |= MV_U3D_EPXCR_EP_HALT;
111 iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
112
113 /* update ep0 state */
114 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
115 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
116 }
117
118 static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index,
119 struct mv_u3d_req *curr_req)
120 {
121 struct mv_u3d_trb *curr_trb;
122 int actual, remaining_length = 0;
123 int direction, ep_num;
124 int retval = 0;
125 u32 tmp, status, length;
126
127 direction = index % 2;
128 ep_num = index / 2;
129
130 actual = curr_req->req.length;
131
132 while (!list_empty(&curr_req->trb_list)) {
133 curr_trb = list_entry(curr_req->trb_list.next,
134 struct mv_u3d_trb, trb_list);
135 if (!curr_trb->trb_hw->ctrl.own) {
136 dev_err(u3d->dev, "%s, TRB own error!\n",
137 u3d->eps[index].name);
138 return 1;
139 }
140
141 curr_trb->trb_hw->ctrl.own = 0;
142 if (direction == MV_U3D_EP_DIR_OUT)
143 tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo);
144 else
145 tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo);
146
147 status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT;
148 length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK;
149
150 if (status == MV_U3D_COMPLETE_SUCCESS ||
151 (status == MV_U3D_COMPLETE_SHORT_PACKET &&
152 direction == MV_U3D_EP_DIR_OUT)) {
153 remaining_length += length;
154 actual -= remaining_length;
155 } else {
156 dev_err(u3d->dev,
157 "complete_tr error: ep=%d %s: error = 0x%x\n",
158 index >> 1, direction ? "SEND" : "RECV",
159 status);
160 retval = -EPROTO;
161 }
162
163 list_del_init(&curr_trb->trb_list);
164 }
165 if (retval)
166 return retval;
167
168 curr_req->req.actual = actual;
169 return 0;
170 }
171
172 /*
173 * mv_u3d_done() - retire a request; caller blocked irqs
174 * @status : request status to be set, only works when
175 * request is still in progress.
176 */
177 static
178 void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status)
179 __releases(&ep->udc->lock)
180 __acquires(&ep->udc->lock)
181 {
182 struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d;
183
184 dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n");
185 /* Removed the req from ep queue */
186 list_del_init(&req->queue);
187
188 /* req.status should be set as -EINPROGRESS in ep_queue() */
189 if (req->req.status == -EINPROGRESS)
190 req->req.status = status;
191 else
192 status = req->req.status;
193
194 /* Free trb for the request */
195 if (!req->chain)
196 dma_pool_free(u3d->trb_pool,
197 req->trb_head->trb_hw, req->trb_head->trb_dma);
198 else {
199 dma_unmap_single(ep->u3d->gadget.dev.parent,
200 (dma_addr_t)req->trb_head->trb_dma,
201 req->trb_count * sizeof(struct mv_u3d_trb_hw),
202 DMA_BIDIRECTIONAL);
203 kfree(req->trb_head->trb_hw);
204 }
205 kfree(req->trb_head);
206
207 usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep));
208
209 if (status && (status != -ESHUTDOWN)) {
210 dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u",
211 ep->ep.name, &req->req, status,
212 req->req.actual, req->req.length);
213 }
214
215 spin_unlock(&ep->u3d->lock);
216
217 usb_gadget_giveback_request(&ep->ep, &req->req);
218
219 spin_lock(&ep->u3d->lock);
220 }
221
222 static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req)
223 {
224 u32 tmp, direction;
225 struct mv_u3d *u3d;
226 struct mv_u3d_ep_context *ep_context;
227 int retval = 0;
228
229 u3d = ep->u3d;
230 direction = mv_u3d_ep_dir(ep);
231
232 /* ep0 in and out share the same ep context slot 1*/
233 if (ep->ep_num == 0)
234 ep_context = &(u3d->ep_context[1]);
235 else
236 ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]);
237
238 /* check if the pipe is empty or not */
239 if (!list_empty(&ep->queue)) {
240 dev_err(u3d->dev, "add trb to non-empty queue!\n");
241 retval = -ENOMEM;
242 WARN_ON(1);
243 } else {
244 ep_context->rsvd0 = cpu_to_le32(1);
245 ep_context->rsvd1 = 0;
246
247 /* Configure the trb address and set the DCS bit.
248 * Both DCS bit and own bit in trb should be set.
249 */
250 ep_context->trb_addr_lo =
251 cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE);
252 ep_context->trb_addr_hi = 0;
253
254 /* Ensure that updates to the EP Context will
255 * occure before Ring Bell.
256 */
257 wmb();
258
259 /* ring bell the ep */
260 if (ep->ep_num == 0)
261 tmp = 0x1;
262 else
263 tmp = ep->ep_num * 2
264 + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1);
265
266 iowrite32(tmp, &u3d->op_regs->doorbell);
267 }
268 return retval;
269 }
270
271 static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req,
272 unsigned *length, dma_addr_t *dma)
273 {
274 u32 temp;
275 unsigned int direction;
276 struct mv_u3d_trb *trb;
277 struct mv_u3d_trb_hw *trb_hw;
278 struct mv_u3d *u3d;
279
280 /* how big will this transfer be? */
281 *length = req->req.length - req->req.actual;
282 BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
283
284 u3d = req->ep->u3d;
285
286 trb = kzalloc(sizeof(*trb), GFP_ATOMIC);
287 if (!trb)
288 return NULL;
289
290 /*
291 * Be careful that no _GFP_HIGHMEM is set,
292 * or we can not use dma_to_virt
293 * cannot use GFP_KERNEL in spin lock
294 */
295 trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma);
296 if (!trb_hw) {
297 kfree(trb);
298 dev_err(u3d->dev,
299 "%s, dma_pool_alloc fail\n", __func__);
300 return NULL;
301 }
302 trb->trb_dma = *dma;
303 trb->trb_hw = trb_hw;
304
305 /* initialize buffer page pointers */
306 temp = (u32)(req->req.dma + req->req.actual);
307
308 trb_hw->buf_addr_lo = cpu_to_le32(temp);
309 trb_hw->buf_addr_hi = 0;
310 trb_hw->trb_len = cpu_to_le32(*length);
311 trb_hw->ctrl.own = 1;
312
313 if (req->ep->ep_num == 0)
314 trb_hw->ctrl.type = TYPE_DATA;
315 else
316 trb_hw->ctrl.type = TYPE_NORMAL;
317
318 req->req.actual += *length;
319
320 direction = mv_u3d_ep_dir(req->ep);
321 if (direction == MV_U3D_EP_DIR_IN)
322 trb_hw->ctrl.dir = 1;
323 else
324 trb_hw->ctrl.dir = 0;
325
326 /* Enable interrupt for the last trb of a request */
327 if (!req->req.no_interrupt)
328 trb_hw->ctrl.ioc = 1;
329
330 trb_hw->ctrl.chain = 0;
331
332 wmb();
333 return trb;
334 }
335
336 static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length,
337 struct mv_u3d_trb *trb, int *is_last)
338 {
339 u32 temp;
340 unsigned int direction;
341 struct mv_u3d *u3d;
342
343 /* how big will this transfer be? */
344 *length = min(req->req.length - req->req.actual,
345 (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
346
347 u3d = req->ep->u3d;
348
349 trb->trb_dma = 0;
350
351 /* initialize buffer page pointers */
352 temp = (u32)(req->req.dma + req->req.actual);
353
354 trb->trb_hw->buf_addr_lo = cpu_to_le32(temp);
355 trb->trb_hw->buf_addr_hi = 0;
356 trb->trb_hw->trb_len = cpu_to_le32(*length);
357 trb->trb_hw->ctrl.own = 1;
358
359 if (req->ep->ep_num == 0)
360 trb->trb_hw->ctrl.type = TYPE_DATA;
361 else
362 trb->trb_hw->ctrl.type = TYPE_NORMAL;
363
364 req->req.actual += *length;
365
366 direction = mv_u3d_ep_dir(req->ep);
367 if (direction == MV_U3D_EP_DIR_IN)
368 trb->trb_hw->ctrl.dir = 1;
369 else
370 trb->trb_hw->ctrl.dir = 0;
371
372 /* zlp is needed if req->req.zero is set */
373 if (req->req.zero) {
374 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
375 *is_last = 1;
376 else
377 *is_last = 0;
378 } else if (req->req.length == req->req.actual)
379 *is_last = 1;
380 else
381 *is_last = 0;
382
383 /* Enable interrupt for the last trb of a request */
384 if (*is_last && !req->req.no_interrupt)
385 trb->trb_hw->ctrl.ioc = 1;
386
387 if (*is_last)
388 trb->trb_hw->ctrl.chain = 0;
389 else {
390 trb->trb_hw->ctrl.chain = 1;
391 dev_dbg(u3d->dev, "chain trb\n");
392 }
393
394 wmb();
395
396 return 0;
397 }
398
399 /* generate TRB linked list for a request
400 * usb controller only supports continous trb chain,
401 * that trb structure physical address should be continous.
402 */
403 static int mv_u3d_req_to_trb(struct mv_u3d_req *req)
404 {
405 unsigned count;
406 int is_last;
407 struct mv_u3d_trb *trb;
408 struct mv_u3d_trb_hw *trb_hw;
409 struct mv_u3d *u3d;
410 dma_addr_t dma;
411 unsigned length;
412 unsigned trb_num;
413
414 u3d = req->ep->u3d;
415
416 INIT_LIST_HEAD(&req->trb_list);
417
418 length = req->req.length - req->req.actual;
419 /* normally the request transfer length is less than 16KB.
420 * we use buil_trb_one() to optimize it.
421 */
422 if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) {
423 trb = mv_u3d_build_trb_one(req, &count, &dma);
424 list_add_tail(&trb->trb_list, &req->trb_list);
425 req->trb_head = trb;
426 req->trb_count = 1;
427 req->chain = 0;
428 } else {
429 trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER;
430 if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER)
431 trb_num++;
432
433 trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC);
434 if (!trb)
435 return -ENOMEM;
436
437 trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC);
438 if (!trb_hw) {
439 kfree(trb);
440 return -ENOMEM;
441 }
442
443 do {
444 trb->trb_hw = trb_hw;
445 if (mv_u3d_build_trb_chain(req, &count,
446 trb, &is_last)) {
447 dev_err(u3d->dev,
448 "%s, mv_u3d_build_trb_chain fail\n",
449 __func__);
450 return -EIO;
451 }
452
453 list_add_tail(&trb->trb_list, &req->trb_list);
454 req->trb_count++;
455 trb++;
456 trb_hw++;
457 } while (!is_last);
458
459 req->trb_head = list_entry(req->trb_list.next,
460 struct mv_u3d_trb, trb_list);
461 req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent,
462 req->trb_head->trb_hw,
463 trb_num * sizeof(*trb_hw),
464 DMA_BIDIRECTIONAL);
465 if (dma_mapping_error(u3d->gadget.dev.parent,
466 req->trb_head->trb_dma)) {
467 kfree(req->trb_head->trb_hw);
468 kfree(req->trb_head);
469 return -EFAULT;
470 }
471
472 req->chain = 1;
473 }
474
475 return 0;
476 }
477
478 static int
479 mv_u3d_start_queue(struct mv_u3d_ep *ep)
480 {
481 struct mv_u3d *u3d = ep->u3d;
482 struct mv_u3d_req *req;
483 int ret;
484
485 if (!list_empty(&ep->req_list) && !ep->processing)
486 req = list_entry(ep->req_list.next, struct mv_u3d_req, list);
487 else
488 return 0;
489
490 ep->processing = 1;
491
492 /* set up dma mapping */
493 ret = usb_gadget_map_request(&u3d->gadget, &req->req,
494 mv_u3d_ep_dir(ep));
495 if (ret)
496 goto break_processing;
497
498 req->req.status = -EINPROGRESS;
499 req->req.actual = 0;
500 req->trb_count = 0;
501
502 /* build trbs */
503 ret = mv_u3d_req_to_trb(req);
504 if (ret) {
505 dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__);
506 goto break_processing;
507 }
508
509 /* and push them to device queue */
510 ret = mv_u3d_queue_trb(ep, req);
511 if (ret)
512 goto break_processing;
513
514 /* irq handler advances the queue */
515 list_add_tail(&req->queue, &ep->queue);
516
517 return 0;
518
519 break_processing:
520 ep->processing = 0;
521 return ret;
522 }
523
524 static int mv_u3d_ep_enable(struct usb_ep *_ep,
525 const struct usb_endpoint_descriptor *desc)
526 {
527 struct mv_u3d *u3d;
528 struct mv_u3d_ep *ep;
529 u16 max = 0;
530 unsigned maxburst = 0;
531 u32 epxcr, direction;
532
533 if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT)
534 return -EINVAL;
535
536 ep = container_of(_ep, struct mv_u3d_ep, ep);
537 u3d = ep->u3d;
538
539 if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN)
540 return -ESHUTDOWN;
541
542 direction = mv_u3d_ep_dir(ep);
543 max = le16_to_cpu(desc->wMaxPacketSize);
544
545 if (!_ep->maxburst)
546 _ep->maxburst = 1;
547 maxburst = _ep->maxburst;
548
549 /* Set the max burst size */
550 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
551 case USB_ENDPOINT_XFER_BULK:
552 if (maxburst > 16) {
553 dev_dbg(u3d->dev,
554 "max burst should not be greater "
555 "than 16 on bulk ep\n");
556 maxburst = 1;
557 _ep->maxburst = maxburst;
558 }
559 dev_dbg(u3d->dev,
560 "maxburst: %d on bulk %s\n", maxburst, ep->name);
561 break;
562 case USB_ENDPOINT_XFER_CONTROL:
563 /* control transfer only supports maxburst as one */
564 maxburst = 1;
565 _ep->maxburst = maxburst;
566 break;
567 case USB_ENDPOINT_XFER_INT:
568 if (maxburst != 1) {
569 dev_dbg(u3d->dev,
570 "max burst should be 1 on int ep "
571 "if transfer size is not 1024\n");
572 maxburst = 1;
573 _ep->maxburst = maxburst;
574 }
575 break;
576 case USB_ENDPOINT_XFER_ISOC:
577 if (maxburst != 1) {
578 dev_dbg(u3d->dev,
579 "max burst should be 1 on isoc ep "
580 "if transfer size is not 1024\n");
581 maxburst = 1;
582 _ep->maxburst = maxburst;
583 }
584 break;
585 default:
586 goto en_done;
587 }
588
589 ep->ep.maxpacket = max;
590 ep->ep.desc = desc;
591 ep->enabled = 1;
592
593 /* Enable the endpoint for Rx or Tx and set the endpoint type */
594 if (direction == MV_U3D_EP_DIR_OUT) {
595 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
596 epxcr |= MV_U3D_EPXCR_EP_INIT;
597 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
598 udelay(5);
599 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
600 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
601
602 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
603 | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
604 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
605 | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
606 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
607 } else {
608 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
609 epxcr |= MV_U3D_EPXCR_EP_INIT;
610 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
611 udelay(5);
612 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
613 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
614
615 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
616 | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
617 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
618 | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
619 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
620 }
621
622 return 0;
623 en_done:
624 return -EINVAL;
625 }
626
627 static int mv_u3d_ep_disable(struct usb_ep *_ep)
628 {
629 struct mv_u3d *u3d;
630 struct mv_u3d_ep *ep;
631 u32 epxcr, direction;
632 unsigned long flags;
633
634 if (!_ep)
635 return -EINVAL;
636
637 ep = container_of(_ep, struct mv_u3d_ep, ep);
638 if (!ep->ep.desc)
639 return -EINVAL;
640
641 u3d = ep->u3d;
642
643 direction = mv_u3d_ep_dir(ep);
644
645 /* nuke all pending requests (does flush) */
646 spin_lock_irqsave(&u3d->lock, flags);
647 mv_u3d_nuke(ep, -ESHUTDOWN);
648 spin_unlock_irqrestore(&u3d->lock, flags);
649
650 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
651 if (direction == MV_U3D_EP_DIR_OUT) {
652 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
653 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
654 | USB_ENDPOINT_XFERTYPE_MASK);
655 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
656 } else {
657 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
658 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
659 | USB_ENDPOINT_XFERTYPE_MASK);
660 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
661 }
662
663 ep->enabled = 0;
664
665 ep->ep.desc = NULL;
666 return 0;
667 }
668
669 static struct usb_request *
670 mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
671 {
672 struct mv_u3d_req *req = NULL;
673
674 req = kzalloc(sizeof *req, gfp_flags);
675 if (!req)
676 return NULL;
677
678 INIT_LIST_HEAD(&req->queue);
679
680 return &req->req;
681 }
682
683 static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req)
684 {
685 struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req);
686
687 kfree(req);
688 }
689
690 static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep)
691 {
692 struct mv_u3d *u3d;
693 u32 direction;
694 struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep);
695 unsigned int loops;
696 u32 tmp;
697
698 /* if endpoint is not enabled, cannot flush endpoint */
699 if (!ep->enabled)
700 return;
701
702 u3d = ep->u3d;
703 direction = mv_u3d_ep_dir(ep);
704
705 /* ep0 need clear bit after flushing fifo. */
706 if (!ep->ep_num) {
707 if (direction == MV_U3D_EP_DIR_OUT) {
708 tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
709 tmp |= MV_U3D_EPXCR_EP_FLUSH;
710 iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
711 udelay(10);
712 tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
713 iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
714 } else {
715 tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
716 tmp |= MV_U3D_EPXCR_EP_FLUSH;
717 iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
718 udelay(10);
719 tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
720 iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
721 }
722 return;
723 }
724
725 if (direction == MV_U3D_EP_DIR_OUT) {
726 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
727 tmp |= MV_U3D_EPXCR_EP_FLUSH;
728 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
729
730 /* Wait until flushing completed */
731 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
732 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) &
733 MV_U3D_EPXCR_EP_FLUSH) {
734 /*
735 * EP_FLUSH bit should be cleared to indicate this
736 * operation is complete
737 */
738 if (loops == 0) {
739 dev_dbg(u3d->dev,
740 "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
741 direction ? "in" : "out");
742 return;
743 }
744 loops--;
745 udelay(LOOPS_USEC);
746 }
747 } else { /* EP_DIR_IN */
748 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
749 tmp |= MV_U3D_EPXCR_EP_FLUSH;
750 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
751
752 /* Wait until flushing completed */
753 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
754 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) &
755 MV_U3D_EPXCR_EP_FLUSH) {
756 /*
757 * EP_FLUSH bit should be cleared to indicate this
758 * operation is complete
759 */
760 if (loops == 0) {
761 dev_dbg(u3d->dev,
762 "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
763 direction ? "in" : "out");
764 return;
765 }
766 loops--;
767 udelay(LOOPS_USEC);
768 }
769 }
770 }
771
772 /* queues (submits) an I/O request to an endpoint */
773 static int
774 mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
775 {
776 struct mv_u3d_ep *ep;
777 struct mv_u3d_req *req;
778 struct mv_u3d *u3d;
779 unsigned long flags;
780 int is_first_req = 0;
781
782 if (unlikely(!_ep || !_req))
783 return -EINVAL;
784
785 ep = container_of(_ep, struct mv_u3d_ep, ep);
786 u3d = ep->u3d;
787
788 req = container_of(_req, struct mv_u3d_req, req);
789
790 if (!ep->ep_num
791 && u3d->ep0_state == MV_U3D_STATUS_STAGE
792 && !_req->length) {
793 dev_dbg(u3d->dev, "ep0 status stage\n");
794 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
795 return 0;
796 }
797
798 dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n",
799 __func__, _ep->name, req);
800
801 /* catch various bogus parameters */
802 if (!req->req.complete || !req->req.buf
803 || !list_empty(&req->queue)) {
804 dev_err(u3d->dev,
805 "%s, bad params, _req: 0x%p,"
806 "req->req.complete: 0x%p, req->req.buf: 0x%p,"
807 "list_empty: 0x%x\n",
808 __func__, _req,
809 req->req.complete, req->req.buf,
810 list_empty(&req->queue));
811 return -EINVAL;
812 }
813 if (unlikely(!ep->ep.desc)) {
814 dev_err(u3d->dev, "%s, bad ep\n", __func__);
815 return -EINVAL;
816 }
817 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
818 if (req->req.length > ep->ep.maxpacket)
819 return -EMSGSIZE;
820 }
821
822 if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) {
823 dev_err(u3d->dev,
824 "bad params of driver/speed\n");
825 return -ESHUTDOWN;
826 }
827
828 req->ep = ep;
829
830 /* Software list handles usb request. */
831 spin_lock_irqsave(&ep->req_lock, flags);
832 is_first_req = list_empty(&ep->req_list);
833 list_add_tail(&req->list, &ep->req_list);
834 spin_unlock_irqrestore(&ep->req_lock, flags);
835 if (!is_first_req) {
836 dev_dbg(u3d->dev, "list is not empty\n");
837 return 0;
838 }
839
840 dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n");
841 spin_lock_irqsave(&u3d->lock, flags);
842 mv_u3d_start_queue(ep);
843 spin_unlock_irqrestore(&u3d->lock, flags);
844 return 0;
845 }
846
847 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
848 static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
849 {
850 struct mv_u3d_ep *ep;
851 struct mv_u3d_req *req;
852 struct mv_u3d *u3d;
853 struct mv_u3d_ep_context *ep_context;
854 struct mv_u3d_req *next_req;
855
856 unsigned long flags;
857 int ret = 0;
858
859 if (!_ep || !_req)
860 return -EINVAL;
861
862 ep = container_of(_ep, struct mv_u3d_ep, ep);
863 u3d = ep->u3d;
864
865 spin_lock_irqsave(&ep->u3d->lock, flags);
866
867 /* make sure it's actually queued on this endpoint */
868 list_for_each_entry(req, &ep->queue, queue) {
869 if (&req->req == _req)
870 break;
871 }
872 if (&req->req != _req) {
873 ret = -EINVAL;
874 goto out;
875 }
876
877 /* The request is in progress, or completed but not dequeued */
878 if (ep->queue.next == &req->queue) {
879 _req->status = -ECONNRESET;
880 mv_u3d_ep_fifo_flush(_ep);
881
882 /* The request isn't the last request in this ep queue */
883 if (req->queue.next != &ep->queue) {
884 dev_dbg(u3d->dev,
885 "it is the last request in this ep queue\n");
886 ep_context = ep->ep_context;
887 next_req = list_entry(req->queue.next,
888 struct mv_u3d_req, queue);
889
890 /* Point first TRB of next request to the EP context. */
891 iowrite32((unsigned long) next_req->trb_head,
892 &ep_context->trb_addr_lo);
893 } else {
894 struct mv_u3d_ep_context *ep_context;
895 ep_context = ep->ep_context;
896 ep_context->trb_addr_lo = 0;
897 ep_context->trb_addr_hi = 0;
898 }
899
900 } else
901 WARN_ON(1);
902
903 mv_u3d_done(ep, req, -ECONNRESET);
904
905 /* remove the req from the ep req list */
906 if (!list_empty(&ep->req_list)) {
907 struct mv_u3d_req *curr_req;
908 curr_req = list_entry(ep->req_list.next,
909 struct mv_u3d_req, list);
910 if (curr_req == req) {
911 list_del_init(&req->list);
912 ep->processing = 0;
913 }
914 }
915
916 out:
917 spin_unlock_irqrestore(&ep->u3d->lock, flags);
918 return ret;
919 }
920
921 static void
922 mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall)
923 {
924 u32 tmp;
925 struct mv_u3d_ep *ep = u3d->eps;
926
927 dev_dbg(u3d->dev, "%s\n", __func__);
928 if (direction == MV_U3D_EP_DIR_OUT) {
929 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
930 if (stall)
931 tmp |= MV_U3D_EPXCR_EP_HALT;
932 else
933 tmp &= ~MV_U3D_EPXCR_EP_HALT;
934 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
935 } else {
936 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
937 if (stall)
938 tmp |= MV_U3D_EPXCR_EP_HALT;
939 else
940 tmp &= ~MV_U3D_EPXCR_EP_HALT;
941 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
942 }
943 }
944
945 static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
946 {
947 struct mv_u3d_ep *ep;
948 unsigned long flags = 0;
949 int status = 0;
950 struct mv_u3d *u3d;
951
952 ep = container_of(_ep, struct mv_u3d_ep, ep);
953 u3d = ep->u3d;
954 if (!ep->ep.desc) {
955 status = -EINVAL;
956 goto out;
957 }
958
959 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
960 status = -EOPNOTSUPP;
961 goto out;
962 }
963
964 /*
965 * Attempt to halt IN ep will fail if any transfer requests
966 * are still queue
967 */
968 if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN)
969 && !list_empty(&ep->queue)) {
970 status = -EAGAIN;
971 goto out;
972 }
973
974 spin_lock_irqsave(&ep->u3d->lock, flags);
975 mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt);
976 if (halt && wedge)
977 ep->wedge = 1;
978 else if (!halt)
979 ep->wedge = 0;
980 spin_unlock_irqrestore(&ep->u3d->lock, flags);
981
982 if (ep->ep_num == 0)
983 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
984 out:
985 return status;
986 }
987
988 static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt)
989 {
990 return mv_u3d_ep_set_halt_wedge(_ep, halt, 0);
991 }
992
993 static int mv_u3d_ep_set_wedge(struct usb_ep *_ep)
994 {
995 return mv_u3d_ep_set_halt_wedge(_ep, 1, 1);
996 }
997
998 static const struct usb_ep_ops mv_u3d_ep_ops = {
999 .enable = mv_u3d_ep_enable,
1000 .disable = mv_u3d_ep_disable,
1001
1002 .alloc_request = mv_u3d_alloc_request,
1003 .free_request = mv_u3d_free_request,
1004
1005 .queue = mv_u3d_ep_queue,
1006 .dequeue = mv_u3d_ep_dequeue,
1007
1008 .set_wedge = mv_u3d_ep_set_wedge,
1009 .set_halt = mv_u3d_ep_set_halt,
1010 .fifo_flush = mv_u3d_ep_fifo_flush,
1011 };
1012
1013 static void mv_u3d_controller_stop(struct mv_u3d *u3d)
1014 {
1015 u32 tmp;
1016
1017 if (!u3d->clock_gating && u3d->vbus_valid_detect)
1018 iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID,
1019 &u3d->vuc_regs->intrenable);
1020 else
1021 iowrite32(0, &u3d->vuc_regs->intrenable);
1022 iowrite32(~0x0, &u3d->vuc_regs->endcomplete);
1023 iowrite32(~0x0, &u3d->vuc_regs->trbunderrun);
1024 iowrite32(~0x0, &u3d->vuc_regs->trbcomplete);
1025 iowrite32(~0x0, &u3d->vuc_regs->linkchange);
1026 iowrite32(0x1, &u3d->vuc_regs->setuplock);
1027
1028 /* Reset the RUN bit in the command register to stop USB */
1029 tmp = ioread32(&u3d->op_regs->usbcmd);
1030 tmp &= ~MV_U3D_CMD_RUN_STOP;
1031 iowrite32(tmp, &u3d->op_regs->usbcmd);
1032 dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n",
1033 ioread32(&u3d->op_regs->usbcmd));
1034 }
1035
1036 static void mv_u3d_controller_start(struct mv_u3d *u3d)
1037 {
1038 u32 usbintr;
1039 u32 temp;
1040
1041 /* enable link LTSSM state machine */
1042 temp = ioread32(&u3d->vuc_regs->ltssm);
1043 temp |= MV_U3D_LTSSM_PHY_INIT_DONE;
1044 iowrite32(temp, &u3d->vuc_regs->ltssm);
1045
1046 /* Enable interrupts */
1047 usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR |
1048 MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE |
1049 MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP |
1050 (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0);
1051 iowrite32(usbintr, &u3d->vuc_regs->intrenable);
1052
1053 /* Enable ctrl ep */
1054 iowrite32(0x1, &u3d->vuc_regs->ctrlepenable);
1055
1056 /* Set the Run bit in the command register */
1057 iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd);
1058 dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n",
1059 ioread32(&u3d->op_regs->usbcmd));
1060 }
1061
1062 static int mv_u3d_controller_reset(struct mv_u3d *u3d)
1063 {
1064 unsigned int loops;
1065 u32 tmp;
1066
1067 /* Stop the controller */
1068 tmp = ioread32(&u3d->op_regs->usbcmd);
1069 tmp &= ~MV_U3D_CMD_RUN_STOP;
1070 iowrite32(tmp, &u3d->op_regs->usbcmd);
1071
1072 /* Reset the controller to get default values */
1073 iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd);
1074
1075 /* wait for reset to complete */
1076 loops = LOOPS(MV_U3D_RESET_TIMEOUT);
1077 while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) {
1078 if (loops == 0) {
1079 dev_err(u3d->dev,
1080 "Wait for RESET completed TIMEOUT\n");
1081 return -ETIMEDOUT;
1082 }
1083 loops--;
1084 udelay(LOOPS_USEC);
1085 }
1086
1087 /* Configure the Endpoint Context Address */
1088 iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl);
1089 iowrite32(0, &u3d->op_regs->dcbaaph);
1090
1091 return 0;
1092 }
1093
1094 static int mv_u3d_enable(struct mv_u3d *u3d)
1095 {
1096 struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1097 int retval;
1098
1099 if (u3d->active)
1100 return 0;
1101
1102 if (!u3d->clock_gating) {
1103 u3d->active = 1;
1104 return 0;
1105 }
1106
1107 dev_dbg(u3d->dev, "enable u3d\n");
1108 clk_enable(u3d->clk);
1109 if (pdata->phy_init) {
1110 retval = pdata->phy_init(u3d->phy_regs);
1111 if (retval) {
1112 dev_err(u3d->dev,
1113 "init phy error %d\n", retval);
1114 clk_disable(u3d->clk);
1115 return retval;
1116 }
1117 }
1118 u3d->active = 1;
1119
1120 return 0;
1121 }
1122
1123 static void mv_u3d_disable(struct mv_u3d *u3d)
1124 {
1125 struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1126 if (u3d->clock_gating && u3d->active) {
1127 dev_dbg(u3d->dev, "disable u3d\n");
1128 if (pdata->phy_deinit)
1129 pdata->phy_deinit(u3d->phy_regs);
1130 clk_disable(u3d->clk);
1131 u3d->active = 0;
1132 }
1133 }
1134
1135 static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active)
1136 {
1137 struct mv_u3d *u3d;
1138 unsigned long flags;
1139 int retval = 0;
1140
1141 u3d = container_of(gadget, struct mv_u3d, gadget);
1142
1143 spin_lock_irqsave(&u3d->lock, flags);
1144
1145 u3d->vbus_active = (is_active != 0);
1146 dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1147 __func__, u3d->softconnect, u3d->vbus_active);
1148 /*
1149 * 1. external VBUS detect: we can disable/enable clock on demand.
1150 * 2. UDC VBUS detect: we have to enable clock all the time.
1151 * 3. No VBUS detect: we have to enable clock all the time.
1152 */
1153 if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1154 retval = mv_u3d_enable(u3d);
1155 if (retval == 0) {
1156 /*
1157 * after clock is disabled, we lost all the register
1158 * context. We have to re-init registers
1159 */
1160 mv_u3d_controller_reset(u3d);
1161 mv_u3d_ep0_reset(u3d);
1162 mv_u3d_controller_start(u3d);
1163 }
1164 } else if (u3d->driver && u3d->softconnect) {
1165 if (!u3d->active)
1166 goto out;
1167
1168 /* stop all the transfer in queue*/
1169 mv_u3d_stop_activity(u3d, u3d->driver);
1170 mv_u3d_controller_stop(u3d);
1171 mv_u3d_disable(u3d);
1172 }
1173
1174 out:
1175 spin_unlock_irqrestore(&u3d->lock, flags);
1176 return retval;
1177 }
1178
1179 /* constrain controller's VBUS power usage
1180 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1181 * reporting how much power the device may consume. For example, this
1182 * could affect how quickly batteries are recharged.
1183 *
1184 * Returns zero on success, else negative errno.
1185 */
1186 static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1187 {
1188 struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1189
1190 u3d->power = mA;
1191
1192 return 0;
1193 }
1194
1195 static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on)
1196 {
1197 struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1198 unsigned long flags;
1199 int retval = 0;
1200
1201 spin_lock_irqsave(&u3d->lock, flags);
1202
1203 dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1204 __func__, u3d->softconnect, u3d->vbus_active);
1205 u3d->softconnect = (is_on != 0);
1206 if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1207 retval = mv_u3d_enable(u3d);
1208 if (retval == 0) {
1209 /*
1210 * after clock is disabled, we lost all the register
1211 * context. We have to re-init registers
1212 */
1213 mv_u3d_controller_reset(u3d);
1214 mv_u3d_ep0_reset(u3d);
1215 mv_u3d_controller_start(u3d);
1216 }
1217 } else if (u3d->driver && u3d->vbus_active) {
1218 /* stop all the transfer in queue*/
1219 mv_u3d_stop_activity(u3d, u3d->driver);
1220 mv_u3d_controller_stop(u3d);
1221 mv_u3d_disable(u3d);
1222 }
1223
1224 spin_unlock_irqrestore(&u3d->lock, flags);
1225
1226 return retval;
1227 }
1228
1229 static int mv_u3d_start(struct usb_gadget *g,
1230 struct usb_gadget_driver *driver)
1231 {
1232 struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1233 struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1234 unsigned long flags;
1235
1236 if (u3d->driver)
1237 return -EBUSY;
1238
1239 spin_lock_irqsave(&u3d->lock, flags);
1240
1241 if (!u3d->clock_gating) {
1242 clk_enable(u3d->clk);
1243 if (pdata->phy_init)
1244 pdata->phy_init(u3d->phy_regs);
1245 }
1246
1247 /* hook up the driver ... */
1248 driver->driver.bus = NULL;
1249 u3d->driver = driver;
1250
1251 u3d->ep0_dir = USB_DIR_OUT;
1252
1253 spin_unlock_irqrestore(&u3d->lock, flags);
1254
1255 u3d->vbus_valid_detect = 1;
1256
1257 return 0;
1258 }
1259
1260 static int mv_u3d_stop(struct usb_gadget *g)
1261 {
1262 struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1263 struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1264 unsigned long flags;
1265
1266 u3d->vbus_valid_detect = 0;
1267 spin_lock_irqsave(&u3d->lock, flags);
1268
1269 /* enable clock to access controller register */
1270 clk_enable(u3d->clk);
1271 if (pdata->phy_init)
1272 pdata->phy_init(u3d->phy_regs);
1273
1274 mv_u3d_controller_stop(u3d);
1275 /* stop all usb activities */
1276 u3d->gadget.speed = USB_SPEED_UNKNOWN;
1277 mv_u3d_stop_activity(u3d, NULL);
1278 mv_u3d_disable(u3d);
1279
1280 if (pdata->phy_deinit)
1281 pdata->phy_deinit(u3d->phy_regs);
1282 clk_disable(u3d->clk);
1283
1284 spin_unlock_irqrestore(&u3d->lock, flags);
1285
1286 u3d->driver = NULL;
1287
1288 return 0;
1289 }
1290
1291 /* device controller usb_gadget_ops structure */
1292 static const struct usb_gadget_ops mv_u3d_ops = {
1293 /* notify controller that VBUS is powered or not */
1294 .vbus_session = mv_u3d_vbus_session,
1295
1296 /* constrain controller's VBUS power usage */
1297 .vbus_draw = mv_u3d_vbus_draw,
1298
1299 .pullup = mv_u3d_pullup,
1300 .udc_start = mv_u3d_start,
1301 .udc_stop = mv_u3d_stop,
1302 };
1303
1304 static int mv_u3d_eps_init(struct mv_u3d *u3d)
1305 {
1306 struct mv_u3d_ep *ep;
1307 char name[14];
1308 int i;
1309
1310 /* initialize ep0, ep0 in/out use eps[1] */
1311 ep = &u3d->eps[1];
1312 ep->u3d = u3d;
1313 strncpy(ep->name, "ep0", sizeof(ep->name));
1314 ep->ep.name = ep->name;
1315 ep->ep.ops = &mv_u3d_ep_ops;
1316 ep->wedge = 0;
1317 usb_ep_set_maxpacket_limit(&ep->ep, MV_U3D_EP0_MAX_PKT_SIZE);
1318 ep->ep.caps.type_control = true;
1319 ep->ep.caps.dir_in = true;
1320 ep->ep.caps.dir_out = true;
1321 ep->ep_num = 0;
1322 ep->ep.desc = &mv_u3d_ep0_desc;
1323 INIT_LIST_HEAD(&ep->queue);
1324 INIT_LIST_HEAD(&ep->req_list);
1325 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1326
1327 /* add ep0 ep_context */
1328 ep->ep_context = &u3d->ep_context[1];
1329
1330 /* initialize other endpoints */
1331 for (i = 2; i < u3d->max_eps * 2; i++) {
1332 ep = &u3d->eps[i];
1333 if (i & 1) {
1334 snprintf(name, sizeof(name), "ep%din", i >> 1);
1335 ep->direction = MV_U3D_EP_DIR_IN;
1336 ep->ep.caps.dir_in = true;
1337 } else {
1338 snprintf(name, sizeof(name), "ep%dout", i >> 1);
1339 ep->direction = MV_U3D_EP_DIR_OUT;
1340 ep->ep.caps.dir_out = true;
1341 }
1342 ep->u3d = u3d;
1343 strncpy(ep->name, name, sizeof(ep->name));
1344 ep->ep.name = ep->name;
1345
1346 ep->ep.caps.type_iso = true;
1347 ep->ep.caps.type_bulk = true;
1348 ep->ep.caps.type_int = true;
1349
1350 ep->ep.ops = &mv_u3d_ep_ops;
1351 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
1352 ep->ep_num = i / 2;
1353
1354 INIT_LIST_HEAD(&ep->queue);
1355 list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list);
1356
1357 INIT_LIST_HEAD(&ep->req_list);
1358 spin_lock_init(&ep->req_lock);
1359 ep->ep_context = &u3d->ep_context[i];
1360 }
1361
1362 return 0;
1363 }
1364
1365 /* delete all endpoint requests, called with spinlock held */
1366 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status)
1367 {
1368 /* endpoint fifo flush */
1369 mv_u3d_ep_fifo_flush(&ep->ep);
1370
1371 while (!list_empty(&ep->queue)) {
1372 struct mv_u3d_req *req = NULL;
1373 req = list_entry(ep->queue.next, struct mv_u3d_req, queue);
1374 mv_u3d_done(ep, req, status);
1375 }
1376 }
1377
1378 /* stop all USB activities */
1379 static
1380 void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver)
1381 {
1382 struct mv_u3d_ep *ep;
1383
1384 mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN);
1385
1386 list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) {
1387 mv_u3d_nuke(ep, -ESHUTDOWN);
1388 }
1389
1390 /* report disconnect; the driver is already quiesced */
1391 if (driver) {
1392 spin_unlock(&u3d->lock);
1393 driver->disconnect(&u3d->gadget);
1394 spin_lock(&u3d->lock);
1395 }
1396 }
1397
1398 static void mv_u3d_irq_process_error(struct mv_u3d *u3d)
1399 {
1400 /* Increment the error count */
1401 u3d->errors++;
1402 dev_err(u3d->dev, "%s\n", __func__);
1403 }
1404
1405 static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d)
1406 {
1407 u32 linkchange;
1408
1409 linkchange = ioread32(&u3d->vuc_regs->linkchange);
1410 iowrite32(linkchange, &u3d->vuc_regs->linkchange);
1411
1412 dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange);
1413
1414 if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) {
1415 dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n",
1416 ioread32(&u3d->vuc_regs->ltssmstate));
1417
1418 u3d->usb_state = USB_STATE_DEFAULT;
1419 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1420 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
1421
1422 /* set speed */
1423 u3d->gadget.speed = USB_SPEED_SUPER;
1424 }
1425
1426 if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) {
1427 dev_dbg(u3d->dev, "link suspend\n");
1428 u3d->resume_state = u3d->usb_state;
1429 u3d->usb_state = USB_STATE_SUSPENDED;
1430 }
1431
1432 if (linkchange & MV_U3D_LINK_CHANGE_RESUME) {
1433 dev_dbg(u3d->dev, "link resume\n");
1434 u3d->usb_state = u3d->resume_state;
1435 u3d->resume_state = 0;
1436 }
1437
1438 if (linkchange & MV_U3D_LINK_CHANGE_WRESET) {
1439 dev_dbg(u3d->dev, "warm reset\n");
1440 u3d->usb_state = USB_STATE_POWERED;
1441 }
1442
1443 if (linkchange & MV_U3D_LINK_CHANGE_HRESET) {
1444 dev_dbg(u3d->dev, "hot reset\n");
1445 u3d->usb_state = USB_STATE_DEFAULT;
1446 }
1447
1448 if (linkchange & MV_U3D_LINK_CHANGE_INACT)
1449 dev_dbg(u3d->dev, "inactive\n");
1450
1451 if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0)
1452 dev_dbg(u3d->dev, "ss.disabled\n");
1453
1454 if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) {
1455 dev_dbg(u3d->dev, "vbus invalid\n");
1456 u3d->usb_state = USB_STATE_ATTACHED;
1457 u3d->vbus_valid_detect = 1;
1458 /* if external vbus detect is not supported,
1459 * we handle it here.
1460 */
1461 if (!u3d->vbus) {
1462 spin_unlock(&u3d->lock);
1463 mv_u3d_vbus_session(&u3d->gadget, 0);
1464 spin_lock(&u3d->lock);
1465 }
1466 }
1467 }
1468
1469 static void mv_u3d_ch9setaddress(struct mv_u3d *u3d,
1470 struct usb_ctrlrequest *setup)
1471 {
1472 u32 tmp;
1473
1474 if (u3d->usb_state != USB_STATE_DEFAULT) {
1475 dev_err(u3d->dev,
1476 "%s, cannot setaddr in this state (%d)\n",
1477 __func__, u3d->usb_state);
1478 goto err;
1479 }
1480
1481 u3d->dev_addr = (u8)setup->wValue;
1482
1483 dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr);
1484
1485 if (u3d->dev_addr > 127) {
1486 dev_err(u3d->dev,
1487 "%s, u3d address is wrong (out of range)\n", __func__);
1488 u3d->dev_addr = 0;
1489 goto err;
1490 }
1491
1492 /* update usb state */
1493 u3d->usb_state = USB_STATE_ADDRESS;
1494
1495 /* set the new address */
1496 tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr);
1497 tmp &= ~0x7F;
1498 tmp |= (u32)u3d->dev_addr;
1499 iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr);
1500
1501 return;
1502 err:
1503 mv_u3d_ep0_stall(u3d);
1504 }
1505
1506 static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup)
1507 {
1508 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1509 if (setup->bRequest == USB_REQ_SET_CONFIGURATION)
1510 return 1;
1511
1512 return 0;
1513 }
1514
1515 static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num,
1516 struct usb_ctrlrequest *setup)
1517 __releases(&u3c->lock)
1518 __acquires(&u3c->lock)
1519 {
1520 bool delegate = false;
1521
1522 mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN);
1523
1524 dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1525 setup->bRequestType, setup->bRequest,
1526 setup->wValue, setup->wIndex, setup->wLength);
1527
1528 /* We process some stardard setup requests here */
1529 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1530 switch (setup->bRequest) {
1531 case USB_REQ_GET_STATUS:
1532 delegate = true;
1533 break;
1534
1535 case USB_REQ_SET_ADDRESS:
1536 mv_u3d_ch9setaddress(u3d, setup);
1537 break;
1538
1539 case USB_REQ_CLEAR_FEATURE:
1540 delegate = true;
1541 break;
1542
1543 case USB_REQ_SET_FEATURE:
1544 delegate = true;
1545 break;
1546
1547 default:
1548 delegate = true;
1549 }
1550 } else
1551 delegate = true;
1552
1553 /* delegate USB standard requests to the gadget driver */
1554 if (delegate == true) {
1555 /* USB requests handled by gadget */
1556 if (setup->wLength) {
1557 /* DATA phase from gadget, STATUS phase from u3d */
1558 u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1559 ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT;
1560 spin_unlock(&u3d->lock);
1561 if (u3d->driver->setup(&u3d->gadget,
1562 &u3d->local_setup_buff) < 0) {
1563 dev_err(u3d->dev, "setup error!\n");
1564 mv_u3d_ep0_stall(u3d);
1565 }
1566 spin_lock(&u3d->lock);
1567 } else {
1568 /* no DATA phase, STATUS phase from gadget */
1569 u3d->ep0_dir = MV_U3D_EP_DIR_IN;
1570 u3d->ep0_state = MV_U3D_STATUS_STAGE;
1571 spin_unlock(&u3d->lock);
1572 if (u3d->driver->setup(&u3d->gadget,
1573 &u3d->local_setup_buff) < 0)
1574 mv_u3d_ep0_stall(u3d);
1575 spin_lock(&u3d->lock);
1576 }
1577
1578 if (mv_u3d_is_set_configuration(setup)) {
1579 dev_dbg(u3d->dev, "u3d configured\n");
1580 u3d->usb_state = USB_STATE_CONFIGURED;
1581 }
1582 }
1583 }
1584
1585 static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr)
1586 {
1587 struct mv_u3d_ep_context *epcontext;
1588
1589 epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN];
1590
1591 /* Copy the setup packet to local buffer */
1592 memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8);
1593 }
1594
1595 static void mv_u3d_irq_process_setup(struct mv_u3d *u3d)
1596 {
1597 u32 tmp, i;
1598 /* Process all Setup packet received interrupts */
1599 tmp = ioread32(&u3d->vuc_regs->setuplock);
1600 if (tmp) {
1601 for (i = 0; i < u3d->max_eps; i++) {
1602 if (tmp & (1 << i)) {
1603 mv_u3d_get_setup_data(u3d, i,
1604 (u8 *)(&u3d->local_setup_buff));
1605 mv_u3d_handle_setup_packet(u3d, i,
1606 &u3d->local_setup_buff);
1607 }
1608 }
1609 }
1610
1611 iowrite32(tmp, &u3d->vuc_regs->setuplock);
1612 }
1613
1614 static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d)
1615 {
1616 u32 tmp, bit_pos;
1617 int i, ep_num = 0, direction = 0;
1618 struct mv_u3d_ep *curr_ep;
1619 struct mv_u3d_req *curr_req, *temp_req;
1620 int status;
1621
1622 tmp = ioread32(&u3d->vuc_regs->endcomplete);
1623
1624 dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp);
1625 if (!tmp)
1626 return;
1627 iowrite32(tmp, &u3d->vuc_regs->endcomplete);
1628
1629 for (i = 0; i < u3d->max_eps * 2; i++) {
1630 ep_num = i >> 1;
1631 direction = i % 2;
1632
1633 bit_pos = 1 << (ep_num + 16 * direction);
1634
1635 if (!(bit_pos & tmp))
1636 continue;
1637
1638 if (i == 0)
1639 curr_ep = &u3d->eps[1];
1640 else
1641 curr_ep = &u3d->eps[i];
1642
1643 /* remove req out of ep request list after completion */
1644 dev_dbg(u3d->dev, "tr comp: check req_list\n");
1645 spin_lock(&curr_ep->req_lock);
1646 if (!list_empty(&curr_ep->req_list)) {
1647 struct mv_u3d_req *req;
1648 req = list_entry(curr_ep->req_list.next,
1649 struct mv_u3d_req, list);
1650 list_del_init(&req->list);
1651 curr_ep->processing = 0;
1652 }
1653 spin_unlock(&curr_ep->req_lock);
1654
1655 /* process the req queue until an uncomplete request */
1656 list_for_each_entry_safe(curr_req, temp_req,
1657 &curr_ep->queue, queue) {
1658 status = mv_u3d_process_ep_req(u3d, i, curr_req);
1659 if (status)
1660 break;
1661 /* write back status to req */
1662 curr_req->req.status = status;
1663
1664 /* ep0 request completion */
1665 if (ep_num == 0) {
1666 mv_u3d_done(curr_ep, curr_req, 0);
1667 break;
1668 } else {
1669 mv_u3d_done(curr_ep, curr_req, status);
1670 }
1671 }
1672
1673 dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n");
1674 mv_u3d_start_queue(curr_ep);
1675 }
1676 }
1677
1678 static irqreturn_t mv_u3d_irq(int irq, void *dev)
1679 {
1680 struct mv_u3d *u3d = (struct mv_u3d *)dev;
1681 u32 status, intr;
1682 u32 bridgesetting;
1683 u32 trbunderrun;
1684
1685 spin_lock(&u3d->lock);
1686
1687 status = ioread32(&u3d->vuc_regs->intrcause);
1688 intr = ioread32(&u3d->vuc_regs->intrenable);
1689 status &= intr;
1690
1691 if (status == 0) {
1692 spin_unlock(&u3d->lock);
1693 dev_err(u3d->dev, "irq error!\n");
1694 return IRQ_NONE;
1695 }
1696
1697 if (status & MV_U3D_USBINT_VBUS_VALID) {
1698 bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting);
1699 if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) {
1700 /* write vbus valid bit of bridge setting to clear */
1701 bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID;
1702 iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting);
1703 dev_dbg(u3d->dev, "vbus valid\n");
1704
1705 u3d->usb_state = USB_STATE_POWERED;
1706 u3d->vbus_valid_detect = 0;
1707 /* if external vbus detect is not supported,
1708 * we handle it here.
1709 */
1710 if (!u3d->vbus) {
1711 spin_unlock(&u3d->lock);
1712 mv_u3d_vbus_session(&u3d->gadget, 1);
1713 spin_lock(&u3d->lock);
1714 }
1715 } else
1716 dev_err(u3d->dev, "vbus bit is not set\n");
1717 }
1718
1719 /* RX data is already in the 16KB FIFO.*/
1720 if (status & MV_U3D_USBINT_UNDER_RUN) {
1721 trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun);
1722 dev_err(u3d->dev, "under run, ep%d\n", trbunderrun);
1723 iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun);
1724 mv_u3d_irq_process_error(u3d);
1725 }
1726
1727 if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) {
1728 /* write one to clear */
1729 iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR
1730 | MV_U3D_USBINT_TXDESC_ERR),
1731 &u3d->vuc_regs->intrcause);
1732 dev_err(u3d->dev, "desc err 0x%x\n", status);
1733 mv_u3d_irq_process_error(u3d);
1734 }
1735
1736 if (status & MV_U3D_USBINT_LINK_CHG)
1737 mv_u3d_irq_process_link_change(u3d);
1738
1739 if (status & MV_U3D_USBINT_TX_COMPLETE)
1740 mv_u3d_irq_process_tr_complete(u3d);
1741
1742 if (status & MV_U3D_USBINT_RX_COMPLETE)
1743 mv_u3d_irq_process_tr_complete(u3d);
1744
1745 if (status & MV_U3D_USBINT_SETUP)
1746 mv_u3d_irq_process_setup(u3d);
1747
1748 spin_unlock(&u3d->lock);
1749 return IRQ_HANDLED;
1750 }
1751
1752 static int mv_u3d_remove(struct platform_device *dev)
1753 {
1754 struct mv_u3d *u3d = platform_get_drvdata(dev);
1755
1756 BUG_ON(u3d == NULL);
1757
1758 usb_del_gadget_udc(&u3d->gadget);
1759
1760 /* free memory allocated in probe */
1761 dma_pool_destroy(u3d->trb_pool);
1762
1763 if (u3d->ep_context)
1764 dma_free_coherent(&dev->dev, u3d->ep_context_size,
1765 u3d->ep_context, u3d->ep_context_dma);
1766
1767 kfree(u3d->eps);
1768
1769 if (u3d->irq)
1770 free_irq(u3d->irq, u3d);
1771
1772 if (u3d->cap_regs)
1773 iounmap(u3d->cap_regs);
1774 u3d->cap_regs = NULL;
1775
1776 kfree(u3d->status_req);
1777
1778 clk_put(u3d->clk);
1779
1780 kfree(u3d);
1781
1782 return 0;
1783 }
1784
1785 static int mv_u3d_probe(struct platform_device *dev)
1786 {
1787 struct mv_u3d *u3d = NULL;
1788 struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev);
1789 int retval = 0;
1790 struct resource *r;
1791 size_t size;
1792
1793 if (!dev_get_platdata(&dev->dev)) {
1794 dev_err(&dev->dev, "missing platform_data\n");
1795 retval = -ENODEV;
1796 goto err_pdata;
1797 }
1798
1799 u3d = kzalloc(sizeof(*u3d), GFP_KERNEL);
1800 if (!u3d) {
1801 retval = -ENOMEM;
1802 goto err_alloc_private;
1803 }
1804
1805 spin_lock_init(&u3d->lock);
1806
1807 platform_set_drvdata(dev, u3d);
1808
1809 u3d->dev = &dev->dev;
1810 u3d->vbus = pdata->vbus;
1811
1812 u3d->clk = clk_get(&dev->dev, NULL);
1813 if (IS_ERR(u3d->clk)) {
1814 retval = PTR_ERR(u3d->clk);
1815 goto err_get_clk;
1816 }
1817
1818 r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs");
1819 if (!r) {
1820 dev_err(&dev->dev, "no I/O memory resource defined\n");
1821 retval = -ENODEV;
1822 goto err_get_cap_regs;
1823 }
1824
1825 u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *)
1826 ioremap(r->start, resource_size(r));
1827 if (!u3d->cap_regs) {
1828 dev_err(&dev->dev, "failed to map I/O memory\n");
1829 retval = -EBUSY;
1830 goto err_map_cap_regs;
1831 } else {
1832 dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n",
1833 (unsigned long) r->start,
1834 (unsigned long) u3d->cap_regs);
1835 }
1836
1837 /* we will access controller register, so enable the u3d controller */
1838 clk_enable(u3d->clk);
1839
1840 if (pdata->phy_init) {
1841 retval = pdata->phy_init(u3d->phy_regs);
1842 if (retval) {
1843 dev_err(&dev->dev, "init phy error %d\n", retval);
1844 goto err_u3d_enable;
1845 }
1846 }
1847
1848 u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs
1849 + MV_U3D_USB3_OP_REGS_OFFSET);
1850
1851 u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs
1852 + ioread32(&u3d->cap_regs->vuoff));
1853
1854 u3d->max_eps = 16;
1855
1856 /*
1857 * some platform will use usb to download image, it may not disconnect
1858 * usb gadget before loading kernel. So first stop u3d here.
1859 */
1860 mv_u3d_controller_stop(u3d);
1861 iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause);
1862
1863 if (pdata->phy_deinit)
1864 pdata->phy_deinit(u3d->phy_regs);
1865 clk_disable(u3d->clk);
1866
1867 size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2;
1868 size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1)
1869 & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1);
1870 u3d->ep_context = dma_alloc_coherent(&dev->dev, size,
1871 &u3d->ep_context_dma, GFP_KERNEL);
1872 if (!u3d->ep_context) {
1873 dev_err(&dev->dev, "allocate ep context memory failed\n");
1874 retval = -ENOMEM;
1875 goto err_alloc_ep_context;
1876 }
1877 u3d->ep_context_size = size;
1878
1879 /* create TRB dma_pool resource */
1880 u3d->trb_pool = dma_pool_create("u3d_trb",
1881 &dev->dev,
1882 sizeof(struct mv_u3d_trb_hw),
1883 MV_U3D_TRB_ALIGNMENT,
1884 MV_U3D_DMA_BOUNDARY);
1885
1886 if (!u3d->trb_pool) {
1887 retval = -ENOMEM;
1888 goto err_alloc_trb_pool;
1889 }
1890
1891 size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2;
1892 u3d->eps = kzalloc(size, GFP_KERNEL);
1893 if (!u3d->eps) {
1894 retval = -ENOMEM;
1895 goto err_alloc_eps;
1896 }
1897
1898 /* initialize ep0 status request structure */
1899 u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL);
1900 if (!u3d->status_req) {
1901 retval = -ENOMEM;
1902 goto err_alloc_status_req;
1903 }
1904 INIT_LIST_HEAD(&u3d->status_req->queue);
1905
1906 /* allocate a small amount of memory to get valid address */
1907 u3d->status_req->req.buf = (char *)u3d->status_req
1908 + sizeof(struct mv_u3d_req);
1909 u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf);
1910
1911 u3d->resume_state = USB_STATE_NOTATTACHED;
1912 u3d->usb_state = USB_STATE_ATTACHED;
1913 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1914 u3d->remote_wakeup = 0;
1915
1916 r = platform_get_resource(dev, IORESOURCE_IRQ, 0);
1917 if (!r) {
1918 dev_err(&dev->dev, "no IRQ resource defined\n");
1919 retval = -ENODEV;
1920 goto err_get_irq;
1921 }
1922 u3d->irq = r->start;
1923 if (request_irq(u3d->irq, mv_u3d_irq,
1924 IRQF_SHARED, driver_name, u3d)) {
1925 u3d->irq = 0;
1926 dev_err(&dev->dev, "Request irq %d for u3d failed\n",
1927 u3d->irq);
1928 retval = -ENODEV;
1929 goto err_request_irq;
1930 }
1931
1932 /* initialize gadget structure */
1933 u3d->gadget.ops = &mv_u3d_ops; /* usb_gadget_ops */
1934 u3d->gadget.ep0 = &u3d->eps[1].ep; /* gadget ep0 */
1935 INIT_LIST_HEAD(&u3d->gadget.ep_list); /* ep_list */
1936 u3d->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
1937
1938 /* the "gadget" abstracts/virtualizes the controller */
1939 u3d->gadget.name = driver_name; /* gadget name */
1940
1941 mv_u3d_eps_init(u3d);
1942
1943 /* external vbus detection */
1944 if (u3d->vbus) {
1945 u3d->clock_gating = 1;
1946 dev_err(&dev->dev, "external vbus detection\n");
1947 }
1948
1949 if (!u3d->clock_gating)
1950 u3d->vbus_active = 1;
1951
1952 /* enable usb3 controller vbus detection */
1953 u3d->vbus_valid_detect = 1;
1954
1955 retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget);
1956 if (retval)
1957 goto err_unregister;
1958
1959 dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n",
1960 u3d->clock_gating ? "with" : "without");
1961
1962 return 0;
1963
1964 err_unregister:
1965 free_irq(u3d->irq, u3d);
1966 err_request_irq:
1967 err_get_irq:
1968 kfree(u3d->status_req);
1969 err_alloc_status_req:
1970 kfree(u3d->eps);
1971 err_alloc_eps:
1972 dma_pool_destroy(u3d->trb_pool);
1973 err_alloc_trb_pool:
1974 dma_free_coherent(&dev->dev, u3d->ep_context_size,
1975 u3d->ep_context, u3d->ep_context_dma);
1976 err_alloc_ep_context:
1977 if (pdata->phy_deinit)
1978 pdata->phy_deinit(u3d->phy_regs);
1979 clk_disable(u3d->clk);
1980 err_u3d_enable:
1981 iounmap(u3d->cap_regs);
1982 err_map_cap_regs:
1983 err_get_cap_regs:
1984 err_get_clk:
1985 clk_put(u3d->clk);
1986 kfree(u3d);
1987 err_alloc_private:
1988 err_pdata:
1989 return retval;
1990 }
1991
1992 #ifdef CONFIG_PM_SLEEP
1993 static int mv_u3d_suspend(struct device *dev)
1994 {
1995 struct mv_u3d *u3d = dev_get_drvdata(dev);
1996
1997 /*
1998 * only cable is unplugged, usb can suspend.
1999 * So do not care about clock_gating == 1, it is handled by
2000 * vbus session.
2001 */
2002 if (!u3d->clock_gating) {
2003 mv_u3d_controller_stop(u3d);
2004
2005 spin_lock_irq(&u3d->lock);
2006 /* stop all usb activities */
2007 mv_u3d_stop_activity(u3d, u3d->driver);
2008 spin_unlock_irq(&u3d->lock);
2009
2010 mv_u3d_disable(u3d);
2011 }
2012
2013 return 0;
2014 }
2015
2016 static int mv_u3d_resume(struct device *dev)
2017 {
2018 struct mv_u3d *u3d = dev_get_drvdata(dev);
2019 int retval;
2020
2021 if (!u3d->clock_gating) {
2022 retval = mv_u3d_enable(u3d);
2023 if (retval)
2024 return retval;
2025
2026 if (u3d->driver && u3d->softconnect) {
2027 mv_u3d_controller_reset(u3d);
2028 mv_u3d_ep0_reset(u3d);
2029 mv_u3d_controller_start(u3d);
2030 }
2031 }
2032
2033 return 0;
2034 }
2035 #endif
2036
2037 static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume);
2038
2039 static void mv_u3d_shutdown(struct platform_device *dev)
2040 {
2041 struct mv_u3d *u3d = platform_get_drvdata(dev);
2042 u32 tmp;
2043
2044 tmp = ioread32(&u3d->op_regs->usbcmd);
2045 tmp &= ~MV_U3D_CMD_RUN_STOP;
2046 iowrite32(tmp, &u3d->op_regs->usbcmd);
2047 }
2048
2049 static struct platform_driver mv_u3d_driver = {
2050 .probe = mv_u3d_probe,
2051 .remove = mv_u3d_remove,
2052 .shutdown = mv_u3d_shutdown,
2053 .driver = {
2054 .name = "mv-u3d",
2055 .pm = &mv_u3d_pm_ops,
2056 },
2057 };
2058
2059 module_platform_driver(mv_u3d_driver);
2060 MODULE_ALIAS("platform:mv-u3d");
2061 MODULE_DESCRIPTION(DRIVER_DESC);
2062 MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>");
2063 MODULE_LICENSE("GPL");
Linux with added FPC-III support