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[S390] Remove error checking from copy_oldmem_page()
[linux/fpc-iii.git] / drivers / gpio / gpio-ep93xx.c
blob7aafbb4373396661dc1afc15b4606c11c77bb20c
1 /*
2 * Generic EP93xx GPIO handling
3 *
4 * Copyright (c) 2008 Ryan Mallon
5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
6 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
22 #include <linux/slab.h>
23 #include <linux/basic_mmio_gpio.h>
24
25 #include <mach/hardware.h>
26 #include <mach/gpio-ep93xx.h>
27
28 #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
29
30 struct ep93xx_gpio {
31 void __iomem *mmio_base;
32 struct bgpio_chip bgc[8];
33 };
34
35 /*************************************************************************
36 * Interrupt handling for EP93xx on-chip GPIOs
37 *************************************************************************/
38 static unsigned char gpio_int_unmasked[3];
39 static unsigned char gpio_int_enabled[3];
40 static unsigned char gpio_int_type1[3];
41 static unsigned char gpio_int_type2[3];
42 static unsigned char gpio_int_debounce[3];
43
44 /* Port ordering is: A B F */
45 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
46 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
47 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
48 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
49 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
50
51 static void ep93xx_gpio_update_int_params(unsigned port)
52 {
53 BUG_ON(port > 2);
54
55 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
56
57 __raw_writeb(gpio_int_type2[port],
58 EP93XX_GPIO_REG(int_type2_register_offset[port]));
59
60 __raw_writeb(gpio_int_type1[port],
61 EP93XX_GPIO_REG(int_type1_register_offset[port]));
62
63 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
64 EP93XX_GPIO_REG(int_en_register_offset[port]));
65 }
66
67 static inline void ep93xx_gpio_int_mask(unsigned line)
68 {
69 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
70 }
71
72 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
73 {
74 int line = irq_to_gpio(irq);
75 int port = line >> 3;
76 int port_mask = 1 << (line & 7);
77
78 if (enable)
79 gpio_int_debounce[port] |= port_mask;
80 else
81 gpio_int_debounce[port] &= ~port_mask;
82
83 __raw_writeb(gpio_int_debounce[port],
84 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
85 }
86
87 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
88 {
89 unsigned char status;
90 int i;
91
92 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
93 for (i = 0; i < 8; i++) {
94 if (status & (1 << i)) {
95 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
96 generic_handle_irq(gpio_irq);
97 }
98 }
99
100 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
101 for (i = 0; i < 8; i++) {
102 if (status & (1 << i)) {
103 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
104 generic_handle_irq(gpio_irq);
105 }
106 }
107 }
108
109 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
110 {
111 /*
112 * map discontiguous hw irq range to continuous sw irq range:
113 *
114 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
115 */
116 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
117 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
118
119 generic_handle_irq(gpio_irq);
120 }
121
122 static void ep93xx_gpio_irq_ack(struct irq_data *d)
123 {
124 int line = irq_to_gpio(d->irq);
125 int port = line >> 3;
126 int port_mask = 1 << (line & 7);
127
128 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
129 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
130 ep93xx_gpio_update_int_params(port);
131 }
132
133 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
134 }
135
136 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
137 {
138 int line = irq_to_gpio(d->irq);
139 int port = line >> 3;
140 int port_mask = 1 << (line & 7);
141
142 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
143 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
144
145 gpio_int_unmasked[port] &= ~port_mask;
146 ep93xx_gpio_update_int_params(port);
147
148 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
149 }
150
151 static void ep93xx_gpio_irq_mask(struct irq_data *d)
152 {
153 int line = irq_to_gpio(d->irq);
154 int port = line >> 3;
155
156 gpio_int_unmasked[port] &= ~(1 << (line & 7));
157 ep93xx_gpio_update_int_params(port);
158 }
159
160 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
161 {
162 int line = irq_to_gpio(d->irq);
163 int port = line >> 3;
164
165 gpio_int_unmasked[port] |= 1 << (line & 7);
166 ep93xx_gpio_update_int_params(port);
167 }
168
169 /*
170 * gpio_int_type1 controls whether the interrupt is level (0) or
171 * edge (1) triggered, while gpio_int_type2 controls whether it
172 * triggers on low/falling (0) or high/rising (1).
173 */
174 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
175 {
176 const int gpio = irq_to_gpio(d->irq);
177 const int port = gpio >> 3;
178 const int port_mask = 1 << (gpio & 7);
179 irq_flow_handler_t handler;
180
181 gpio_direction_input(gpio);
182
183 switch (type) {
184 case IRQ_TYPE_EDGE_RISING:
185 gpio_int_type1[port] |= port_mask;
186 gpio_int_type2[port] |= port_mask;
187 handler = handle_edge_irq;
188 break;
189 case IRQ_TYPE_EDGE_FALLING:
190 gpio_int_type1[port] |= port_mask;
191 gpio_int_type2[port] &= ~port_mask;
192 handler = handle_edge_irq;
193 break;
194 case IRQ_TYPE_LEVEL_HIGH:
195 gpio_int_type1[port] &= ~port_mask;
196 gpio_int_type2[port] |= port_mask;
197 handler = handle_level_irq;
198 break;
199 case IRQ_TYPE_LEVEL_LOW:
200 gpio_int_type1[port] &= ~port_mask;
201 gpio_int_type2[port] &= ~port_mask;
202 handler = handle_level_irq;
203 break;
204 case IRQ_TYPE_EDGE_BOTH:
205 gpio_int_type1[port] |= port_mask;
206 /* set initial polarity based on current input level */
207 if (gpio_get_value(gpio))
208 gpio_int_type2[port] &= ~port_mask; /* falling */
209 else
210 gpio_int_type2[port] |= port_mask; /* rising */
211 handler = handle_edge_irq;
212 break;
213 default:
214 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
215 return -EINVAL;
216 }
217
218 __irq_set_handler_locked(d->irq, handler);
219
220 gpio_int_enabled[port] |= port_mask;
221
222 ep93xx_gpio_update_int_params(port);
223
224 return 0;
225 }
226
227 static struct irq_chip ep93xx_gpio_irq_chip = {
228 .name = "GPIO",
229 .irq_ack = ep93xx_gpio_irq_ack,
230 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
231 .irq_mask = ep93xx_gpio_irq_mask,
232 .irq_unmask = ep93xx_gpio_irq_unmask,
233 .irq_set_type = ep93xx_gpio_irq_type,
234 };
235
236 static void ep93xx_gpio_init_irq(void)
237 {
238 int gpio_irq;
239
240 for (gpio_irq = gpio_to_irq(0);
241 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
242 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
243 handle_level_irq);
244 set_irq_flags(gpio_irq, IRQF_VALID);
245 }
246
247 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
248 ep93xx_gpio_ab_irq_handler);
249 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
250 ep93xx_gpio_f_irq_handler);
251 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
252 ep93xx_gpio_f_irq_handler);
253 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
254 ep93xx_gpio_f_irq_handler);
255 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
256 ep93xx_gpio_f_irq_handler);
257 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
258 ep93xx_gpio_f_irq_handler);
259 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
260 ep93xx_gpio_f_irq_handler);
261 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
262 ep93xx_gpio_f_irq_handler);
263 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
264 ep93xx_gpio_f_irq_handler);
265 }
266
267
268 /*************************************************************************
269 * gpiolib interface for EP93xx on-chip GPIOs
270 *************************************************************************/
271 struct ep93xx_gpio_bank {
272 const char *label;
273 int data;
274 int dir;
275 int base;
276 bool has_debounce;
277 };
278
279 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
280 { \
281 .label = _label, \
282 .data = _data, \
283 .dir = _dir, \
284 .base = _base, \
285 .has_debounce = _debounce, \
286 }
287
288 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
289 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
290 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
291 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
292 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
293 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
294 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
295 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
296 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
297 };
298
299 static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
300 unsigned offset, unsigned debounce)
301 {
302 int gpio = chip->base + offset;
303 int irq = gpio_to_irq(gpio);
304
305 if (irq < 0)
306 return -EINVAL;
307
308 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
309
310 return 0;
311 }
312
313 /*
314 * Map GPIO A0..A7 (0..7) to irq 64..71,
315 * B0..B7 (7..15) to irq 72..79, and
316 * F0..F7 (16..24) to irq 80..87.
317 */
318 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
319 {
320 int gpio = chip->base + offset;
321
322 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
323 return -EINVAL;
324
325 return 64 + gpio;
326 }
327
328 static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
329 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
330 {
331 void __iomem *data = mmio_base + bank->data;
332 void __iomem *dir = mmio_base + bank->dir;
333 int err;
334
335 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
336 if (err)
337 return err;
338
339 bgc->gc.label = bank->label;
340 bgc->gc.base = bank->base;
341
342 if (bank->has_debounce) {
343 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
344 bgc->gc.to_irq = ep93xx_gpio_to_irq;
345 }
346
347 return gpiochip_add(&bgc->gc);
348 }
349
350 static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
351 {
352 struct ep93xx_gpio *ep93xx_gpio;
353 struct resource *res;
354 void __iomem *mmio;
355 int i;
356 int ret;
357
358 ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
359 if (!ep93xx_gpio)
360 return -ENOMEM;
361
362 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
363 if (!res) {
364 ret = -ENXIO;
365 goto exit_free;
366 }
367
368 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
369 ret = -EBUSY;
370 goto exit_free;
371 }
372
373 mmio = ioremap(res->start, resource_size(res));
374 if (!mmio) {
375 ret = -ENXIO;
376 goto exit_release;
377 }
378 ep93xx_gpio->mmio_base = mmio;
379
380 /* Default all ports to GPIO */
381 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
382 EP93XX_SYSCON_DEVCFG_GONK |
383 EP93XX_SYSCON_DEVCFG_EONIDE |
384 EP93XX_SYSCON_DEVCFG_GONIDE |
385 EP93XX_SYSCON_DEVCFG_HONIDE);
386
387 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
388 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
389 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
390
391 if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
392 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
393 bank->label);
394 }
395
396 ep93xx_gpio_init_irq();
397
398 return 0;
399
400 exit_release:
401 release_mem_region(res->start, resource_size(res));
402 exit_free:
403 kfree(ep93xx_gpio);
404 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
405 return ret;
406 }
407
408 static struct platform_driver ep93xx_gpio_driver = {
409 .driver = {
410 .name = "gpio-ep93xx",
411 .owner = THIS_MODULE,
412 },
413 .probe = ep93xx_gpio_probe,
414 };
415
416 static int __init ep93xx_gpio_init(void)
417 {
418 return platform_driver_register(&ep93xx_gpio_driver);
419 }
420 postcore_initcall(ep93xx_gpio_init);
421
422 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
423 "H Hartley Sweeten <hsweeten@visionengravers.com>");
424 MODULE_DESCRIPTION("EP93XX GPIO driver");
425 MODULE_LICENSE("GPL");
Linux with added FPC-III support