drivers/gpu/drm/nouveau/nouveau_dp.c

   1 /*
   2  * Copyright 2009 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_i2c.h"
  29 #include "nouveau_connector.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_crtc.h"
  32
  33 /******************************************************************************
  34  * aux channel util functions
  35  *****************************************************************************/
  36 #define AUX_DBG(fmt, args...) do {                                             \
  37         if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) {                     \
  38                 NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args);     \
  39         }                                                                      \
  40 } while (0)
  41 #define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
  42
  43 static void
  44 auxch_fini(struct drm_device *dev, int ch)
  45 {
  46         nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
  47 }
  48
  49 static int
  50 auxch_init(struct drm_device *dev, int ch)
  51 {
  52         const u32 unksel = 1; /* nfi which to use, or if it matters.. */
  53         const u32 ureq = unksel ? 0x00100000 : 0x00200000;
  54         const u32 urep = unksel ? 0x01000000 : 0x02000000;
  55         u32 ctrl, timeout;
  56
  57         /* wait up to 1ms for any previous transaction to be done... */
  58         timeout = 1000;
  59         do {
  60                 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
  61                 udelay(1);
  62                 if (!timeout--) {
  63                         AUX_ERR("begin idle timeout 0x%08x", ctrl);
  64                         return -EBUSY;
  65                 }
  66         } while (ctrl & 0x03010000);
  67
  68         /* set some magic, and wait up to 1ms for it to appear */
  69         nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
  70         timeout = 1000;
  71         do {
  72                 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
  73                 udelay(1);
  74                 if (!timeout--) {
  75                         AUX_ERR("magic wait 0x%08x\n", ctrl);
  76                         auxch_fini(dev, ch);
  77                         return -EBUSY;
  78                 }
  79         } while ((ctrl & 0x03000000) != urep);
  80
  81         return 0;
  82 }
  83
  84 static int
  85 auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
  86 {
  87         u32 ctrl, stat, timeout, retries;
  88         u32 xbuf[4] = {};
  89         int ret, i;
  90
  91         AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
  92
  93         ret = auxch_init(dev, ch);
  94         if (ret)
  95                 goto out;
  96
  97         stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
  98         if (!(stat & 0x10000000)) {
  99                 AUX_DBG("sink not detected\n");
 100                 ret = -ENXIO;
 101                 goto out;
 102         }
 103
 104         if (!(type & 1)) {
 105                 memcpy(xbuf, data, size);
 106                 for (i = 0; i < 16; i += 4) {
 107                         AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
 108                         nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
 109                 }
 110         }
 111
 112         ctrl  = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
 113         ctrl &= ~0x0001f0ff;
 114         ctrl |= type << 12;
 115         ctrl |= size - 1;
 116         nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
 117
 118         /* retry transaction a number of times on failure... */
 119         ret = -EREMOTEIO;
 120         for (retries = 0; retries < 32; retries++) {
 121                 /* reset, and delay a while if this is a retry */
 122                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
 123                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
 124                 if (retries)
 125                         udelay(400);
 126
 127                 /* transaction request, wait up to 1ms for it to complete */
 128                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
 129
 130                 timeout = 1000;
 131                 do {
 132                         ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
 133                         udelay(1);
 134                         if (!timeout--) {
 135                                 AUX_ERR("tx req timeout 0x%08x\n", ctrl);
 136                                 goto out;
 137                         }
 138                 } while (ctrl & 0x00010000);
 139
 140                 /* read status, and check if transaction completed ok */
 141                 stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
 142                 if (!(stat & 0x000f0f00)) {
 143                         ret = 0;
 144                         break;
 145                 }
 146
 147                 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
 148         }
 149
 150         if (type & 1) {
 151                 for (i = 0; i < 16; i += 4) {
 152                         xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
 153                         AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
 154                 }
 155                 memcpy(data, xbuf, size);
 156         }
 157
 158 out:
 159         auxch_fini(dev, ch);
 160         return ret;
 161 }
 162
 163 static u32
 164 dp_link_bw_get(struct drm_device *dev, int or, int link)
 165 {
 166         u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
 167         if (!(ctrl & 0x000c0000))
 168                 return 162000;
 169         return 270000;
 170 }
 171
 172 static int
 173 dp_lane_count_get(struct drm_device *dev, int or, int link)
 174 {
 175         u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 176         switch (ctrl & 0x000f0000) {
 177         case 0x00010000: return 1;
 178         case 0x00030000: return 2;
 179         default:
 180                 return 4;
 181         }
 182 }
 183
 184 void
 185 nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
 186 {
 187         const u32 symbol = 100000;
 188         int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
 189         int TU, VTUi, VTUf, VTUa;
 190         u64 link_data_rate, link_ratio, unk;
 191         u32 best_diff = 64 * symbol;
 192         u32 link_nr, link_bw, r;
 193
 194         /* calculate packed data rate for each lane */
 195         link_nr = dp_lane_count_get(dev, or, link);
 196         link_data_rate = (clk * bpp / 8) / link_nr;
 197
 198         /* calculate ratio of packed data rate to link symbol rate */
 199         link_bw = dp_link_bw_get(dev, or, link);
 200         link_ratio = link_data_rate * symbol;
 201         r = do_div(link_ratio, link_bw);
 202
 203         for (TU = 64; TU >= 32; TU--) {
 204                 /* calculate average number of valid symbols in each TU */
 205                 u32 tu_valid = link_ratio * TU;
 206                 u32 calc, diff;
 207
 208                 /* find a hw representation for the fraction.. */
 209                 VTUi = tu_valid / symbol;
 210                 calc = VTUi * symbol;
 211                 diff = tu_valid - calc;
 212                 if (diff) {
 213                         if (diff >= (symbol / 2)) {
 214                                 VTUf = symbol / (symbol - diff);
 215                                 if (symbol - (VTUf * diff))
 216                                         VTUf++;
 217
 218                                 if (VTUf <= 15) {
 219                                         VTUa  = 1;
 220                                         calc += symbol - (symbol / VTUf);
 221                                 } else {
 222                                         VTUa  = 0;
 223                                         VTUf  = 1;
 224                                         calc += symbol;
 225                                 }
 226                         } else {
 227                                 VTUa  = 0;
 228                                 VTUf  = min((int)(symbol / diff), 15);
 229                                 calc += symbol / VTUf;
 230                         }
 231
 232                         diff = calc - tu_valid;
 233                 } else {
 234                         /* no remainder, but the hw doesn't like the fractional
 235                          * part to be zero.  decrement the integer part and
 236                          * have the fraction add a whole symbol back
 237                          */
 238                         VTUa = 0;
 239                         VTUf = 1;
 240                         VTUi--;
 241                 }
 242
 243                 if (diff < best_diff) {
 244                         best_diff = diff;
 245                         bestTU = TU;
 246                         bestVTUa = VTUa;
 247                         bestVTUf = VTUf;
 248                         bestVTUi = VTUi;
 249                         if (diff == 0)
 250                                 break;
 251                 }
 252         }
 253
 254         if (!bestTU) {
 255                 NV_ERROR(dev, "DP: unable to find suitable config\n");
 256                 return;
 257         }
 258
 259         /* XXX close to vbios numbers, but not right */
 260         unk  = (symbol - link_ratio) * bestTU;
 261         unk *= link_ratio;
 262         r = do_div(unk, symbol);
 263         r = do_div(unk, symbol);
 264         unk += 6;
 265
 266         nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
 267         nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
 268                                                              bestVTUf << 16 |
 269                                                              bestVTUi << 8 |
 270                                                              unk);
 271 }
 272
 273 u8 *
 274 nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
 275 {
 276         struct drm_nouveau_private *dev_priv = dev->dev_private;
 277         struct nvbios *bios = &dev_priv->vbios;
 278         struct bit_entry d;
 279         u8 *table;
 280         int i;
 281
 282         if (bit_table(dev, 'd', &d)) {
 283                 NV_ERROR(dev, "BIT 'd' table not found\n");
 284                 return NULL;
 285         }
 286
 287         if (d.version != 1) {
 288                 NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
 289                 return NULL;
 290         }
 291
 292         table = ROMPTR(bios, d.data[0]);
 293         if (!table) {
 294                 NV_ERROR(dev, "displayport table pointer invalid\n");
 295                 return NULL;
 296         }
 297
 298         switch (table[0]) {
 299         case 0x20:
 300         case 0x21:
 301         case 0x30:
 302                 break;
 303         default:
 304                 NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
 305                 return NULL;
 306         }
 307
 308         for (i = 0; i < table[3]; i++) {
 309                 *entry = ROMPTR(bios, table[table[1] + (i * table[2])]);
 310                 if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
 311                         return table;
 312         }
 313
 314         NV_ERROR(dev, "displayport encoder table not found\n");
 315         return NULL;
 316 }
 317
 318 /******************************************************************************
 319  * link training
 320  *****************************************************************************/
 321 struct dp_state {
 322         struct dcb_entry *dcb;
 323         u8 *table;
 324         u8 *entry;
 325         int auxch;
 326         int crtc;
 327         int or;
 328         int link;
 329         u8 *dpcd;
 330         int link_nr;
 331         u32 link_bw;
 332         u8  stat[6];
 333         u8  conf[4];
 334 };
 335
 336 static void
 337 dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
 338 {
 339         struct drm_nouveau_private *dev_priv = dev->dev_private;
 340         int or = dp->or, link = dp->link;
 341         u8 *entry, sink[2];
 342         u32 dp_ctrl;
 343         u16 script;
 344
 345         NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
 346
 347         /* set selected link rate on source */
 348         switch (dp->link_bw) {
 349         case 270000:
 350                 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
 351                 sink[0] = DP_LINK_BW_2_7;
 352                 break;
 353         default:
 354                 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
 355                 sink[0] = DP_LINK_BW_1_62;
 356                 break;
 357         }
 358
 359         /* offset +0x0a of each dp encoder table entry is a pointer to another
 360          * table, that has (among other things) pointers to more scripts that
 361          * need to be executed, this time depending on link speed.
 362          */
 363         entry = ROMPTR(&dev_priv->vbios, dp->entry[10]);
 364         if (entry) {
 365                 if (dp->table[0] < 0x30) {
 366                         while (dp->link_bw < (ROM16(entry[0]) * 10))
 367                                 entry += 4;
 368                         script = ROM16(entry[2]);
 369                 } else {
 370                         while (dp->link_bw < (entry[0] * 27000))
 371                                 entry += 3;
 372                         script = ROM16(entry[1]);
 373                 }
 374
 375                 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
 376         }
 377
 378         /* configure lane count on the source */
 379         dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
 380         sink[1] = dp->link_nr;
 381         if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) {
 382                 dp_ctrl |= 0x00004000;
 383                 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 384         }
 385
 386         nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
 387
 388         /* inform the sink of the new configuration */
 389         auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
 390 }
 391
 392 static void
 393 dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
 394 {
 395         u8 sink_tp;
 396
 397         NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
 398
 399         nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
 400
 401         auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
 402         sink_tp &= ~DP_TRAINING_PATTERN_MASK;
 403         sink_tp |= tp;
 404         auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
 405 }
 406
 407 static const u8 nv50_lane_map[] = { 16, 8, 0, 24 };
 408 static const u8 nvaf_lane_map[] = { 24, 16, 8, 0 };
 409
 410 static int
 411 dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
 412 {
 413         struct drm_nouveau_private *dev_priv = dev->dev_private;
 414         u32 mask = 0, drv = 0, pre = 0, unk = 0;
 415         const u8 *shifts;
 416         int link = dp->link;
 417         int or = dp->or;
 418         int i;
 419
 420         if (dev_priv->chipset != 0xaf)
 421                 shifts = nv50_lane_map;
 422         else
 423                 shifts = nvaf_lane_map;
 424
 425         for (i = 0; i < dp->link_nr; i++) {
 426                 u8 *conf = dp->entry + dp->table[4];
 427                 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
 428                 u8 lpre = (lane & 0x0c) >> 2;
 429                 u8 lvsw = (lane & 0x03) >> 0;
 430
 431                 mask |= 0xff << shifts[i];
 432                 unk |= 1 << (shifts[i] >> 3);
 433
 434                 dp->conf[i] = (lpre << 3) | lvsw;
 435                 if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
 436                         dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
 437                 if (lpre == DP_TRAIN_PRE_EMPHASIS_9_5)
 438                         dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 439
 440                 NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
 441
 442                 if (dp->table[0] < 0x30) {
 443                         u8 *last = conf + (dp->entry[4] * dp->table[5]);
 444                         while (lvsw != conf[0] || lpre != conf[1]) {
 445                                 conf += dp->table[5];
 446                                 if (conf >= last)
 447                                         return -EINVAL;
 448                         }
 449
 450                         conf += 2;
 451                 } else {
 452                         /* no lookup table anymore, set entries for each
 453                          * combination of voltage swing and pre-emphasis
 454                          * level allowed by the DP spec.
 455                          */
 456                         switch (lvsw) {
 457                         case 0: lpre += 0; break;
 458                         case 1: lpre += 4; break;
 459                         case 2: lpre += 7; break;
 460                         case 3: lpre += 9; break;
 461                         }
 462
 463                         conf = conf + (lpre * dp->table[5]);
 464                         conf++;
 465                 }
 466
 467                 drv |= conf[0] << shifts[i];
 468                 pre |= conf[1] << shifts[i];
 469                 unk  = (unk & ~0x0000ff00) | (conf[2] << 8);
 470         }
 471
 472         nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
 473         nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
 474         nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
 475
 476         return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
 477 }
 478
 479 static int
 480 dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
 481 {
 482         int ret;
 483
 484         udelay(delay);
 485
 486         ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
 487         if (ret)
 488                 return ret;
 489
 490         NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
 491                      dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
 492                      dp->stat[4], dp->stat[5]);
 493         return 0;
 494 }
 495
 496 static int
 497 dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
 498 {
 499         bool cr_done = false, abort = false;
 500         int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 501         int tries = 0, i;
 502
 503         dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
 504
 505         do {
 506                 if (dp_link_train_commit(dev, dp) ||
 507                     dp_link_train_update(dev, dp, 100))
 508                         break;
 509
 510                 cr_done = true;
 511                 for (i = 0; i < dp->link_nr; i++) {
 512                         u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 513                         if (!(lane & DP_LANE_CR_DONE)) {
 514                                 cr_done = false;
 515                                 if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
 516                                         abort = true;
 517                                 break;
 518                         }
 519                 }
 520
 521                 if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
 522                         voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 523                         tries = 0;
 524                 }
 525         } while (!cr_done && !abort && ++tries < 5);
 526
 527         return cr_done ? 0 : -1;
 528 }
 529
 530 static int
 531 dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
 532 {
 533         bool eq_done, cr_done = true;
 534         int tries = 0, i;
 535
 536         dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
 537
 538         do {
 539                 if (dp_link_train_update(dev, dp, 400))
 540                         break;
 541
 542                 eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
 543                 for (i = 0; i < dp->link_nr && eq_done; i++) {
 544                         u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 545                         if (!(lane & DP_LANE_CR_DONE))
 546                                 cr_done = false;
 547                         if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
 548                             !(lane & DP_LANE_SYMBOL_LOCKED))
 549                                 eq_done = false;
 550                 }
 551
 552                 if (dp_link_train_commit(dev, dp))
 553                         break;
 554         } while (!eq_done && cr_done && ++tries <= 5);
 555
 556         return eq_done ? 0 : -1;
 557 }
 558
 559 bool
 560 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
 561 {
 562         struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
 563         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 564         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 565         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 566         struct nouveau_connector *nv_connector =
 567                 nouveau_encoder_connector_get(nv_encoder);
 568         struct drm_device *dev = encoder->dev;
 569         struct nouveau_i2c_chan *auxch;
 570         const u32 bw_list[] = { 270000, 162000, 0 };
 571         const u32 *link_bw = bw_list;
 572         struct dp_state dp;
 573
 574         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
 575         if (!auxch)
 576                 return false;
 577
 578         dp.table = nouveau_dp_bios_data(dev, nv_encoder->dcb, &dp.entry);
 579         if (!dp.table)
 580                 return -EINVAL;
 581
 582         dp.dcb = nv_encoder->dcb;
 583         dp.crtc = nv_crtc->index;
 584         dp.auxch = auxch->rd;
 585         dp.or = nv_encoder->or;
 586         dp.link = !(nv_encoder->dcb->sorconf.link & 1);
 587         dp.dpcd = nv_encoder->dp.dpcd;
 588
 589         /* some sinks toggle hotplug in response to some of the actions
 590          * we take during link training (DP_SET_POWER is one), we need
 591          * to ignore them for the moment to avoid races.
 592          */
 593         pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
 594
 595         /* enable down-spreading, if possible */
 596         if (dp.table[1] >= 16) {
 597                 u16 script = ROM16(dp.entry[14]);
 598                 if (nv_encoder->dp.dpcd[3] & 1)
 599                         script = ROM16(dp.entry[12]);
 600
 601                 nouveau_bios_run_init_table(dev, script, dp.dcb, dp.crtc);
 602         }
 603
 604         /* execute pre-train script from vbios */
 605         nouveau_bios_run_init_table(dev, ROM16(dp.entry[6]), dp.dcb, dp.crtc);
 606
 607         /* start off at highest link rate supported by encoder and display */
 608         while (*link_bw > nv_encoder->dp.link_bw)
 609                 link_bw++;
 610
 611         while (link_bw[0]) {
 612                 /* find minimum required lane count at this link rate */
 613                 dp.link_nr = nv_encoder->dp.link_nr;
 614                 while ((dp.link_nr >> 1) * link_bw[0] > datarate)
 615                         dp.link_nr >>= 1;
 616
 617                 /* drop link rate to minimum with this lane count */
 618                 while ((link_bw[1] * dp.link_nr) > datarate)
 619                         link_bw++;
 620                 dp.link_bw = link_bw[0];
 621
 622                 /* program selected link configuration */
 623                 dp_set_link_config(dev, &dp);
 624
 625                 /* attempt to train the link at this configuration */
 626                 memset(dp.stat, 0x00, sizeof(dp.stat));
 627                 if (!dp_link_train_cr(dev, &dp) &&
 628                     !dp_link_train_eq(dev, &dp))
 629                         break;
 630
 631                 /* retry at lower rate */
 632                 link_bw++;
 633         }
 634
 635         /* finish link training */
 636         dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
 637
 638         /* execute post-train script from vbios */
 639         nouveau_bios_run_init_table(dev, ROM16(dp.entry[8]), dp.dcb, dp.crtc);
 640
 641         /* re-enable hotplug detect */
 642         pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true);
 643         return true;
 644 }
 645
 646 bool
 647 nouveau_dp_detect(struct drm_encoder *encoder)
 648 {
 649         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 650         struct drm_device *dev = encoder->dev;
 651         struct nouveau_i2c_chan *auxch;
 652         u8 *dpcd = nv_encoder->dp.dpcd;
 653         int ret;
 654
 655         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
 656         if (!auxch)
 657                 return false;
 658
 659         ret = auxch_tx(dev, auxch->rd, 9, DP_DPCD_REV, dpcd, 8);
 660         if (ret)
 661                 return false;
 662
 663         nv_encoder->dp.link_bw = 27000 * dpcd[1];
 664         nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
 665
 666         NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
 667                      nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
 668         NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
 669                      nv_encoder->dcb->dpconf.link_nr,
 670                      nv_encoder->dcb->dpconf.link_bw);
 671
 672         if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
 673                 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
 674         if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
 675                 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
 676
 677         NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
 678                      nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
 679
 680         return true;
 681 }
 682
 683 int
 684 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
 685                  uint8_t *data, int data_nr)
 686 {
 687         return auxch_tx(auxch->dev, auxch->rd, cmd, addr, data, data_nr);
 688 }
 689
 690 static int
 691 nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 692 {
 693         struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
 694         struct i2c_msg *msg = msgs;
 695         int ret, mcnt = num;
 696
 697         while (mcnt--) {
 698                 u8 remaining = msg->len;
 699                 u8 *ptr = msg->buf;
 700
 701                 while (remaining) {
 702                         u8 cnt = (remaining > 16) ? 16 : remaining;
 703                         u8 cmd;
 704
 705                         if (msg->flags & I2C_M_RD)
 706                                 cmd = AUX_I2C_READ;
 707                         else
 708                                 cmd = AUX_I2C_WRITE;
 709
 710                         if (mcnt || remaining > 16)
 711                                 cmd |= AUX_I2C_MOT;
 712
 713                         ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
 714                         if (ret < 0)
 715                                 return ret;
 716
 717                         ptr += cnt;
 718                         remaining -= cnt;
 719                 }
 720
 721                 msg++;
 722         }
 723
 724         return num;
 725 }
 726
 727 static u32
 728 nouveau_dp_i2c_func(struct i2c_adapter *adap)
 729 {
 730         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 731 }
 732
 733 const struct i2c_algorithm nouveau_dp_i2c_algo = {
 734         .master_xfer = nouveau_dp_i2c_xfer,
 735         .functionality = nouveau_dp_i2c_func
 736 };