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[S390] Remove error checking from copy_oldmem_page()
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
blob29837da1098b3a85a50bbc9ee4ccc2b0a4901dab
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 spinlock_t lock;
50 struct list_head channels;
51 struct nouveau_vm *vm;
52 };
53
54 static inline struct nouveau_fpriv *
55 nouveau_fpriv(struct drm_file *file_priv)
56 {
57 return file_priv ? file_priv->driver_priv : NULL;
58 }
59
60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
61
62 #include "nouveau_drm.h"
63 #include "nouveau_reg.h"
64 #include "nouveau_bios.h"
65 #include "nouveau_util.h"
66
67 struct nouveau_grctx;
68 struct nouveau_mem;
69 #include "nouveau_vm.h"
70
71 #define MAX_NUM_DCB_ENTRIES 16
72
73 #define NOUVEAU_MAX_CHANNEL_NR 128
74 #define NOUVEAU_MAX_TILE_NR 15
75
76 struct nouveau_mem {
77 struct drm_device *dev;
78
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
81 u8 page_shift;
82
83 struct drm_mm_node *tag;
84 struct list_head regions;
85 dma_addr_t *pages;
86 u32 memtype;
87 u64 offset;
88 u64 size;
89 };
90
91 struct nouveau_tile_reg {
92 bool used;
93 uint32_t addr;
94 uint32_t limit;
95 uint32_t pitch;
96 uint32_t zcomp;
97 struct drm_mm_node *tag_mem;
98 struct nouveau_fence *fence;
99 };
100
101 struct nouveau_bo {
102 struct ttm_buffer_object bo;
103 struct ttm_placement placement;
104 u32 valid_domains;
105 u32 placements[3];
106 u32 busy_placements[3];
107 struct ttm_bo_kmap_obj kmap;
108 struct list_head head;
109
110 /* protected by ttm_bo_reserve() */
111 struct drm_file *reserved_by;
112 struct list_head entry;
113 int pbbo_index;
114 bool validate_mapped;
115
116 struct nouveau_channel *channel;
117
118 struct list_head vma_list;
119 unsigned page_shift;
120
121 uint32_t tile_mode;
122 uint32_t tile_flags;
123 struct nouveau_tile_reg *tile;
124
125 struct drm_gem_object *gem;
126 int pin_refcnt;
127 };
128
129 #define nouveau_bo_tile_layout(nvbo) \
130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
131
132 static inline struct nouveau_bo *
133 nouveau_bo(struct ttm_buffer_object *bo)
134 {
135 return container_of(bo, struct nouveau_bo, bo);
136 }
137
138 static inline struct nouveau_bo *
139 nouveau_gem_object(struct drm_gem_object *gem)
140 {
141 return gem ? gem->driver_private : NULL;
142 }
143
144 /* TODO: submit equivalent to TTM generic API upstream? */
145 static inline void __iomem *
146 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
147 {
148 bool is_iomem;
149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
150 &nvbo->kmap, &is_iomem);
151 WARN_ON_ONCE(ioptr && !is_iomem);
152 return ioptr;
153 }
154
155 enum nouveau_flags {
156 NV_NFORCE = 0x10000000,
157 NV_NFORCE2 = 0x20000000
158 };
159
160 #define NVOBJ_ENGINE_SW 0
161 #define NVOBJ_ENGINE_GR 1
162 #define NVOBJ_ENGINE_CRYPT 2
163 #define NVOBJ_ENGINE_COPY0 3
164 #define NVOBJ_ENGINE_COPY1 4
165 #define NVOBJ_ENGINE_MPEG 5
166 #define NVOBJ_ENGINE_DISPLAY 15
167 #define NVOBJ_ENGINE_NR 16
168
169 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
170 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
171 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
172 #define NVOBJ_FLAG_VM (1 << 3)
173 #define NVOBJ_FLAG_VM_USER (1 << 4)
174
175 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
176
177 struct nouveau_gpuobj {
178 struct drm_device *dev;
179 struct kref refcount;
180 struct list_head list;
181
182 void *node;
183 u32 *suspend;
184
185 uint32_t flags;
186
187 u32 size;
188 u32 pinst; /* PRAMIN BAR offset */
189 u32 cinst; /* Channel offset */
190 u64 vinst; /* VRAM address */
191 u64 linst; /* VM address */
192
193 uint32_t engine;
194 uint32_t class;
195
196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
197 void *priv;
198 };
199
200 struct nouveau_page_flip_state {
201 struct list_head head;
202 struct drm_pending_vblank_event *event;
203 int crtc, bpp, pitch, x, y;
204 uint64_t offset;
205 };
206
207 enum nouveau_channel_mutex_class {
208 NOUVEAU_UCHANNEL_MUTEX,
209 NOUVEAU_KCHANNEL_MUTEX
210 };
211
212 struct nouveau_channel {
213 struct drm_device *dev;
214 struct list_head list;
215 int id;
216
217 /* references to the channel data structure */
218 struct kref ref;
219 /* users of the hardware channel resources, the hardware
220 * context will be kicked off when it reaches zero. */
221 atomic_t users;
222 struct mutex mutex;
223
224 /* owner of this fifo */
225 struct drm_file *file_priv;
226 /* mapping of the fifo itself */
227 struct drm_local_map *map;
228
229 /* mapping of the regs controlling the fifo */
230 void __iomem *user;
231 uint32_t user_get;
232 uint32_t user_put;
233
234 /* Fencing */
235 struct {
236 /* lock protects the pending list only */
237 spinlock_t lock;
238 struct list_head pending;
239 uint32_t sequence;
240 uint32_t sequence_ack;
241 atomic_t last_sequence_irq;
242 struct nouveau_vma vma;
243 } fence;
244
245 /* DMA push buffer */
246 struct nouveau_gpuobj *pushbuf;
247 struct nouveau_bo *pushbuf_bo;
248 struct nouveau_vma pushbuf_vma;
249 uint32_t pushbuf_base;
250
251 /* Notifier memory */
252 struct nouveau_bo *notifier_bo;
253 struct nouveau_vma notifier_vma;
254 struct drm_mm notifier_heap;
255
256 /* PFIFO context */
257 struct nouveau_gpuobj *ramfc;
258 struct nouveau_gpuobj *cache;
259 void *fifo_priv;
260
261 /* Execution engine contexts */
262 void *engctx[NVOBJ_ENGINE_NR];
263
264 /* NV50 VM */
265 struct nouveau_vm *vm;
266 struct nouveau_gpuobj *vm_pd;
267
268 /* Objects */
269 struct nouveau_gpuobj *ramin; /* Private instmem */
270 struct drm_mm ramin_heap; /* Private PRAMIN heap */
271 struct nouveau_ramht *ramht; /* Hash table */
272
273 /* GPU object info for stuff used in-kernel (mm_enabled) */
274 uint32_t m2mf_ntfy;
275 uint32_t vram_handle;
276 uint32_t gart_handle;
277 bool accel_done;
278
279 /* Push buffer state (only for drm's channel on !mm_enabled) */
280 struct {
281 int max;
282 int free;
283 int cur;
284 int put;
285 /* access via pushbuf_bo */
286
287 int ib_base;
288 int ib_max;
289 int ib_free;
290 int ib_put;
291 } dma;
292
293 uint32_t sw_subchannel[8];
294
295 struct nouveau_vma dispc_vma[2];
296 struct {
297 struct nouveau_gpuobj *vblsem;
298 uint32_t vblsem_head;
299 uint32_t vblsem_offset;
300 uint32_t vblsem_rval;
301 struct list_head vbl_wait;
302 struct list_head flip;
303 } nvsw;
304
305 struct {
306 bool active;
307 char name[32];
308 struct drm_info_list info;
309 } debugfs;
310 };
311
312 struct nouveau_exec_engine {
313 void (*destroy)(struct drm_device *, int engine);
314 int (*init)(struct drm_device *, int engine);
315 int (*fini)(struct drm_device *, int engine, bool suspend);
316 int (*context_new)(struct nouveau_channel *, int engine);
317 void (*context_del)(struct nouveau_channel *, int engine);
318 int (*object_new)(struct nouveau_channel *, int engine,
319 u32 handle, u16 class);
320 void (*set_tile_region)(struct drm_device *dev, int i);
321 void (*tlb_flush)(struct drm_device *, int engine);
322 };
323
324 struct nouveau_instmem_engine {
325 void *priv;
326
327 int (*init)(struct drm_device *dev);
328 void (*takedown)(struct drm_device *dev);
329 int (*suspend)(struct drm_device *dev);
330 void (*resume)(struct drm_device *dev);
331
332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
333 u32 size, u32 align);
334 void (*put)(struct nouveau_gpuobj *);
335 int (*map)(struct nouveau_gpuobj *);
336 void (*unmap)(struct nouveau_gpuobj *);
337
338 void (*flush)(struct drm_device *);
339 };
340
341 struct nouveau_mc_engine {
342 int (*init)(struct drm_device *dev);
343 void (*takedown)(struct drm_device *dev);
344 };
345
346 struct nouveau_timer_engine {
347 int (*init)(struct drm_device *dev);
348 void (*takedown)(struct drm_device *dev);
349 uint64_t (*read)(struct drm_device *dev);
350 };
351
352 struct nouveau_fb_engine {
353 int num_tiles;
354 struct drm_mm tag_heap;
355 void *priv;
356
357 int (*init)(struct drm_device *dev);
358 void (*takedown)(struct drm_device *dev);
359
360 void (*init_tile_region)(struct drm_device *dev, int i,
361 uint32_t addr, uint32_t size,
362 uint32_t pitch, uint32_t flags);
363 void (*set_tile_region)(struct drm_device *dev, int i);
364 void (*free_tile_region)(struct drm_device *dev, int i);
365 };
366
367 struct nouveau_fifo_engine {
368 void *priv;
369 int channels;
370
371 struct nouveau_gpuobj *playlist[2];
372 int cur_playlist;
373
374 int (*init)(struct drm_device *);
375 void (*takedown)(struct drm_device *);
376
377 void (*disable)(struct drm_device *);
378 void (*enable)(struct drm_device *);
379 bool (*reassign)(struct drm_device *, bool enable);
380 bool (*cache_pull)(struct drm_device *dev, bool enable);
381
382 int (*channel_id)(struct drm_device *);
383
384 int (*create_context)(struct nouveau_channel *);
385 void (*destroy_context)(struct nouveau_channel *);
386 int (*load_context)(struct nouveau_channel *);
387 int (*unload_context)(struct drm_device *);
388 void (*tlb_flush)(struct drm_device *dev);
389 };
390
391 struct nouveau_display_engine {
392 void *priv;
393 int (*early_init)(struct drm_device *);
394 void (*late_takedown)(struct drm_device *);
395 int (*create)(struct drm_device *);
396 int (*init)(struct drm_device *);
397 void (*destroy)(struct drm_device *);
398 };
399
400 struct nouveau_gpio_engine {
401 void *priv;
402
403 int (*init)(struct drm_device *);
404 void (*takedown)(struct drm_device *);
405
406 int (*get)(struct drm_device *, enum dcb_gpio_tag);
407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
408
409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
410 void (*)(void *, int), void *);
411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
412 void (*)(void *, int), void *);
413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
414 };
415
416 struct nouveau_pm_voltage_level {
417 u32 voltage; /* microvolts */
418 u8 vid;
419 };
420
421 struct nouveau_pm_voltage {
422 bool supported;
423 u8 version;
424 u8 vid_mask;
425
426 struct nouveau_pm_voltage_level *level;
427 int nr_level;
428 };
429
430 struct nouveau_pm_memtiming {
431 int id;
432 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */
433 u32 reg_1;
434 u32 reg_2;
435 u32 reg_3;
436 u32 reg_4;
437 u32 reg_5;
438 u32 reg_6;
439 u32 reg_7;
440 u32 reg_8;
441 /* To be written to 0x1002c0 */
442 u8 CL;
443 u8 WR;
444 };
445
446 struct nouveau_pm_tbl_header{
447 u8 version;
448 u8 header_len;
449 u8 entry_cnt;
450 u8 entry_len;
451 };
452
453 struct nouveau_pm_tbl_entry{
454 u8 tWR;
455 u8 tUNK_1;
456 u8 tCL;
457 u8 tRP; /* Byte 3 */
458 u8 empty_4;
459 u8 tRAS; /* Byte 5 */
460 u8 empty_6;
461 u8 tRFC; /* Byte 7 */
462 u8 empty_8;
463 u8 tRC; /* Byte 9 */
464 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
465 u8 empty_15,empty_16,empty_17;
466 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
467 };
468
469 /* nouveau_mem.c */
470 void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr,
471 struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
472 struct nouveau_pm_memtiming *timing);
473
474 #define NOUVEAU_PM_MAX_LEVEL 8
475 struct nouveau_pm_level {
476 struct device_attribute dev_attr;
477 char name[32];
478 int id;
479
480 u32 core;
481 u32 memory;
482 u32 shader;
483 u32 rop;
484 u32 copy;
485 u32 daemon;
486 u32 vdec;
487 u32 unk05; /* nv50:nva3, roughly.. */
488 u32 unka0; /* nva3:nvc0 */
489 u32 hub01; /* nvc0- */
490 u32 hub06; /* nvc0- */
491 u32 hub07; /* nvc0- */
492
493 u32 volt_min; /* microvolts */
494 u32 volt_max;
495 u8 fanspeed;
496
497 u16 memscript;
498 struct nouveau_pm_memtiming *timing;
499 };
500
501 struct nouveau_pm_temp_sensor_constants {
502 u16 offset_constant;
503 s16 offset_mult;
504 s16 offset_div;
505 s16 slope_mult;
506 s16 slope_div;
507 };
508
509 struct nouveau_pm_threshold_temp {
510 s16 critical;
511 s16 down_clock;
512 s16 fan_boost;
513 };
514
515 struct nouveau_pm_memtimings {
516 bool supported;
517 struct nouveau_pm_memtiming *timing;
518 int nr_timing;
519 };
520
521 struct nouveau_pm_engine {
522 struct nouveau_pm_voltage voltage;
523 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
524 int nr_perflvl;
525 struct nouveau_pm_memtimings memtimings;
526 struct nouveau_pm_temp_sensor_constants sensor_constants;
527 struct nouveau_pm_threshold_temp threshold_temp;
528
529 struct nouveau_pm_level boot;
530 struct nouveau_pm_level *cur;
531
532 struct device *hwmon;
533 struct notifier_block acpi_nb;
534
535 int (*clock_get)(struct drm_device *, u32 id);
536 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
537 u32 id, int khz);
538 void (*clock_set)(struct drm_device *, void *);
539
540 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
541 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
542 void (*clocks_set)(struct drm_device *, void *);
543
544 int (*voltage_get)(struct drm_device *);
545 int (*voltage_set)(struct drm_device *, int voltage);
546 int (*fanspeed_get)(struct drm_device *);
547 int (*fanspeed_set)(struct drm_device *, int fanspeed);
548 int (*temp_get)(struct drm_device *);
549 };
550
551 struct nouveau_vram_engine {
552 struct nouveau_mm mm;
553
554 int (*init)(struct drm_device *);
555 void (*takedown)(struct drm_device *dev);
556 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
557 u32 type, struct nouveau_mem **);
558 void (*put)(struct drm_device *, struct nouveau_mem **);
559
560 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
561 };
562
563 struct nouveau_engine {
564 struct nouveau_instmem_engine instmem;
565 struct nouveau_mc_engine mc;
566 struct nouveau_timer_engine timer;
567 struct nouveau_fb_engine fb;
568 struct nouveau_fifo_engine fifo;
569 struct nouveau_display_engine display;
570 struct nouveau_gpio_engine gpio;
571 struct nouveau_pm_engine pm;
572 struct nouveau_vram_engine vram;
573 };
574
575 struct nouveau_pll_vals {
576 union {
577 struct {
578 #ifdef __BIG_ENDIAN
579 uint8_t N1, M1, N2, M2;
580 #else
581 uint8_t M1, N1, M2, N2;
582 #endif
583 };
584 struct {
585 uint16_t NM1, NM2;
586 } __attribute__((packed));
587 };
588 int log2P;
589
590 int refclk;
591 };
592
593 enum nv04_fp_display_regs {
594 FP_DISPLAY_END,
595 FP_TOTAL,
596 FP_CRTC,
597 FP_SYNC_START,
598 FP_SYNC_END,
599 FP_VALID_START,
600 FP_VALID_END
601 };
602
603 struct nv04_crtc_reg {
604 unsigned char MiscOutReg;
605 uint8_t CRTC[0xa0];
606 uint8_t CR58[0x10];
607 uint8_t Sequencer[5];
608 uint8_t Graphics[9];
609 uint8_t Attribute[21];
610 unsigned char DAC[768];
611
612 /* PCRTC regs */
613 uint32_t fb_start;
614 uint32_t crtc_cfg;
615 uint32_t cursor_cfg;
616 uint32_t gpio_ext;
617 uint32_t crtc_830;
618 uint32_t crtc_834;
619 uint32_t crtc_850;
620 uint32_t crtc_eng_ctrl;
621
622 /* PRAMDAC regs */
623 uint32_t nv10_cursync;
624 struct nouveau_pll_vals pllvals;
625 uint32_t ramdac_gen_ctrl;
626 uint32_t ramdac_630;
627 uint32_t ramdac_634;
628 uint32_t tv_setup;
629 uint32_t tv_vtotal;
630 uint32_t tv_vskew;
631 uint32_t tv_vsync_delay;
632 uint32_t tv_htotal;
633 uint32_t tv_hskew;
634 uint32_t tv_hsync_delay;
635 uint32_t tv_hsync_delay2;
636 uint32_t fp_horiz_regs[7];
637 uint32_t fp_vert_regs[7];
638 uint32_t dither;
639 uint32_t fp_control;
640 uint32_t dither_regs[6];
641 uint32_t fp_debug_0;
642 uint32_t fp_debug_1;
643 uint32_t fp_debug_2;
644 uint32_t fp_margin_color;
645 uint32_t ramdac_8c0;
646 uint32_t ramdac_a20;
647 uint32_t ramdac_a24;
648 uint32_t ramdac_a34;
649 uint32_t ctv_regs[38];
650 };
651
652 struct nv04_output_reg {
653 uint32_t output;
654 int head;
655 };
656
657 struct nv04_mode_state {
658 struct nv04_crtc_reg crtc_reg[2];
659 uint32_t pllsel;
660 uint32_t sel_clk;
661 };
662
663 enum nouveau_card_type {
664 NV_04 = 0x00,
665 NV_10 = 0x10,
666 NV_20 = 0x20,
667 NV_30 = 0x30,
668 NV_40 = 0x40,
669 NV_50 = 0x50,
670 NV_C0 = 0xc0,
671 NV_D0 = 0xd0
672 };
673
674 struct drm_nouveau_private {
675 struct drm_device *dev;
676 bool noaccel;
677
678 /* the card type, takes NV_* as values */
679 enum nouveau_card_type card_type;
680 /* exact chipset, derived from NV_PMC_BOOT_0 */
681 int chipset;
682 int flags;
683 u32 crystal;
684
685 void __iomem *mmio;
686
687 spinlock_t ramin_lock;
688 void __iomem *ramin;
689 u32 ramin_size;
690 u32 ramin_base;
691 bool ramin_available;
692 struct drm_mm ramin_heap;
693 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
694 struct list_head gpuobj_list;
695 struct list_head classes;
696
697 struct nouveau_bo *vga_ram;
698
699 /* interrupt handling */
700 void (*irq_handler[32])(struct drm_device *);
701 bool msi_enabled;
702
703 struct list_head vbl_waiting;
704
705 struct {
706 struct drm_global_reference mem_global_ref;
707 struct ttm_bo_global_ref bo_global_ref;
708 struct ttm_bo_device bdev;
709 atomic_t validate_sequence;
710 } ttm;
711
712 struct {
713 spinlock_t lock;
714 struct drm_mm heap;
715 struct nouveau_bo *bo;
716 } fence;
717
718 struct {
719 spinlock_t lock;
720 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
721 } channels;
722
723 struct nouveau_engine engine;
724 struct nouveau_channel *channel;
725
726 /* For PFIFO and PGRAPH. */
727 spinlock_t context_switch_lock;
728
729 /* VM/PRAMIN flush, legacy PRAMIN aperture */
730 spinlock_t vm_lock;
731
732 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
733 struct nouveau_ramht *ramht;
734 struct nouveau_gpuobj *ramfc;
735 struct nouveau_gpuobj *ramro;
736
737 uint32_t ramin_rsvd_vram;
738
739 struct {
740 enum {
741 NOUVEAU_GART_NONE = 0,
742 NOUVEAU_GART_AGP, /* AGP */
743 NOUVEAU_GART_PDMA, /* paged dma object */
744 NOUVEAU_GART_HW /* on-chip gart/vm */
745 } type;
746 uint64_t aper_base;
747 uint64_t aper_size;
748 uint64_t aper_free;
749
750 struct ttm_backend_func *func;
751
752 struct {
753 struct page *page;
754 dma_addr_t addr;
755 } dummy;
756
757 struct nouveau_gpuobj *sg_ctxdma;
758 } gart_info;
759
760 /* nv10-nv40 tiling regions */
761 struct {
762 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
763 spinlock_t lock;
764 } tile;
765
766 /* VRAM/fb configuration */
767 uint64_t vram_size;
768 uint64_t vram_sys_base;
769
770 uint64_t fb_available_size;
771 uint64_t fb_mappable_pages;
772 uint64_t fb_aper_free;
773 int fb_mtrr;
774
775 /* BAR control (NV50-) */
776 struct nouveau_vm *bar1_vm;
777 struct nouveau_vm *bar3_vm;
778
779 /* G8x/G9x virtual address space */
780 struct nouveau_vm *chan_vm;
781
782 struct nvbios vbios;
783
784 struct nv04_mode_state mode_reg;
785 struct nv04_mode_state saved_reg;
786 uint32_t saved_vga_font[4][16384];
787 uint32_t crtc_owner;
788 uint32_t dac_users[4];
789
790 struct backlight_device *backlight;
791
792 struct {
793 struct dentry *channel_root;
794 } debugfs;
795
796 struct nouveau_fbdev *nfbdev;
797 struct apertures_struct *apertures;
798 };
799
800 static inline struct drm_nouveau_private *
801 nouveau_private(struct drm_device *dev)
802 {
803 return dev->dev_private;
804 }
805
806 static inline struct drm_nouveau_private *
807 nouveau_bdev(struct ttm_bo_device *bd)
808 {
809 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
810 }
811
812 static inline int
813 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
814 {
815 struct nouveau_bo *prev;
816
817 if (!pnvbo)
818 return -EINVAL;
819 prev = *pnvbo;
820
821 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
822 if (prev) {
823 struct ttm_buffer_object *bo = &prev->bo;
824
825 ttm_bo_unref(&bo);
826 }
827
828 return 0;
829 }
830
831 /* nouveau_drv.c */
832 extern int nouveau_modeset;
833 extern int nouveau_agpmode;
834 extern int nouveau_duallink;
835 extern int nouveau_uscript_lvds;
836 extern int nouveau_uscript_tmds;
837 extern int nouveau_vram_pushbuf;
838 extern int nouveau_vram_notify;
839 extern int nouveau_fbpercrtc;
840 extern int nouveau_tv_disable;
841 extern char *nouveau_tv_norm;
842 extern int nouveau_reg_debug;
843 extern char *nouveau_vbios;
844 extern int nouveau_ignorelid;
845 extern int nouveau_nofbaccel;
846 extern int nouveau_noaccel;
847 extern int nouveau_force_post;
848 extern int nouveau_override_conntype;
849 extern char *nouveau_perflvl;
850 extern int nouveau_perflvl_wr;
851 extern int nouveau_msi;
852 extern int nouveau_ctxfw;
853
854 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
855 extern int nouveau_pci_resume(struct pci_dev *pdev);
856
857 /* nouveau_state.c */
858 extern int nouveau_open(struct drm_device *, struct drm_file *);
859 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
860 extern void nouveau_postclose(struct drm_device *, struct drm_file *);
861 extern int nouveau_load(struct drm_device *, unsigned long flags);
862 extern int nouveau_firstopen(struct drm_device *);
863 extern void nouveau_lastclose(struct drm_device *);
864 extern int nouveau_unload(struct drm_device *);
865 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
866 struct drm_file *);
867 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
868 struct drm_file *);
869 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
870 uint32_t reg, uint32_t mask, uint32_t val);
871 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
872 uint32_t reg, uint32_t mask, uint32_t val);
873 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
874 bool (*cond)(void *), void *);
875 extern bool nouveau_wait_for_idle(struct drm_device *);
876 extern int nouveau_card_init(struct drm_device *);
877
878 /* nouveau_mem.c */
879 extern int nouveau_mem_vram_init(struct drm_device *);
880 extern void nouveau_mem_vram_fini(struct drm_device *);
881 extern int nouveau_mem_gart_init(struct drm_device *);
882 extern void nouveau_mem_gart_fini(struct drm_device *);
883 extern int nouveau_mem_init_agp(struct drm_device *);
884 extern int nouveau_mem_reset_agp(struct drm_device *);
885 extern void nouveau_mem_close(struct drm_device *);
886 extern int nouveau_mem_detect(struct drm_device *);
887 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
888 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
889 struct drm_device *dev, uint32_t addr, uint32_t size,
890 uint32_t pitch, uint32_t flags);
891 extern void nv10_mem_put_tile_region(struct drm_device *dev,
892 struct nouveau_tile_reg *tile,
893 struct nouveau_fence *fence);
894 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
895 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
896
897 /* nouveau_notifier.c */
898 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
899 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
900 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
901 int cout, uint32_t start, uint32_t end,
902 uint32_t *offset);
903 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
904 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
905 struct drm_file *);
906 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
907 struct drm_file *);
908
909 /* nouveau_channel.c */
910 extern struct drm_ioctl_desc nouveau_ioctls[];
911 extern int nouveau_max_ioctl;
912 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
913 extern int nouveau_channel_alloc(struct drm_device *dev,
914 struct nouveau_channel **chan,
915 struct drm_file *file_priv,
916 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
917 extern struct nouveau_channel *
918 nouveau_channel_get_unlocked(struct nouveau_channel *);
919 extern struct nouveau_channel *
920 nouveau_channel_get(struct drm_file *, int id);
921 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
922 extern void nouveau_channel_put(struct nouveau_channel **);
923 extern void nouveau_channel_ref(struct nouveau_channel *chan,
924 struct nouveau_channel **pchan);
925 extern void nouveau_channel_idle(struct nouveau_channel *chan);
926
927 /* nouveau_object.c */
928 #define NVOBJ_ENGINE_ADD(d, e, p) do { \
929 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
930 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
931 } while (0)
932
933 #define NVOBJ_ENGINE_DEL(d, e) do { \
934 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
935 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
936 } while (0)
937
938 #define NVOBJ_CLASS(d, c, e) do { \
939 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
940 if (ret) \
941 return ret; \
942 } while (0)
943
944 #define NVOBJ_MTHD(d, c, m, e) do { \
945 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
946 if (ret) \
947 return ret; \
948 } while (0)
949
950 extern int nouveau_gpuobj_early_init(struct drm_device *);
951 extern int nouveau_gpuobj_init(struct drm_device *);
952 extern void nouveau_gpuobj_takedown(struct drm_device *);
953 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
954 extern void nouveau_gpuobj_resume(struct drm_device *dev);
955 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
956 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
957 int (*exec)(struct nouveau_channel *,
958 u32 class, u32 mthd, u32 data));
959 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
960 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
961 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
962 uint32_t vram_h, uint32_t tt_h);
963 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
964 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
965 uint32_t size, int align, uint32_t flags,
966 struct nouveau_gpuobj **);
967 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
968 struct nouveau_gpuobj **);
969 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
970 u32 size, u32 flags,
971 struct nouveau_gpuobj **);
972 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
973 uint64_t offset, uint64_t size, int access,
974 int target, struct nouveau_gpuobj **);
975 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
976 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
977 u64 size, int target, int access, u32 type,
978 u32 comp, struct nouveau_gpuobj **pobj);
979 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
980 int class, u64 base, u64 size, int target,
981 int access, u32 type, u32 comp);
982 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
983 struct drm_file *);
984 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
985 struct drm_file *);
986
987 /* nouveau_irq.c */
988 extern int nouveau_irq_init(struct drm_device *);
989 extern void nouveau_irq_fini(struct drm_device *);
990 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
991 extern void nouveau_irq_register(struct drm_device *, int status_bit,
992 void (*)(struct drm_device *));
993 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
994 extern void nouveau_irq_preinstall(struct drm_device *);
995 extern int nouveau_irq_postinstall(struct drm_device *);
996 extern void nouveau_irq_uninstall(struct drm_device *);
997
998 /* nouveau_sgdma.c */
999 extern int nouveau_sgdma_init(struct drm_device *);
1000 extern void nouveau_sgdma_takedown(struct drm_device *);
1001 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1002 uint32_t offset);
1003 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
1004
1005 /* nouveau_debugfs.c */
1006 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1007 extern int nouveau_debugfs_init(struct drm_minor *);
1008 extern void nouveau_debugfs_takedown(struct drm_minor *);
1009 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1010 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1011 #else
1012 static inline int
1013 nouveau_debugfs_init(struct drm_minor *minor)
1014 {
1015 return 0;
1016 }
1017
1018 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1019 {
1020 }
1021
1022 static inline int
1023 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1024 {
1025 return 0;
1026 }
1027
1028 static inline void
1029 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1030 {
1031 }
1032 #endif
1033
1034 /* nouveau_dma.c */
1035 extern void nouveau_dma_pre_init(struct nouveau_channel *);
1036 extern int nouveau_dma_init(struct nouveau_channel *);
1037 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1038
1039 /* nouveau_acpi.c */
1040 #define ROM_BIOS_PAGE 4096
1041 #if defined(CONFIG_ACPI)
1042 void nouveau_register_dsm_handler(void);
1043 void nouveau_unregister_dsm_handler(void);
1044 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1045 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1046 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1047 #else
1048 static inline void nouveau_register_dsm_handler(void) {}
1049 static inline void nouveau_unregister_dsm_handler(void) {}
1050 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1051 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1052 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1053 #endif
1054
1055 /* nouveau_backlight.c */
1056 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1057 extern int nouveau_backlight_init(struct drm_device *);
1058 extern void nouveau_backlight_exit(struct drm_device *);
1059 #else
1060 static inline int nouveau_backlight_init(struct drm_device *dev)
1061 {
1062 return 0;
1063 }
1064
1065 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1066 #endif
1067
1068 /* nouveau_bios.c */
1069 extern int nouveau_bios_init(struct drm_device *);
1070 extern void nouveau_bios_takedown(struct drm_device *dev);
1071 extern int nouveau_run_vbios_init(struct drm_device *);
1072 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1073 struct dcb_entry *, int crtc);
1074 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1075 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1076 enum dcb_gpio_tag);
1077 extern struct dcb_connector_table_entry *
1078 nouveau_bios_connector_entry(struct drm_device *, int index);
1079 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1080 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1081 struct pll_lims *);
1082 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1083 struct dcb_entry *, int crtc);
1084 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1085 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1086 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1087 bool *dl, bool *if_is_24bit);
1088 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1089 int head, int pxclk);
1090 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1091 enum LVDS_script, int pxclk);
1092 bool bios_encoder_match(struct dcb_entry *, u32 hash);
1093
1094 /* nouveau_ttm.c */
1095 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1096 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1097 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1098
1099 /* nouveau_dp.c */
1100 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1101 uint8_t *data, int data_nr);
1102 bool nouveau_dp_detect(struct drm_encoder *);
1103 bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate);
1104 void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32);
1105 u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **);
1106
1107 /* nv04_fb.c */
1108 extern int nv04_fb_init(struct drm_device *);
1109 extern void nv04_fb_takedown(struct drm_device *);
1110
1111 /* nv10_fb.c */
1112 extern int nv10_fb_init(struct drm_device *);
1113 extern void nv10_fb_takedown(struct drm_device *);
1114 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1115 uint32_t addr, uint32_t size,
1116 uint32_t pitch, uint32_t flags);
1117 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1118 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1119
1120 /* nv30_fb.c */
1121 extern int nv30_fb_init(struct drm_device *);
1122 extern void nv30_fb_takedown(struct drm_device *);
1123 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1124 uint32_t addr, uint32_t size,
1125 uint32_t pitch, uint32_t flags);
1126 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1127
1128 /* nv40_fb.c */
1129 extern int nv40_fb_init(struct drm_device *);
1130 extern void nv40_fb_takedown(struct drm_device *);
1131 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1132
1133 /* nv50_fb.c */
1134 extern int nv50_fb_init(struct drm_device *);
1135 extern void nv50_fb_takedown(struct drm_device *);
1136 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1137
1138 /* nvc0_fb.c */
1139 extern int nvc0_fb_init(struct drm_device *);
1140 extern void nvc0_fb_takedown(struct drm_device *);
1141
1142 /* nv04_fifo.c */
1143 extern int nv04_fifo_init(struct drm_device *);
1144 extern void nv04_fifo_fini(struct drm_device *);
1145 extern void nv04_fifo_disable(struct drm_device *);
1146 extern void nv04_fifo_enable(struct drm_device *);
1147 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1148 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1149 extern int nv04_fifo_channel_id(struct drm_device *);
1150 extern int nv04_fifo_create_context(struct nouveau_channel *);
1151 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1152 extern int nv04_fifo_load_context(struct nouveau_channel *);
1153 extern int nv04_fifo_unload_context(struct drm_device *);
1154 extern void nv04_fifo_isr(struct drm_device *);
1155
1156 /* nv10_fifo.c */
1157 extern int nv10_fifo_init(struct drm_device *);
1158 extern int nv10_fifo_channel_id(struct drm_device *);
1159 extern int nv10_fifo_create_context(struct nouveau_channel *);
1160 extern int nv10_fifo_load_context(struct nouveau_channel *);
1161 extern int nv10_fifo_unload_context(struct drm_device *);
1162
1163 /* nv40_fifo.c */
1164 extern int nv40_fifo_init(struct drm_device *);
1165 extern int nv40_fifo_create_context(struct nouveau_channel *);
1166 extern int nv40_fifo_load_context(struct nouveau_channel *);
1167 extern int nv40_fifo_unload_context(struct drm_device *);
1168
1169 /* nv50_fifo.c */
1170 extern int nv50_fifo_init(struct drm_device *);
1171 extern void nv50_fifo_takedown(struct drm_device *);
1172 extern int nv50_fifo_channel_id(struct drm_device *);
1173 extern int nv50_fifo_create_context(struct nouveau_channel *);
1174 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1175 extern int nv50_fifo_load_context(struct nouveau_channel *);
1176 extern int nv50_fifo_unload_context(struct drm_device *);
1177 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1178
1179 /* nvc0_fifo.c */
1180 extern int nvc0_fifo_init(struct drm_device *);
1181 extern void nvc0_fifo_takedown(struct drm_device *);
1182 extern void nvc0_fifo_disable(struct drm_device *);
1183 extern void nvc0_fifo_enable(struct drm_device *);
1184 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1185 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1186 extern int nvc0_fifo_channel_id(struct drm_device *);
1187 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1188 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1189 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1190 extern int nvc0_fifo_unload_context(struct drm_device *);
1191
1192 /* nv04_graph.c */
1193 extern int nv04_graph_create(struct drm_device *);
1194 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1195 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1196 u32 class, u32 mthd, u32 data);
1197 extern struct nouveau_bitfield nv04_graph_nsource[];
1198
1199 /* nv10_graph.c */
1200 extern int nv10_graph_create(struct drm_device *);
1201 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1202 extern struct nouveau_bitfield nv10_graph_intr[];
1203 extern struct nouveau_bitfield nv10_graph_nstatus[];
1204
1205 /* nv20_graph.c */
1206 extern int nv20_graph_create(struct drm_device *);
1207
1208 /* nv40_graph.c */
1209 extern int nv40_graph_create(struct drm_device *);
1210 extern void nv40_grctx_init(struct nouveau_grctx *);
1211
1212 /* nv50_graph.c */
1213 extern int nv50_graph_create(struct drm_device *);
1214 extern int nv50_grctx_init(struct nouveau_grctx *);
1215 extern struct nouveau_enum nv50_data_error_names[];
1216 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1217
1218 /* nvc0_graph.c */
1219 extern int nvc0_graph_create(struct drm_device *);
1220 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1221
1222 /* nv84_crypt.c */
1223 extern int nv84_crypt_create(struct drm_device *);
1224
1225 /* nva3_copy.c */
1226 extern int nva3_copy_create(struct drm_device *dev);
1227
1228 /* nvc0_copy.c */
1229 extern int nvc0_copy_create(struct drm_device *dev, int engine);
1230
1231 /* nv31_mpeg.c */
1232 extern int nv31_mpeg_create(struct drm_device *dev);
1233
1234 /* nv50_mpeg.c */
1235 extern int nv50_mpeg_create(struct drm_device *dev);
1236
1237 /* nv04_instmem.c */
1238 extern int nv04_instmem_init(struct drm_device *);
1239 extern void nv04_instmem_takedown(struct drm_device *);
1240 extern int nv04_instmem_suspend(struct drm_device *);
1241 extern void nv04_instmem_resume(struct drm_device *);
1242 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1243 u32 size, u32 align);
1244 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1245 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1246 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1247 extern void nv04_instmem_flush(struct drm_device *);
1248
1249 /* nv50_instmem.c */
1250 extern int nv50_instmem_init(struct drm_device *);
1251 extern void nv50_instmem_takedown(struct drm_device *);
1252 extern int nv50_instmem_suspend(struct drm_device *);
1253 extern void nv50_instmem_resume(struct drm_device *);
1254 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1255 u32 size, u32 align);
1256 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1257 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1258 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1259 extern void nv50_instmem_flush(struct drm_device *);
1260 extern void nv84_instmem_flush(struct drm_device *);
1261
1262 /* nvc0_instmem.c */
1263 extern int nvc0_instmem_init(struct drm_device *);
1264 extern void nvc0_instmem_takedown(struct drm_device *);
1265 extern int nvc0_instmem_suspend(struct drm_device *);
1266 extern void nvc0_instmem_resume(struct drm_device *);
1267
1268 /* nv04_mc.c */
1269 extern int nv04_mc_init(struct drm_device *);
1270 extern void nv04_mc_takedown(struct drm_device *);
1271
1272 /* nv40_mc.c */
1273 extern int nv40_mc_init(struct drm_device *);
1274 extern void nv40_mc_takedown(struct drm_device *);
1275
1276 /* nv50_mc.c */
1277 extern int nv50_mc_init(struct drm_device *);
1278 extern void nv50_mc_takedown(struct drm_device *);
1279
1280 /* nv04_timer.c */
1281 extern int nv04_timer_init(struct drm_device *);
1282 extern uint64_t nv04_timer_read(struct drm_device *);
1283 extern void nv04_timer_takedown(struct drm_device *);
1284
1285 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1286 unsigned long arg);
1287
1288 /* nv04_dac.c */
1289 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1290 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1291 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1292 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1293 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1294
1295 /* nv04_dfp.c */
1296 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1297 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1298 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1299 int head, bool dl);
1300 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1301 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1302
1303 /* nv04_tv.c */
1304 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1305 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1306
1307 /* nv17_tv.c */
1308 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1309
1310 /* nv04_display.c */
1311 extern int nv04_display_early_init(struct drm_device *);
1312 extern void nv04_display_late_takedown(struct drm_device *);
1313 extern int nv04_display_create(struct drm_device *);
1314 extern int nv04_display_init(struct drm_device *);
1315 extern void nv04_display_destroy(struct drm_device *);
1316
1317 /* nvd0_display.c */
1318 extern int nvd0_display_create(struct drm_device *);
1319 extern int nvd0_display_init(struct drm_device *);
1320 extern void nvd0_display_destroy(struct drm_device *);
1321
1322 /* nv04_crtc.c */
1323 extern int nv04_crtc_create(struct drm_device *, int index);
1324
1325 /* nouveau_bo.c */
1326 extern struct ttm_bo_driver nouveau_bo_driver;
1327 extern int nouveau_bo_new(struct drm_device *, int size, int align,
1328 uint32_t flags, uint32_t tile_mode,
1329 uint32_t tile_flags, struct nouveau_bo **);
1330 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1331 extern int nouveau_bo_unpin(struct nouveau_bo *);
1332 extern int nouveau_bo_map(struct nouveau_bo *);
1333 extern void nouveau_bo_unmap(struct nouveau_bo *);
1334 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1335 uint32_t busy);
1336 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1337 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1338 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1339 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1340 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1341 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1342 bool no_wait_reserve, bool no_wait_gpu);
1343
1344 extern struct nouveau_vma *
1345 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1346 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1347 struct nouveau_vma *);
1348 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1349
1350 /* nouveau_fence.c */
1351 struct nouveau_fence;
1352 extern int nouveau_fence_init(struct drm_device *);
1353 extern void nouveau_fence_fini(struct drm_device *);
1354 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1355 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1356 extern void nouveau_fence_update(struct nouveau_channel *);
1357 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1358 bool emit);
1359 extern int nouveau_fence_emit(struct nouveau_fence *);
1360 extern void nouveau_fence_work(struct nouveau_fence *fence,
1361 void (*work)(void *priv, bool signalled),
1362 void *priv);
1363 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1364
1365 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1366 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1367 extern int __nouveau_fence_flush(void *obj, void *arg);
1368 extern void __nouveau_fence_unref(void **obj);
1369 extern void *__nouveau_fence_ref(void *obj);
1370
1371 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1372 {
1373 return __nouveau_fence_signalled(obj, NULL);
1374 }
1375 static inline int
1376 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1377 {
1378 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1379 }
1380 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1381 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1382 {
1383 return __nouveau_fence_flush(obj, NULL);
1384 }
1385 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1386 {
1387 __nouveau_fence_unref((void **)obj);
1388 }
1389 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1390 {
1391 return __nouveau_fence_ref(obj);
1392 }
1393
1394 /* nouveau_gem.c */
1395 extern int nouveau_gem_new(struct drm_device *, int size, int align,
1396 uint32_t domain, uint32_t tile_mode,
1397 uint32_t tile_flags, struct nouveau_bo **);
1398 extern int nouveau_gem_object_new(struct drm_gem_object *);
1399 extern void nouveau_gem_object_del(struct drm_gem_object *);
1400 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1401 extern void nouveau_gem_object_close(struct drm_gem_object *,
1402 struct drm_file *);
1403 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1404 struct drm_file *);
1405 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1406 struct drm_file *);
1407 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1408 struct drm_file *);
1409 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1410 struct drm_file *);
1411 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1412 struct drm_file *);
1413
1414 /* nouveau_display.c */
1415 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1416 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1417 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1418 struct drm_pending_vblank_event *event);
1419 int nouveau_finish_page_flip(struct nouveau_channel *,
1420 struct nouveau_page_flip_state *);
1421
1422 /* nv10_gpio.c */
1423 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1424 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1425
1426 /* nv50_gpio.c */
1427 int nv50_gpio_init(struct drm_device *dev);
1428 void nv50_gpio_fini(struct drm_device *dev);
1429 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1430 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1431 int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1432 int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1433 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1434 void (*)(void *, int), void *);
1435 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1436 void (*)(void *, int), void *);
1437 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1438
1439 /* nv50_calc. */
1440 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1441 int *N1, int *M1, int *N2, int *M2, int *P);
1442 int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1443 int clk, int *N, int *fN, int *M, int *P);
1444
1445 #ifndef ioread32_native
1446 #ifdef __BIG_ENDIAN
1447 #define ioread16_native ioread16be
1448 #define iowrite16_native iowrite16be
1449 #define ioread32_native ioread32be
1450 #define iowrite32_native iowrite32be
1451 #else /* def __BIG_ENDIAN */
1452 #define ioread16_native ioread16
1453 #define iowrite16_native iowrite16
1454 #define ioread32_native ioread32
1455 #define iowrite32_native iowrite32
1456 #endif /* def __BIG_ENDIAN else */
1457 #endif /* !ioread32_native */
1458
1459 /* channel control reg access */
1460 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1461 {
1462 return ioread32_native(chan->user + reg);
1463 }
1464
1465 static inline void nvchan_wr32(struct nouveau_channel *chan,
1466 unsigned reg, u32 val)
1467 {
1468 iowrite32_native(val, chan->user + reg);
1469 }
1470
1471 /* register access */
1472 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1473 {
1474 struct drm_nouveau_private *dev_priv = dev->dev_private;
1475 return ioread32_native(dev_priv->mmio + reg);
1476 }
1477
1478 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1479 {
1480 struct drm_nouveau_private *dev_priv = dev->dev_private;
1481 iowrite32_native(val, dev_priv->mmio + reg);
1482 }
1483
1484 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1485 {
1486 u32 tmp = nv_rd32(dev, reg);
1487 nv_wr32(dev, reg, (tmp & ~mask) | val);
1488 return tmp;
1489 }
1490
1491 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1492 {
1493 struct drm_nouveau_private *dev_priv = dev->dev_private;
1494 return ioread8(dev_priv->mmio + reg);
1495 }
1496
1497 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1498 {
1499 struct drm_nouveau_private *dev_priv = dev->dev_private;
1500 iowrite8(val, dev_priv->mmio + reg);
1501 }
1502
1503 #define nv_wait(dev, reg, mask, val) \
1504 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1505 #define nv_wait_ne(dev, reg, mask, val) \
1506 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1507 #define nv_wait_cb(dev, func, data) \
1508 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1509
1510 /* PRAMIN access */
1511 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1512 {
1513 struct drm_nouveau_private *dev_priv = dev->dev_private;
1514 return ioread32_native(dev_priv->ramin + offset);
1515 }
1516
1517 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1518 {
1519 struct drm_nouveau_private *dev_priv = dev->dev_private;
1520 iowrite32_native(val, dev_priv->ramin + offset);
1521 }
1522
1523 /* object access */
1524 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1525 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1526
1527 /*
1528 * Logging
1529 * Argument d is (struct drm_device *).
1530 */
1531 #define NV_PRINTK(level, d, fmt, arg...) \
1532 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1533 pci_name(d->pdev), ##arg)
1534 #ifndef NV_DEBUG_NOTRACE
1535 #define NV_DEBUG(d, fmt, arg...) do { \
1536 if (drm_debug & DRM_UT_DRIVER) { \
1537 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1538 __LINE__, ##arg); \
1539 } \
1540 } while (0)
1541 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1542 if (drm_debug & DRM_UT_KMS) { \
1543 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1544 __LINE__, ##arg); \
1545 } \
1546 } while (0)
1547 #else
1548 #define NV_DEBUG(d, fmt, arg...) do { \
1549 if (drm_debug & DRM_UT_DRIVER) \
1550 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1551 } while (0)
1552 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1553 if (drm_debug & DRM_UT_KMS) \
1554 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1555 } while (0)
1556 #endif
1557 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1558 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1559 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1560 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1561 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1562
1563 /* nouveau_reg_debug bitmask */
1564 enum {
1565 NOUVEAU_REG_DEBUG_MC = 0x1,
1566 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1567 NOUVEAU_REG_DEBUG_FB = 0x4,
1568 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1569 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1570 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1571 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1572 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1573 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1574 NOUVEAU_REG_DEBUG_EVO = 0x200,
1575 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1576 };
1577
1578 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1579 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1580 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1581 } while (0)
1582
1583 static inline bool
1584 nv_two_heads(struct drm_device *dev)
1585 {
1586 struct drm_nouveau_private *dev_priv = dev->dev_private;
1587 const int impl = dev->pci_device & 0x0ff0;
1588
1589 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1590 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1591 return true;
1592
1593 return false;
1594 }
1595
1596 static inline bool
1597 nv_gf4_disp_arch(struct drm_device *dev)
1598 {
1599 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1600 }
1601
1602 static inline bool
1603 nv_two_reg_pll(struct drm_device *dev)
1604 {
1605 struct drm_nouveau_private *dev_priv = dev->dev_private;
1606 const int impl = dev->pci_device & 0x0ff0;
1607
1608 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1609 return true;
1610 return false;
1611 }
1612
1613 static inline bool
1614 nv_match_device(struct drm_device *dev, unsigned device,
1615 unsigned sub_vendor, unsigned sub_device)
1616 {
1617 return dev->pdev->device == device &&
1618 dev->pdev->subsystem_vendor == sub_vendor &&
1619 dev->pdev->subsystem_device == sub_device;
1620 }
1621
1622 static inline void *
1623 nv_engine(struct drm_device *dev, int engine)
1624 {
1625 struct drm_nouveau_private *dev_priv = dev->dev_private;
1626 return (void *)dev_priv->eng[engine];
1627 }
1628
1629 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1630 * helpful to determine a number of other hardware features
1631 */
1632 static inline int
1633 nv44_graph_class(struct drm_device *dev)
1634 {
1635 struct drm_nouveau_private *dev_priv = dev->dev_private;
1636
1637 if ((dev_priv->chipset & 0xf0) == 0x60)
1638 return 1;
1639
1640 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1641 }
1642
1643 /* memory type/access flags, do not match hardware values */
1644 #define NV_MEM_ACCESS_RO 1
1645 #define NV_MEM_ACCESS_WO 2
1646 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1647 #define NV_MEM_ACCESS_SYS 4
1648 #define NV_MEM_ACCESS_VM 8
1649
1650 #define NV_MEM_TARGET_VRAM 0
1651 #define NV_MEM_TARGET_PCI 1
1652 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1653 #define NV_MEM_TARGET_VM 3
1654 #define NV_MEM_TARGET_GART 4
1655
1656 #define NV_MEM_TYPE_VM 0x7f
1657 #define NV_MEM_COMP_VM 0x03
1658
1659 /* NV_SW object class */
1660 #define NV_SW 0x0000506e
1661 #define NV_SW_DMA_SEMAPHORE 0x00000060
1662 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1663 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1664 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1665 #define NV_SW_YIELD 0x00000080
1666 #define NV_SW_DMA_VBLSEM 0x0000018c
1667 #define NV_SW_VBLSEM_OFFSET 0x00000400
1668 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1669 #define NV_SW_VBLSEM_RELEASE 0x00000408
1670 #define NV_SW_PAGE_FLIP 0x00000500
1671
1672 #endif /* __NOUVEAU_DRV_H__ */
Linux with added FPC-III support