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[S390] Remove error checking from copy_oldmem_page()
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nouveau_state.c
blob82478e0998e5c7bb1109e17a37c90005491fddbf
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
41
42 static void nouveau_stub_takedown(struct drm_device *dev) {}
43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
44
45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
46 {
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
49
50 switch (dev_priv->chipset & 0xf0) {
51 case 0x00:
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
56 engine->instmem.get = nv04_instmem_get;
57 engine->instmem.put = nv04_instmem_put;
58 engine->instmem.map = nv04_instmem_map;
59 engine->instmem.unmap = nv04_instmem_unmap;
60 engine->instmem.flush = nv04_instmem_flush;
61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
68 engine->fifo.channels = 16;
69 engine->fifo.init = nv04_fifo_init;
70 engine->fifo.takedown = nv04_fifo_fini;
71 engine->fifo.disable = nv04_fifo_disable;
72 engine->fifo.enable = nv04_fifo_enable;
73 engine->fifo.reassign = nv04_fifo_reassign;
74 engine->fifo.cache_pull = nv04_fifo_cache_pull;
75 engine->fifo.channel_id = nv04_fifo_channel_id;
76 engine->fifo.create_context = nv04_fifo_create_context;
77 engine->fifo.destroy_context = nv04_fifo_destroy_context;
78 engine->fifo.load_context = nv04_fifo_load_context;
79 engine->fifo.unload_context = nv04_fifo_unload_context;
80 engine->display.early_init = nv04_display_early_init;
81 engine->display.late_takedown = nv04_display_late_takedown;
82 engine->display.create = nv04_display_create;
83 engine->display.init = nv04_display_init;
84 engine->display.destroy = nv04_display_destroy;
85 engine->gpio.init = nouveau_stub_init;
86 engine->gpio.takedown = nouveau_stub_takedown;
87 engine->gpio.get = NULL;
88 engine->gpio.set = NULL;
89 engine->gpio.irq_enable = NULL;
90 engine->pm.clock_get = nv04_pm_clock_get;
91 engine->pm.clock_pre = nv04_pm_clock_pre;
92 engine->pm.clock_set = nv04_pm_clock_set;
93 engine->vram.init = nouveau_mem_detect;
94 engine->vram.takedown = nouveau_stub_takedown;
95 engine->vram.flags_valid = nouveau_mem_flags_valid;
96 break;
97 case 0x10:
98 engine->instmem.init = nv04_instmem_init;
99 engine->instmem.takedown = nv04_instmem_takedown;
100 engine->instmem.suspend = nv04_instmem_suspend;
101 engine->instmem.resume = nv04_instmem_resume;
102 engine->instmem.get = nv04_instmem_get;
103 engine->instmem.put = nv04_instmem_put;
104 engine->instmem.map = nv04_instmem_map;
105 engine->instmem.unmap = nv04_instmem_unmap;
106 engine->instmem.flush = nv04_instmem_flush;
107 engine->mc.init = nv04_mc_init;
108 engine->mc.takedown = nv04_mc_takedown;
109 engine->timer.init = nv04_timer_init;
110 engine->timer.read = nv04_timer_read;
111 engine->timer.takedown = nv04_timer_takedown;
112 engine->fb.init = nv10_fb_init;
113 engine->fb.takedown = nv10_fb_takedown;
114 engine->fb.init_tile_region = nv10_fb_init_tile_region;
115 engine->fb.set_tile_region = nv10_fb_set_tile_region;
116 engine->fb.free_tile_region = nv10_fb_free_tile_region;
117 engine->fifo.channels = 32;
118 engine->fifo.init = nv10_fifo_init;
119 engine->fifo.takedown = nv04_fifo_fini;
120 engine->fifo.disable = nv04_fifo_disable;
121 engine->fifo.enable = nv04_fifo_enable;
122 engine->fifo.reassign = nv04_fifo_reassign;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
124 engine->fifo.channel_id = nv10_fifo_channel_id;
125 engine->fifo.create_context = nv10_fifo_create_context;
126 engine->fifo.destroy_context = nv04_fifo_destroy_context;
127 engine->fifo.load_context = nv10_fifo_load_context;
128 engine->fifo.unload_context = nv10_fifo_unload_context;
129 engine->display.early_init = nv04_display_early_init;
130 engine->display.late_takedown = nv04_display_late_takedown;
131 engine->display.create = nv04_display_create;
132 engine->display.init = nv04_display_init;
133 engine->display.destroy = nv04_display_destroy;
134 engine->gpio.init = nouveau_stub_init;
135 engine->gpio.takedown = nouveau_stub_takedown;
136 engine->gpio.get = nv10_gpio_get;
137 engine->gpio.set = nv10_gpio_set;
138 engine->gpio.irq_enable = NULL;
139 engine->pm.clock_get = nv04_pm_clock_get;
140 engine->pm.clock_pre = nv04_pm_clock_pre;
141 engine->pm.clock_set = nv04_pm_clock_set;
142 engine->vram.init = nouveau_mem_detect;
143 engine->vram.takedown = nouveau_stub_takedown;
144 engine->vram.flags_valid = nouveau_mem_flags_valid;
145 break;
146 case 0x20:
147 engine->instmem.init = nv04_instmem_init;
148 engine->instmem.takedown = nv04_instmem_takedown;
149 engine->instmem.suspend = nv04_instmem_suspend;
150 engine->instmem.resume = nv04_instmem_resume;
151 engine->instmem.get = nv04_instmem_get;
152 engine->instmem.put = nv04_instmem_put;
153 engine->instmem.map = nv04_instmem_map;
154 engine->instmem.unmap = nv04_instmem_unmap;
155 engine->instmem.flush = nv04_instmem_flush;
156 engine->mc.init = nv04_mc_init;
157 engine->mc.takedown = nv04_mc_takedown;
158 engine->timer.init = nv04_timer_init;
159 engine->timer.read = nv04_timer_read;
160 engine->timer.takedown = nv04_timer_takedown;
161 engine->fb.init = nv10_fb_init;
162 engine->fb.takedown = nv10_fb_takedown;
163 engine->fb.init_tile_region = nv10_fb_init_tile_region;
164 engine->fb.set_tile_region = nv10_fb_set_tile_region;
165 engine->fb.free_tile_region = nv10_fb_free_tile_region;
166 engine->fifo.channels = 32;
167 engine->fifo.init = nv10_fifo_init;
168 engine->fifo.takedown = nv04_fifo_fini;
169 engine->fifo.disable = nv04_fifo_disable;
170 engine->fifo.enable = nv04_fifo_enable;
171 engine->fifo.reassign = nv04_fifo_reassign;
172 engine->fifo.cache_pull = nv04_fifo_cache_pull;
173 engine->fifo.channel_id = nv10_fifo_channel_id;
174 engine->fifo.create_context = nv10_fifo_create_context;
175 engine->fifo.destroy_context = nv04_fifo_destroy_context;
176 engine->fifo.load_context = nv10_fifo_load_context;
177 engine->fifo.unload_context = nv10_fifo_unload_context;
178 engine->display.early_init = nv04_display_early_init;
179 engine->display.late_takedown = nv04_display_late_takedown;
180 engine->display.create = nv04_display_create;
181 engine->display.init = nv04_display_init;
182 engine->display.destroy = nv04_display_destroy;
183 engine->gpio.init = nouveau_stub_init;
184 engine->gpio.takedown = nouveau_stub_takedown;
185 engine->gpio.get = nv10_gpio_get;
186 engine->gpio.set = nv10_gpio_set;
187 engine->gpio.irq_enable = NULL;
188 engine->pm.clock_get = nv04_pm_clock_get;
189 engine->pm.clock_pre = nv04_pm_clock_pre;
190 engine->pm.clock_set = nv04_pm_clock_set;
191 engine->vram.init = nouveau_mem_detect;
192 engine->vram.takedown = nouveau_stub_takedown;
193 engine->vram.flags_valid = nouveau_mem_flags_valid;
194 break;
195 case 0x30:
196 engine->instmem.init = nv04_instmem_init;
197 engine->instmem.takedown = nv04_instmem_takedown;
198 engine->instmem.suspend = nv04_instmem_suspend;
199 engine->instmem.resume = nv04_instmem_resume;
200 engine->instmem.get = nv04_instmem_get;
201 engine->instmem.put = nv04_instmem_put;
202 engine->instmem.map = nv04_instmem_map;
203 engine->instmem.unmap = nv04_instmem_unmap;
204 engine->instmem.flush = nv04_instmem_flush;
205 engine->mc.init = nv04_mc_init;
206 engine->mc.takedown = nv04_mc_takedown;
207 engine->timer.init = nv04_timer_init;
208 engine->timer.read = nv04_timer_read;
209 engine->timer.takedown = nv04_timer_takedown;
210 engine->fb.init = nv30_fb_init;
211 engine->fb.takedown = nv30_fb_takedown;
212 engine->fb.init_tile_region = nv30_fb_init_tile_region;
213 engine->fb.set_tile_region = nv10_fb_set_tile_region;
214 engine->fb.free_tile_region = nv30_fb_free_tile_region;
215 engine->fifo.channels = 32;
216 engine->fifo.init = nv10_fifo_init;
217 engine->fifo.takedown = nv04_fifo_fini;
218 engine->fifo.disable = nv04_fifo_disable;
219 engine->fifo.enable = nv04_fifo_enable;
220 engine->fifo.reassign = nv04_fifo_reassign;
221 engine->fifo.cache_pull = nv04_fifo_cache_pull;
222 engine->fifo.channel_id = nv10_fifo_channel_id;
223 engine->fifo.create_context = nv10_fifo_create_context;
224 engine->fifo.destroy_context = nv04_fifo_destroy_context;
225 engine->fifo.load_context = nv10_fifo_load_context;
226 engine->fifo.unload_context = nv10_fifo_unload_context;
227 engine->display.early_init = nv04_display_early_init;
228 engine->display.late_takedown = nv04_display_late_takedown;
229 engine->display.create = nv04_display_create;
230 engine->display.init = nv04_display_init;
231 engine->display.destroy = nv04_display_destroy;
232 engine->gpio.init = nouveau_stub_init;
233 engine->gpio.takedown = nouveau_stub_takedown;
234 engine->gpio.get = nv10_gpio_get;
235 engine->gpio.set = nv10_gpio_set;
236 engine->gpio.irq_enable = NULL;
237 engine->pm.clock_get = nv04_pm_clock_get;
238 engine->pm.clock_pre = nv04_pm_clock_pre;
239 engine->pm.clock_set = nv04_pm_clock_set;
240 engine->pm.voltage_get = nouveau_voltage_gpio_get;
241 engine->pm.voltage_set = nouveau_voltage_gpio_set;
242 engine->vram.init = nouveau_mem_detect;
243 engine->vram.takedown = nouveau_stub_takedown;
244 engine->vram.flags_valid = nouveau_mem_flags_valid;
245 break;
246 case 0x40:
247 case 0x60:
248 engine->instmem.init = nv04_instmem_init;
249 engine->instmem.takedown = nv04_instmem_takedown;
250 engine->instmem.suspend = nv04_instmem_suspend;
251 engine->instmem.resume = nv04_instmem_resume;
252 engine->instmem.get = nv04_instmem_get;
253 engine->instmem.put = nv04_instmem_put;
254 engine->instmem.map = nv04_instmem_map;
255 engine->instmem.unmap = nv04_instmem_unmap;
256 engine->instmem.flush = nv04_instmem_flush;
257 engine->mc.init = nv40_mc_init;
258 engine->mc.takedown = nv40_mc_takedown;
259 engine->timer.init = nv04_timer_init;
260 engine->timer.read = nv04_timer_read;
261 engine->timer.takedown = nv04_timer_takedown;
262 engine->fb.init = nv40_fb_init;
263 engine->fb.takedown = nv40_fb_takedown;
264 engine->fb.init_tile_region = nv30_fb_init_tile_region;
265 engine->fb.set_tile_region = nv40_fb_set_tile_region;
266 engine->fb.free_tile_region = nv30_fb_free_tile_region;
267 engine->fifo.channels = 32;
268 engine->fifo.init = nv40_fifo_init;
269 engine->fifo.takedown = nv04_fifo_fini;
270 engine->fifo.disable = nv04_fifo_disable;
271 engine->fifo.enable = nv04_fifo_enable;
272 engine->fifo.reassign = nv04_fifo_reassign;
273 engine->fifo.cache_pull = nv04_fifo_cache_pull;
274 engine->fifo.channel_id = nv10_fifo_channel_id;
275 engine->fifo.create_context = nv40_fifo_create_context;
276 engine->fifo.destroy_context = nv04_fifo_destroy_context;
277 engine->fifo.load_context = nv40_fifo_load_context;
278 engine->fifo.unload_context = nv40_fifo_unload_context;
279 engine->display.early_init = nv04_display_early_init;
280 engine->display.late_takedown = nv04_display_late_takedown;
281 engine->display.create = nv04_display_create;
282 engine->display.init = nv04_display_init;
283 engine->display.destroy = nv04_display_destroy;
284 engine->gpio.init = nouveau_stub_init;
285 engine->gpio.takedown = nouveau_stub_takedown;
286 engine->gpio.get = nv10_gpio_get;
287 engine->gpio.set = nv10_gpio_set;
288 engine->gpio.irq_enable = NULL;
289 engine->pm.clocks_get = nv40_pm_clocks_get;
290 engine->pm.clocks_pre = nv40_pm_clocks_pre;
291 engine->pm.clocks_set = nv40_pm_clocks_set;
292 engine->pm.voltage_get = nouveau_voltage_gpio_get;
293 engine->pm.voltage_set = nouveau_voltage_gpio_set;
294 engine->pm.temp_get = nv40_temp_get;
295 engine->vram.init = nouveau_mem_detect;
296 engine->vram.takedown = nouveau_stub_takedown;
297 engine->vram.flags_valid = nouveau_mem_flags_valid;
298 break;
299 case 0x50:
300 case 0x80: /* gotta love NVIDIA's consistency.. */
301 case 0x90:
302 case 0xa0:
303 engine->instmem.init = nv50_instmem_init;
304 engine->instmem.takedown = nv50_instmem_takedown;
305 engine->instmem.suspend = nv50_instmem_suspend;
306 engine->instmem.resume = nv50_instmem_resume;
307 engine->instmem.get = nv50_instmem_get;
308 engine->instmem.put = nv50_instmem_put;
309 engine->instmem.map = nv50_instmem_map;
310 engine->instmem.unmap = nv50_instmem_unmap;
311 if (dev_priv->chipset == 0x50)
312 engine->instmem.flush = nv50_instmem_flush;
313 else
314 engine->instmem.flush = nv84_instmem_flush;
315 engine->mc.init = nv50_mc_init;
316 engine->mc.takedown = nv50_mc_takedown;
317 engine->timer.init = nv04_timer_init;
318 engine->timer.read = nv04_timer_read;
319 engine->timer.takedown = nv04_timer_takedown;
320 engine->fb.init = nv50_fb_init;
321 engine->fb.takedown = nv50_fb_takedown;
322 engine->fifo.channels = 128;
323 engine->fifo.init = nv50_fifo_init;
324 engine->fifo.takedown = nv50_fifo_takedown;
325 engine->fifo.disable = nv04_fifo_disable;
326 engine->fifo.enable = nv04_fifo_enable;
327 engine->fifo.reassign = nv04_fifo_reassign;
328 engine->fifo.channel_id = nv50_fifo_channel_id;
329 engine->fifo.create_context = nv50_fifo_create_context;
330 engine->fifo.destroy_context = nv50_fifo_destroy_context;
331 engine->fifo.load_context = nv50_fifo_load_context;
332 engine->fifo.unload_context = nv50_fifo_unload_context;
333 engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
334 engine->display.early_init = nv50_display_early_init;
335 engine->display.late_takedown = nv50_display_late_takedown;
336 engine->display.create = nv50_display_create;
337 engine->display.init = nv50_display_init;
338 engine->display.destroy = nv50_display_destroy;
339 engine->gpio.init = nv50_gpio_init;
340 engine->gpio.takedown = nv50_gpio_fini;
341 engine->gpio.get = nv50_gpio_get;
342 engine->gpio.set = nv50_gpio_set;
343 engine->gpio.irq_register = nv50_gpio_irq_register;
344 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
345 engine->gpio.irq_enable = nv50_gpio_irq_enable;
346 switch (dev_priv->chipset) {
347 case 0x84:
348 case 0x86:
349 case 0x92:
350 case 0x94:
351 case 0x96:
352 case 0x98:
353 case 0xa0:
354 case 0xaa:
355 case 0xac:
356 case 0x50:
357 engine->pm.clock_get = nv50_pm_clock_get;
358 engine->pm.clock_pre = nv50_pm_clock_pre;
359 engine->pm.clock_set = nv50_pm_clock_set;
360 break;
361 default:
362 engine->pm.clocks_get = nva3_pm_clocks_get;
363 engine->pm.clocks_pre = nva3_pm_clocks_pre;
364 engine->pm.clocks_set = nva3_pm_clocks_set;
365 break;
366 }
367 engine->pm.voltage_get = nouveau_voltage_gpio_get;
368 engine->pm.voltage_set = nouveau_voltage_gpio_set;
369 if (dev_priv->chipset >= 0x84)
370 engine->pm.temp_get = nv84_temp_get;
371 else
372 engine->pm.temp_get = nv40_temp_get;
373 engine->vram.init = nv50_vram_init;
374 engine->vram.takedown = nv50_vram_fini;
375 engine->vram.get = nv50_vram_new;
376 engine->vram.put = nv50_vram_del;
377 engine->vram.flags_valid = nv50_vram_flags_valid;
378 break;
379 case 0xc0:
380 engine->instmem.init = nvc0_instmem_init;
381 engine->instmem.takedown = nvc0_instmem_takedown;
382 engine->instmem.suspend = nvc0_instmem_suspend;
383 engine->instmem.resume = nvc0_instmem_resume;
384 engine->instmem.get = nv50_instmem_get;
385 engine->instmem.put = nv50_instmem_put;
386 engine->instmem.map = nv50_instmem_map;
387 engine->instmem.unmap = nv50_instmem_unmap;
388 engine->instmem.flush = nv84_instmem_flush;
389 engine->mc.init = nv50_mc_init;
390 engine->mc.takedown = nv50_mc_takedown;
391 engine->timer.init = nv04_timer_init;
392 engine->timer.read = nv04_timer_read;
393 engine->timer.takedown = nv04_timer_takedown;
394 engine->fb.init = nvc0_fb_init;
395 engine->fb.takedown = nvc0_fb_takedown;
396 engine->fifo.channels = 128;
397 engine->fifo.init = nvc0_fifo_init;
398 engine->fifo.takedown = nvc0_fifo_takedown;
399 engine->fifo.disable = nvc0_fifo_disable;
400 engine->fifo.enable = nvc0_fifo_enable;
401 engine->fifo.reassign = nvc0_fifo_reassign;
402 engine->fifo.channel_id = nvc0_fifo_channel_id;
403 engine->fifo.create_context = nvc0_fifo_create_context;
404 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
405 engine->fifo.load_context = nvc0_fifo_load_context;
406 engine->fifo.unload_context = nvc0_fifo_unload_context;
407 engine->display.early_init = nv50_display_early_init;
408 engine->display.late_takedown = nv50_display_late_takedown;
409 engine->display.create = nv50_display_create;
410 engine->display.init = nv50_display_init;
411 engine->display.destroy = nv50_display_destroy;
412 engine->gpio.init = nv50_gpio_init;
413 engine->gpio.takedown = nouveau_stub_takedown;
414 engine->gpio.get = nv50_gpio_get;
415 engine->gpio.set = nv50_gpio_set;
416 engine->gpio.irq_register = nv50_gpio_irq_register;
417 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
418 engine->gpio.irq_enable = nv50_gpio_irq_enable;
419 engine->vram.init = nvc0_vram_init;
420 engine->vram.takedown = nv50_vram_fini;
421 engine->vram.get = nvc0_vram_new;
422 engine->vram.put = nv50_vram_del;
423 engine->vram.flags_valid = nvc0_vram_flags_valid;
424 engine->pm.temp_get = nv84_temp_get;
425 engine->pm.clocks_get = nvc0_pm_clocks_get;
426 engine->pm.voltage_get = nouveau_voltage_gpio_get;
427 engine->pm.voltage_set = nouveau_voltage_gpio_set;
428 break;
429 case 0xd0:
430 engine->instmem.init = nvc0_instmem_init;
431 engine->instmem.takedown = nvc0_instmem_takedown;
432 engine->instmem.suspend = nvc0_instmem_suspend;
433 engine->instmem.resume = nvc0_instmem_resume;
434 engine->instmem.get = nv50_instmem_get;
435 engine->instmem.put = nv50_instmem_put;
436 engine->instmem.map = nv50_instmem_map;
437 engine->instmem.unmap = nv50_instmem_unmap;
438 engine->instmem.flush = nv84_instmem_flush;
439 engine->mc.init = nv50_mc_init;
440 engine->mc.takedown = nv50_mc_takedown;
441 engine->timer.init = nv04_timer_init;
442 engine->timer.read = nv04_timer_read;
443 engine->timer.takedown = nv04_timer_takedown;
444 engine->fb.init = nvc0_fb_init;
445 engine->fb.takedown = nvc0_fb_takedown;
446 engine->fifo.channels = 128;
447 engine->fifo.init = nvc0_fifo_init;
448 engine->fifo.takedown = nvc0_fifo_takedown;
449 engine->fifo.disable = nvc0_fifo_disable;
450 engine->fifo.enable = nvc0_fifo_enable;
451 engine->fifo.reassign = nvc0_fifo_reassign;
452 engine->fifo.channel_id = nvc0_fifo_channel_id;
453 engine->fifo.create_context = nvc0_fifo_create_context;
454 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
455 engine->fifo.load_context = nvc0_fifo_load_context;
456 engine->fifo.unload_context = nvc0_fifo_unload_context;
457 engine->display.early_init = nouveau_stub_init;
458 engine->display.late_takedown = nouveau_stub_takedown;
459 engine->display.create = nvd0_display_create;
460 engine->display.init = nvd0_display_init;
461 engine->display.destroy = nvd0_display_destroy;
462 engine->gpio.init = nv50_gpio_init;
463 engine->gpio.takedown = nouveau_stub_takedown;
464 engine->gpio.get = nvd0_gpio_get;
465 engine->gpio.set = nvd0_gpio_set;
466 engine->gpio.irq_register = nv50_gpio_irq_register;
467 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
468 engine->gpio.irq_enable = nv50_gpio_irq_enable;
469 engine->vram.init = nvc0_vram_init;
470 engine->vram.takedown = nv50_vram_fini;
471 engine->vram.get = nvc0_vram_new;
472 engine->vram.put = nv50_vram_del;
473 engine->vram.flags_valid = nvc0_vram_flags_valid;
474 engine->pm.clocks_get = nvc0_pm_clocks_get;
475 engine->pm.voltage_get = nouveau_voltage_gpio_get;
476 engine->pm.voltage_set = nouveau_voltage_gpio_set;
477 break;
478 default:
479 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
480 return 1;
481 }
482
483 /* headless mode */
484 if (nouveau_modeset == 2) {
485 engine->display.early_init = nouveau_stub_init;
486 engine->display.late_takedown = nouveau_stub_takedown;
487 engine->display.create = nouveau_stub_init;
488 engine->display.init = nouveau_stub_init;
489 engine->display.destroy = nouveau_stub_takedown;
490 }
491
492 return 0;
493 }
494
495 static unsigned int
496 nouveau_vga_set_decode(void *priv, bool state)
497 {
498 struct drm_device *dev = priv;
499 struct drm_nouveau_private *dev_priv = dev->dev_private;
500
501 if (dev_priv->chipset >= 0x40)
502 nv_wr32(dev, 0x88054, state);
503 else
504 nv_wr32(dev, 0x1854, state);
505
506 if (state)
507 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
508 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
509 else
510 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
511 }
512
513 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
514 enum vga_switcheroo_state state)
515 {
516 struct drm_device *dev = pci_get_drvdata(pdev);
517 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
518 if (state == VGA_SWITCHEROO_ON) {
519 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
520 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
521 nouveau_pci_resume(pdev);
522 drm_kms_helper_poll_enable(dev);
523 dev->switch_power_state = DRM_SWITCH_POWER_ON;
524 } else {
525 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
526 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
527 drm_kms_helper_poll_disable(dev);
528 nouveau_pci_suspend(pdev, pmm);
529 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
530 }
531 }
532
533 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
534 {
535 struct drm_device *dev = pci_get_drvdata(pdev);
536 nouveau_fbcon_output_poll_changed(dev);
537 }
538
539 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
540 {
541 struct drm_device *dev = pci_get_drvdata(pdev);
542 bool can_switch;
543
544 spin_lock(&dev->count_lock);
545 can_switch = (dev->open_count == 0);
546 spin_unlock(&dev->count_lock);
547 return can_switch;
548 }
549
550 int
551 nouveau_card_init(struct drm_device *dev)
552 {
553 struct drm_nouveau_private *dev_priv = dev->dev_private;
554 struct nouveau_engine *engine;
555 int ret, e = 0;
556
557 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
558 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
559 nouveau_switcheroo_reprobe,
560 nouveau_switcheroo_can_switch);
561
562 /* Initialise internal driver API hooks */
563 ret = nouveau_init_engine_ptrs(dev);
564 if (ret)
565 goto out;
566 engine = &dev_priv->engine;
567 spin_lock_init(&dev_priv->channels.lock);
568 spin_lock_init(&dev_priv->tile.lock);
569 spin_lock_init(&dev_priv->context_switch_lock);
570 spin_lock_init(&dev_priv->vm_lock);
571
572 /* Make the CRTCs and I2C buses accessible */
573 ret = engine->display.early_init(dev);
574 if (ret)
575 goto out;
576
577 /* Parse BIOS tables / Run init tables if card not POSTed */
578 ret = nouveau_bios_init(dev);
579 if (ret)
580 goto out_display_early;
581
582 nouveau_pm_init(dev);
583
584 ret = engine->vram.init(dev);
585 if (ret)
586 goto out_bios;
587
588 ret = nouveau_gpuobj_init(dev);
589 if (ret)
590 goto out_vram;
591
592 ret = engine->instmem.init(dev);
593 if (ret)
594 goto out_gpuobj;
595
596 ret = nouveau_mem_vram_init(dev);
597 if (ret)
598 goto out_instmem;
599
600 ret = nouveau_mem_gart_init(dev);
601 if (ret)
602 goto out_ttmvram;
603
604 /* PMC */
605 ret = engine->mc.init(dev);
606 if (ret)
607 goto out_gart;
608
609 /* PGPIO */
610 ret = engine->gpio.init(dev);
611 if (ret)
612 goto out_mc;
613
614 /* PTIMER */
615 ret = engine->timer.init(dev);
616 if (ret)
617 goto out_gpio;
618
619 /* PFB */
620 ret = engine->fb.init(dev);
621 if (ret)
622 goto out_timer;
623
624 if (!dev_priv->noaccel) {
625 switch (dev_priv->card_type) {
626 case NV_04:
627 nv04_graph_create(dev);
628 break;
629 case NV_10:
630 nv10_graph_create(dev);
631 break;
632 case NV_20:
633 case NV_30:
634 nv20_graph_create(dev);
635 break;
636 case NV_40:
637 nv40_graph_create(dev);
638 break;
639 case NV_50:
640 nv50_graph_create(dev);
641 break;
642 case NV_C0:
643 nvc0_graph_create(dev);
644 break;
645 default:
646 break;
647 }
648
649 switch (dev_priv->chipset) {
650 case 0x84:
651 case 0x86:
652 case 0x92:
653 case 0x94:
654 case 0x96:
655 case 0xa0:
656 nv84_crypt_create(dev);
657 break;
658 }
659
660 switch (dev_priv->card_type) {
661 case NV_50:
662 switch (dev_priv->chipset) {
663 case 0xa3:
664 case 0xa5:
665 case 0xa8:
666 case 0xaf:
667 nva3_copy_create(dev);
668 break;
669 }
670 break;
671 case NV_C0:
672 nvc0_copy_create(dev, 0);
673 nvc0_copy_create(dev, 1);
674 break;
675 default:
676 break;
677 }
678
679 if (dev_priv->card_type == NV_40 ||
680 dev_priv->chipset == 0x31 ||
681 dev_priv->chipset == 0x34 ||
682 dev_priv->chipset == 0x36)
683 nv31_mpeg_create(dev);
684 else
685 if (dev_priv->card_type == NV_50 &&
686 (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
687 nv50_mpeg_create(dev);
688
689 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
690 if (dev_priv->eng[e]) {
691 ret = dev_priv->eng[e]->init(dev, e);
692 if (ret)
693 goto out_engine;
694 }
695 }
696
697 /* PFIFO */
698 ret = engine->fifo.init(dev);
699 if (ret)
700 goto out_engine;
701 }
702
703 ret = nouveau_irq_init(dev);
704 if (ret)
705 goto out_fifo;
706
707 /* initialise general modesetting */
708 drm_mode_config_init(dev);
709 drm_mode_create_scaling_mode_property(dev);
710 drm_mode_create_dithering_property(dev);
711 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
712 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 1);
713 dev->mode_config.min_width = 0;
714 dev->mode_config.min_height = 0;
715 if (dev_priv->card_type < NV_10) {
716 dev->mode_config.max_width = 2048;
717 dev->mode_config.max_height = 2048;
718 } else
719 if (dev_priv->card_type < NV_50) {
720 dev->mode_config.max_width = 4096;
721 dev->mode_config.max_height = 4096;
722 } else {
723 dev->mode_config.max_width = 8192;
724 dev->mode_config.max_height = 8192;
725 }
726
727 ret = engine->display.create(dev);
728 if (ret)
729 goto out_irq;
730
731 nouveau_backlight_init(dev);
732
733 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
734 ret = nouveau_fence_init(dev);
735 if (ret)
736 goto out_disp;
737
738 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
739 NvDmaFB, NvDmaTT);
740 if (ret)
741 goto out_fence;
742
743 mutex_unlock(&dev_priv->channel->mutex);
744 }
745
746 if (dev->mode_config.num_crtc) {
747 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
748 if (ret)
749 goto out_chan;
750
751 nouveau_fbcon_init(dev);
752 drm_kms_helper_poll_init(dev);
753 }
754
755 return 0;
756
757 out_chan:
758 nouveau_channel_put_unlocked(&dev_priv->channel);
759 out_fence:
760 nouveau_fence_fini(dev);
761 out_disp:
762 nouveau_backlight_exit(dev);
763 engine->display.destroy(dev);
764 out_irq:
765 nouveau_irq_fini(dev);
766 out_fifo:
767 if (!dev_priv->noaccel)
768 engine->fifo.takedown(dev);
769 out_engine:
770 if (!dev_priv->noaccel) {
771 for (e = e - 1; e >= 0; e--) {
772 if (!dev_priv->eng[e])
773 continue;
774 dev_priv->eng[e]->fini(dev, e, false);
775 dev_priv->eng[e]->destroy(dev,e );
776 }
777 }
778
779 engine->fb.takedown(dev);
780 out_timer:
781 engine->timer.takedown(dev);
782 out_gpio:
783 engine->gpio.takedown(dev);
784 out_mc:
785 engine->mc.takedown(dev);
786 out_gart:
787 nouveau_mem_gart_fini(dev);
788 out_ttmvram:
789 nouveau_mem_vram_fini(dev);
790 out_instmem:
791 engine->instmem.takedown(dev);
792 out_gpuobj:
793 nouveau_gpuobj_takedown(dev);
794 out_vram:
795 engine->vram.takedown(dev);
796 out_bios:
797 nouveau_pm_fini(dev);
798 nouveau_bios_takedown(dev);
799 out_display_early:
800 engine->display.late_takedown(dev);
801 out:
802 vga_client_register(dev->pdev, NULL, NULL, NULL);
803 return ret;
804 }
805
806 static void nouveau_card_takedown(struct drm_device *dev)
807 {
808 struct drm_nouveau_private *dev_priv = dev->dev_private;
809 struct nouveau_engine *engine = &dev_priv->engine;
810 int e;
811
812 if (dev->mode_config.num_crtc) {
813 drm_kms_helper_poll_fini(dev);
814 nouveau_fbcon_fini(dev);
815 drm_vblank_cleanup(dev);
816 }
817
818 if (dev_priv->channel) {
819 nouveau_channel_put_unlocked(&dev_priv->channel);
820 nouveau_fence_fini(dev);
821 }
822
823 nouveau_backlight_exit(dev);
824 engine->display.destroy(dev);
825 drm_mode_config_cleanup(dev);
826
827 if (!dev_priv->noaccel) {
828 engine->fifo.takedown(dev);
829 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
830 if (dev_priv->eng[e]) {
831 dev_priv->eng[e]->fini(dev, e, false);
832 dev_priv->eng[e]->destroy(dev,e );
833 }
834 }
835 }
836 engine->fb.takedown(dev);
837 engine->timer.takedown(dev);
838 engine->gpio.takedown(dev);
839 engine->mc.takedown(dev);
840 engine->display.late_takedown(dev);
841
842 if (dev_priv->vga_ram) {
843 nouveau_bo_unpin(dev_priv->vga_ram);
844 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
845 }
846
847 mutex_lock(&dev->struct_mutex);
848 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
849 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
850 mutex_unlock(&dev->struct_mutex);
851 nouveau_mem_gart_fini(dev);
852 nouveau_mem_vram_fini(dev);
853
854 engine->instmem.takedown(dev);
855 nouveau_gpuobj_takedown(dev);
856 engine->vram.takedown(dev);
857
858 nouveau_irq_fini(dev);
859
860 nouveau_pm_fini(dev);
861 nouveau_bios_takedown(dev);
862
863 vga_client_register(dev->pdev, NULL, NULL, NULL);
864 }
865
866 int
867 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
868 {
869 struct drm_nouveau_private *dev_priv = dev->dev_private;
870 struct nouveau_fpriv *fpriv;
871 int ret;
872
873 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
874 if (unlikely(!fpriv))
875 return -ENOMEM;
876
877 spin_lock_init(&fpriv->lock);
878 INIT_LIST_HEAD(&fpriv->channels);
879
880 if (dev_priv->card_type == NV_50) {
881 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
882 &fpriv->vm);
883 if (ret) {
884 kfree(fpriv);
885 return ret;
886 }
887 } else
888 if (dev_priv->card_type >= NV_C0) {
889 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
890 &fpriv->vm);
891 if (ret) {
892 kfree(fpriv);
893 return ret;
894 }
895 }
896
897 file_priv->driver_priv = fpriv;
898 return 0;
899 }
900
901 /* here a client dies, release the stuff that was allocated for its
902 * file_priv */
903 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
904 {
905 nouveau_channel_cleanup(dev, file_priv);
906 }
907
908 void
909 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
910 {
911 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
912 nouveau_vm_ref(NULL, &fpriv->vm, NULL);
913 kfree(fpriv);
914 }
915
916 /* first module load, setup the mmio/fb mapping */
917 /* KMS: we need mmio at load time, not when the first drm client opens. */
918 int nouveau_firstopen(struct drm_device *dev)
919 {
920 return 0;
921 }
922
923 /* if we have an OF card, copy vbios to RAMIN */
924 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
925 {
926 #if defined(__powerpc__)
927 int size, i;
928 const uint32_t *bios;
929 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
930 if (!dn) {
931 NV_INFO(dev, "Unable to get the OF node\n");
932 return;
933 }
934
935 bios = of_get_property(dn, "NVDA,BMP", &size);
936 if (bios) {
937 for (i = 0; i < size; i += 4)
938 nv_wi32(dev, i, bios[i/4]);
939 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
940 } else {
941 NV_INFO(dev, "Unable to get the OF bios\n");
942 }
943 #endif
944 }
945
946 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
947 {
948 struct pci_dev *pdev = dev->pdev;
949 struct apertures_struct *aper = alloc_apertures(3);
950 if (!aper)
951 return NULL;
952
953 aper->ranges[0].base = pci_resource_start(pdev, 1);
954 aper->ranges[0].size = pci_resource_len(pdev, 1);
955 aper->count = 1;
956
957 if (pci_resource_len(pdev, 2)) {
958 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
959 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
960 aper->count++;
961 }
962
963 if (pci_resource_len(pdev, 3)) {
964 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
965 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
966 aper->count++;
967 }
968
969 return aper;
970 }
971
972 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
973 {
974 struct drm_nouveau_private *dev_priv = dev->dev_private;
975 bool primary = false;
976 dev_priv->apertures = nouveau_get_apertures(dev);
977 if (!dev_priv->apertures)
978 return -ENOMEM;
979
980 #ifdef CONFIG_X86
981 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
982 #endif
983
984 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
985 return 0;
986 }
987
988 int nouveau_load(struct drm_device *dev, unsigned long flags)
989 {
990 struct drm_nouveau_private *dev_priv;
991 uint32_t reg0, strap;
992 resource_size_t mmio_start_offs;
993 int ret;
994
995 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
996 if (!dev_priv) {
997 ret = -ENOMEM;
998 goto err_out;
999 }
1000 dev->dev_private = dev_priv;
1001 dev_priv->dev = dev;
1002
1003 dev_priv->flags = flags & NOUVEAU_FLAGS;
1004
1005 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1006 dev->pci_vendor, dev->pci_device, dev->pdev->class);
1007
1008 /* resource 0 is mmio regs */
1009 /* resource 1 is linear FB */
1010 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
1011 /* resource 6 is bios */
1012
1013 /* map the mmio regs */
1014 mmio_start_offs = pci_resource_start(dev->pdev, 0);
1015 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
1016 if (!dev_priv->mmio) {
1017 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1018 "Please report your setup to " DRIVER_EMAIL "\n");
1019 ret = -EINVAL;
1020 goto err_priv;
1021 }
1022 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
1023 (unsigned long long)mmio_start_offs);
1024
1025 #ifdef __BIG_ENDIAN
1026 /* Put the card in BE mode if it's not */
1027 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1028 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1029
1030 DRM_MEMORYBARRIER();
1031 #endif
1032
1033 /* Time to determine the card architecture */
1034 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1035
1036 /* We're dealing with >=NV10 */
1037 if ((reg0 & 0x0f000000) > 0) {
1038 /* Bit 27-20 contain the architecture in hex */
1039 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1040 /* NV04 or NV05 */
1041 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1042 if (reg0 & 0x00f00000)
1043 dev_priv->chipset = 0x05;
1044 else
1045 dev_priv->chipset = 0x04;
1046 } else
1047 dev_priv->chipset = 0xff;
1048
1049 switch (dev_priv->chipset & 0xf0) {
1050 case 0x00:
1051 case 0x10:
1052 case 0x20:
1053 case 0x30:
1054 dev_priv->card_type = dev_priv->chipset & 0xf0;
1055 break;
1056 case 0x40:
1057 case 0x60:
1058 dev_priv->card_type = NV_40;
1059 break;
1060 case 0x50:
1061 case 0x80:
1062 case 0x90:
1063 case 0xa0:
1064 dev_priv->card_type = NV_50;
1065 break;
1066 case 0xc0:
1067 dev_priv->card_type = NV_C0;
1068 break;
1069 case 0xd0:
1070 dev_priv->card_type = NV_D0;
1071 break;
1072 default:
1073 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
1074 ret = -EINVAL;
1075 goto err_mmio;
1076 }
1077
1078 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1079 dev_priv->card_type, reg0);
1080
1081 /* determine frequency of timing crystal */
1082 strap = nv_rd32(dev, 0x101000);
1083 if ( dev_priv->chipset < 0x17 ||
1084 (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1085 strap &= 0x00000040;
1086 else
1087 strap &= 0x00400040;
1088
1089 switch (strap) {
1090 case 0x00000000: dev_priv->crystal = 13500; break;
1091 case 0x00000040: dev_priv->crystal = 14318; break;
1092 case 0x00400000: dev_priv->crystal = 27000; break;
1093 case 0x00400040: dev_priv->crystal = 25000; break;
1094 }
1095
1096 NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1097
1098 /* Determine whether we'll attempt acceleration or not, some
1099 * cards are disabled by default here due to them being known
1100 * non-functional, or never been tested due to lack of hw.
1101 */
1102 dev_priv->noaccel = !!nouveau_noaccel;
1103 if (nouveau_noaccel == -1) {
1104 switch (dev_priv->chipset) {
1105 case 0xc1: /* known broken */
1106 case 0xc8: /* never tested */
1107 NV_INFO(dev, "acceleration disabled by default, pass "
1108 "noaccel=0 to force enable\n");
1109 dev_priv->noaccel = true;
1110 break;
1111 default:
1112 dev_priv->noaccel = false;
1113 break;
1114 }
1115 }
1116
1117 ret = nouveau_remove_conflicting_drivers(dev);
1118 if (ret)
1119 goto err_mmio;
1120
1121 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1122 if (dev_priv->card_type >= NV_40) {
1123 int ramin_bar = 2;
1124 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1125 ramin_bar = 3;
1126
1127 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1128 dev_priv->ramin =
1129 ioremap(pci_resource_start(dev->pdev, ramin_bar),
1130 dev_priv->ramin_size);
1131 if (!dev_priv->ramin) {
1132 NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1133 ret = -ENOMEM;
1134 goto err_mmio;
1135 }
1136 } else {
1137 dev_priv->ramin_size = 1 * 1024 * 1024;
1138 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1139 dev_priv->ramin_size);
1140 if (!dev_priv->ramin) {
1141 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1142 ret = -ENOMEM;
1143 goto err_mmio;
1144 }
1145 }
1146
1147 nouveau_OF_copy_vbios_to_ramin(dev);
1148
1149 /* Special flags */
1150 if (dev->pci_device == 0x01a0)
1151 dev_priv->flags |= NV_NFORCE;
1152 else if (dev->pci_device == 0x01f0)
1153 dev_priv->flags |= NV_NFORCE2;
1154
1155 /* For kernel modesetting, init card now and bring up fbcon */
1156 ret = nouveau_card_init(dev);
1157 if (ret)
1158 goto err_ramin;
1159
1160 return 0;
1161
1162 err_ramin:
1163 iounmap(dev_priv->ramin);
1164 err_mmio:
1165 iounmap(dev_priv->mmio);
1166 err_priv:
1167 kfree(dev_priv);
1168 dev->dev_private = NULL;
1169 err_out:
1170 return ret;
1171 }
1172
1173 void nouveau_lastclose(struct drm_device *dev)
1174 {
1175 vga_switcheroo_process_delayed_switch();
1176 }
1177
1178 int nouveau_unload(struct drm_device *dev)
1179 {
1180 struct drm_nouveau_private *dev_priv = dev->dev_private;
1181
1182 nouveau_card_takedown(dev);
1183
1184 iounmap(dev_priv->mmio);
1185 iounmap(dev_priv->ramin);
1186
1187 kfree(dev_priv);
1188 dev->dev_private = NULL;
1189 return 0;
1190 }
1191
1192 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1193 struct drm_file *file_priv)
1194 {
1195 struct drm_nouveau_private *dev_priv = dev->dev_private;
1196 struct drm_nouveau_getparam *getparam = data;
1197
1198 switch (getparam->param) {
1199 case NOUVEAU_GETPARAM_CHIPSET_ID:
1200 getparam->value = dev_priv->chipset;
1201 break;
1202 case NOUVEAU_GETPARAM_PCI_VENDOR:
1203 getparam->value = dev->pci_vendor;
1204 break;
1205 case NOUVEAU_GETPARAM_PCI_DEVICE:
1206 getparam->value = dev->pci_device;
1207 break;
1208 case NOUVEAU_GETPARAM_BUS_TYPE:
1209 if (drm_pci_device_is_agp(dev))
1210 getparam->value = NV_AGP;
1211 else if (pci_is_pcie(dev->pdev))
1212 getparam->value = NV_PCIE;
1213 else
1214 getparam->value = NV_PCI;
1215 break;
1216 case NOUVEAU_GETPARAM_FB_SIZE:
1217 getparam->value = dev_priv->fb_available_size;
1218 break;
1219 case NOUVEAU_GETPARAM_AGP_SIZE:
1220 getparam->value = dev_priv->gart_info.aper_size;
1221 break;
1222 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1223 getparam->value = 0; /* deprecated */
1224 break;
1225 case NOUVEAU_GETPARAM_PTIMER_TIME:
1226 getparam->value = dev_priv->engine.timer.read(dev);
1227 break;
1228 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1229 getparam->value = 1;
1230 break;
1231 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1232 getparam->value = dev_priv->card_type < NV_D0;
1233 break;
1234 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1235 /* NV40 and NV50 versions are quite different, but register
1236 * address is the same. User is supposed to know the card
1237 * family anyway... */
1238 if (dev_priv->chipset >= 0x40) {
1239 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1240 break;
1241 }
1242 /* FALLTHRU */
1243 default:
1244 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1245 return -EINVAL;
1246 }
1247
1248 return 0;
1249 }
1250
1251 int
1252 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1253 struct drm_file *file_priv)
1254 {
1255 struct drm_nouveau_setparam *setparam = data;
1256
1257 switch (setparam->param) {
1258 default:
1259 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1260 return -EINVAL;
1261 }
1262
1263 return 0;
1264 }
1265
1266 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1267 bool
1268 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1269 uint32_t reg, uint32_t mask, uint32_t val)
1270 {
1271 struct drm_nouveau_private *dev_priv = dev->dev_private;
1272 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1273 uint64_t start = ptimer->read(dev);
1274
1275 do {
1276 if ((nv_rd32(dev, reg) & mask) == val)
1277 return true;
1278 } while (ptimer->read(dev) - start < timeout);
1279
1280 return false;
1281 }
1282
1283 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1284 bool
1285 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1286 uint32_t reg, uint32_t mask, uint32_t val)
1287 {
1288 struct drm_nouveau_private *dev_priv = dev->dev_private;
1289 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1290 uint64_t start = ptimer->read(dev);
1291
1292 do {
1293 if ((nv_rd32(dev, reg) & mask) != val)
1294 return true;
1295 } while (ptimer->read(dev) - start < timeout);
1296
1297 return false;
1298 }
1299
1300 /* Wait until cond(data) == true, up until timeout has hit */
1301 bool
1302 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1303 bool (*cond)(void *), void *data)
1304 {
1305 struct drm_nouveau_private *dev_priv = dev->dev_private;
1306 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1307 u64 start = ptimer->read(dev);
1308
1309 do {
1310 if (cond(data) == true)
1311 return true;
1312 } while (ptimer->read(dev) - start < timeout);
1313
1314 return false;
1315 }
1316
1317 /* Waits for PGRAPH to go completely idle */
1318 bool nouveau_wait_for_idle(struct drm_device *dev)
1319 {
1320 struct drm_nouveau_private *dev_priv = dev->dev_private;
1321 uint32_t mask = ~0;
1322
1323 if (dev_priv->card_type == NV_40)
1324 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1325
1326 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1327 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1328 nv_rd32(dev, NV04_PGRAPH_STATUS));
1329 return false;
1330 }
1331
1332 return true;
1333 }
1334
Linux with added FPC-III support