drivers/gpu/drm/nouveau/nv04_timer.c

   1 #include "drmP.h"
   2 #include "drm.h"
   3 #include "nouveau_drv.h"
   4 #include "nouveau_drm.h"
   5
   6 int
   7 nv04_timer_init(struct drm_device *dev)
   8 {
   9         struct drm_nouveau_private *dev_priv = dev->dev_private;
  10         u32 m, n, d;
  11
  12         nv_wr32(dev, NV04_PTIMER_INTR_EN_0, 0x00000000);
  13         nv_wr32(dev, NV04_PTIMER_INTR_0, 0xFFFFFFFF);
  14
  15         /* aim for 31.25MHz, which gives us nanosecond timestamps */
  16         d = 1000000 / 32;
  17
  18         /* determine base clock for timer source */
  19         if (dev_priv->chipset < 0x40) {
  20                 n = dev_priv->engine.pm.clock_get(dev, PLL_CORE);
  21         } else
  22         if (dev_priv->chipset == 0x40) {
  23                 /*XXX: figure this out */
  24                 n = 0;
  25         } else {
  26                 n = dev_priv->crystal;
  27                 m = 1;
  28                 while (n < (d * 2)) {
  29                         n += (n / m);
  30                         m++;
  31                 }
  32
  33                 nv_wr32(dev, 0x009220, m - 1);
  34         }
  35
  36         if (!n) {
  37                 NV_WARN(dev, "PTIMER: unknown input clock freq\n");
  38                 if (!nv_rd32(dev, NV04_PTIMER_NUMERATOR) ||
  39                     !nv_rd32(dev, NV04_PTIMER_DENOMINATOR)) {
  40                         nv_wr32(dev, NV04_PTIMER_NUMERATOR, 1);
  41                         nv_wr32(dev, NV04_PTIMER_DENOMINATOR, 1);
  42                 }
  43                 return 0;
  44         }
  45
  46         /* reduce ratio to acceptable values */
  47         while (((n % 5) == 0) && ((d % 5) == 0)) {
  48                 n /= 5;
  49                 d /= 5;
  50         }
  51
  52         while (((n % 2) == 0) && ((d % 2) == 0)) {
  53                 n /= 2;
  54                 d /= 2;
  55         }
  56
  57         while (n > 0xffff || d > 0xffff) {
  58                 n >>= 1;
  59                 d >>= 1;
  60         }
  61
  62         nv_wr32(dev, NV04_PTIMER_NUMERATOR, n);
  63         nv_wr32(dev, NV04_PTIMER_DENOMINATOR, d);
  64         return 0;
  65 }
  66
  67 u64
  68 nv04_timer_read(struct drm_device *dev)
  69 {
  70         u32 hi, lo;
  71
  72         do {
  73                 hi = nv_rd32(dev, NV04_PTIMER_TIME_1);
  74                 lo = nv_rd32(dev, NV04_PTIMER_TIME_0);
  75         } while (hi != nv_rd32(dev, NV04_PTIMER_TIME_1));
  76
  77         return ((u64)hi << 32 | lo);
  78 }
  79
  80 void
  81 nv04_timer_takedown(struct drm_device *dev)
  82 {
  83 }