drivers/gpu/drm/nouveau/nv40_pm.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_bios.h"
  28 #include "nouveau_pm.h"
  29 #include "nouveau_hw.h"
  30
  31 #define min2(a,b) ((a) < (b) ? (a) : (b))
  32
  33 static u32
  34 read_pll_1(struct drm_device *dev, u32 reg)
  35 {
  36         u32 ctrl = nv_rd32(dev, reg + 0x00);
  37         int P = (ctrl & 0x00070000) >> 16;
  38         int N = (ctrl & 0x0000ff00) >> 8;
  39         int M = (ctrl & 0x000000ff) >> 0;
  40         u32 ref = 27000, clk = 0;
  41
  42         if (ctrl & 0x80000000)
  43                 clk = ref * N / M;
  44
  45         return clk >> P;
  46 }
  47
  48 static u32
  49 read_pll_2(struct drm_device *dev, u32 reg)
  50 {
  51         u32 ctrl = nv_rd32(dev, reg + 0x00);
  52         u32 coef = nv_rd32(dev, reg + 0x04);
  53         int N2 = (coef & 0xff000000) >> 24;
  54         int M2 = (coef & 0x00ff0000) >> 16;
  55         int N1 = (coef & 0x0000ff00) >> 8;
  56         int M1 = (coef & 0x000000ff) >> 0;
  57         int P = (ctrl & 0x00070000) >> 16;
  58         u32 ref = 27000, clk = 0;
  59
  60         if (ctrl & 0x80000000)
  61                 clk = ref * N1 / M1;
  62
  63         if (!(ctrl & 0x00000100)) {
  64                 if (ctrl & 0x40000000)
  65                         clk = clk * N2 / M2;
  66         }
  67
  68         return clk >> P;
  69 }
  70
  71 static u32
  72 read_clk(struct drm_device *dev, u32 src)
  73 {
  74         switch (src) {
  75         case 3:
  76                 return read_pll_2(dev, 0x004000);
  77         case 2:
  78                 return read_pll_1(dev, 0x004008);
  79         default:
  80                 break;
  81         }
  82
  83         return 0;
  84 }
  85
  86 int
  87 nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
  88 {
  89         u32 ctrl = nv_rd32(dev, 0x00c040);
  90
  91         perflvl->core   = read_clk(dev, (ctrl & 0x00000003) >> 0);
  92         perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4);
  93         perflvl->memory = read_pll_2(dev, 0x4020);
  94         return 0;
  95 }
  96
  97 struct nv40_pm_state {
  98         u32 ctrl;
  99         u32 npll_ctrl;
 100         u32 npll_coef;
 101         u32 spll;
 102         u32 mpll_ctrl;
 103         u32 mpll_coef;
 104 };
 105
 106 static int
 107 nv40_calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll,
 108               u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P)
 109 {
 110         struct nouveau_pll_vals coef;
 111         int ret;
 112
 113         ret = get_pll_limits(dev, reg, pll);
 114         if (ret)
 115                 return ret;
 116
 117         if (clk < pll->vco1.maxfreq)
 118                 pll->vco2.maxfreq = 0;
 119
 120         ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef);
 121         if (ret == 0)
 122                 return -ERANGE;
 123
 124         *N1 = coef.N1;
 125         *M1 = coef.M1;
 126         if (N2 && M2) {
 127                 if (pll->vco2.maxfreq) {
 128                         *N2 = coef.N2;
 129                         *M2 = coef.M2;
 130                 } else {
 131                         *N2 = 1;
 132                         *M2 = 1;
 133                 }
 134         }
 135         *log2P = coef.log2P;
 136         return 0;
 137 }
 138
 139 void *
 140 nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
 141 {
 142         struct nv40_pm_state *info;
 143         struct pll_lims pll;
 144         int N1, N2, M1, M2, log2P;
 145         int ret;
 146
 147         info = kmalloc(sizeof(*info), GFP_KERNEL);
 148         if (!info)
 149                 return ERR_PTR(-ENOMEM);
 150
 151         /* core/geometric clock */
 152         ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core,
 153                             &N1, &M1, &N2, &M2, &log2P);
 154         if (ret < 0)
 155                 goto out;
 156
 157         if (N2 == M2) {
 158                 info->npll_ctrl = 0x80000100 | (log2P << 16);
 159                 info->npll_coef = (N1 << 8) | M1;
 160         } else {
 161                 info->npll_ctrl = 0xc0000000 | (log2P << 16);
 162                 info->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
 163         }
 164
 165         /* use the second PLL for shader/rop clock, if it differs from core */
 166         if (perflvl->shader && perflvl->shader != perflvl->core) {
 167                 ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader,
 168                                     &N1, &M1, NULL, NULL, &log2P);
 169                 if (ret < 0)
 170                         goto out;
 171
 172                 info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
 173                 info->ctrl = 0x00000223;
 174         } else {
 175                 info->spll = 0x00000000;
 176                 info->ctrl = 0x00000333;
 177         }
 178
 179         /* memory clock */
 180         ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,
 181                             &N1, &M1, &N2, &M2, &log2P);
 182         if (ret < 0)
 183                 goto out;
 184
 185         info->mpll_ctrl  = 0x80000000 | (log2P << 16);
 186         info->mpll_ctrl |= min2(pll.log2p_bias + log2P, pll.max_log2p) << 20;
 187         if (N2 == M2) {
 188                 info->mpll_ctrl |= 0x00000100;
 189                 info->mpll_coef  = (N1 << 8) | M1;
 190         } else {
 191                 info->mpll_ctrl |= 0x40000000;
 192                 info->mpll_coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
 193         }
 194
 195 out:
 196         if (ret < 0) {
 197                 kfree(info);
 198                 info = ERR_PTR(ret);
 199         }
 200         return info;
 201 }
 202
 203 static bool
 204 nv40_pm_gr_idle(void *data)
 205 {
 206         struct drm_device *dev = data;
 207
 208         if ((nv_rd32(dev, 0x400760) & 0x000000f0) >> 4 !=
 209             (nv_rd32(dev, 0x400760) & 0x0000000f))
 210                 return false;
 211
 212         if (nv_rd32(dev, 0x400700))
 213                 return false;
 214
 215         return true;
 216 }
 217
 218 void
 219 nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
 220 {
 221         struct drm_nouveau_private *dev_priv = dev->dev_private;
 222         struct nv40_pm_state *info = pre_state;
 223         unsigned long flags;
 224         struct bit_entry M;
 225         u32 crtc_mask = 0;
 226         u8 sr1[2];
 227         int i;
 228
 229         /* determine which CRTCs are active, fetch VGA_SR1 for each */
 230         for (i = 0; i < 2; i++) {
 231                 u32 vbl = nv_rd32(dev, 0x600808 + (i * 0x2000));
 232                 u32 cnt = 0;
 233                 do {
 234                         if (vbl != nv_rd32(dev, 0x600808 + (i * 0x2000))) {
 235                                 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);
 236                                 sr1[i] = nv_rd08(dev, 0x0c03c5 + (i * 0x2000));
 237                                 if (!(sr1[i] & 0x20))
 238                                         crtc_mask |= (1 << i);
 239                                 break;
 240                         }
 241                         udelay(1);
 242                 } while (cnt++ < 32);
 243         }
 244
 245         /* halt and idle engines */
 246         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 247         nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
 248         if (!nv_wait(dev, 0x002500, 0x00000010, 0x00000000))
 249                 goto resume;
 250         nv_mask(dev, 0x003220, 0x00000001, 0x00000000);
 251         if (!nv_wait(dev, 0x003220, 0x00000010, 0x00000000))
 252                 goto resume;
 253         nv_mask(dev, 0x003200, 0x00000001, 0x00000000);
 254         nv04_fifo_cache_pull(dev, false);
 255
 256         if (!nv_wait_cb(dev, nv40_pm_gr_idle, dev))
 257                 goto resume;
 258
 259         /* set engine clocks */
 260         nv_mask(dev, 0x00c040, 0x00000333, 0x00000000);
 261         nv_wr32(dev, 0x004004, info->npll_coef);
 262         nv_mask(dev, 0x004000, 0xc0070100, info->npll_ctrl);
 263         nv_mask(dev, 0x004008, 0xc007ffff, info->spll);
 264         mdelay(5);
 265         nv_mask(dev, 0x00c040, 0x00000333, info->ctrl);
 266
 267         /* wait for vblank start on active crtcs, disable memory access */
 268         for (i = 0; i < 2; i++) {
 269                 if (!(crtc_mask & (1 << i)))
 270                         continue;
 271                 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
 272                 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
 273                 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);
 274                 nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
 275         }
 276
 277         /* prepare ram for reclocking */
 278         nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */
 279         nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
 280         nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
 281         nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
 282         nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */
 283
 284         /* change the PLL of each memory partition */
 285         nv_mask(dev, 0x00c040, 0x0000c000, 0x00000000);
 286         switch (dev_priv->chipset) {
 287         case 0x40:
 288         case 0x45:
 289         case 0x41:
 290         case 0x42:
 291         case 0x47:
 292                 nv_mask(dev, 0x004044, 0xc0771100, info->mpll_ctrl);
 293                 nv_mask(dev, 0x00402c, 0xc0771100, info->mpll_ctrl);
 294                 nv_wr32(dev, 0x004048, info->mpll_coef);
 295                 nv_wr32(dev, 0x004030, info->mpll_coef);
 296         case 0x43:
 297         case 0x49:
 298         case 0x4b:
 299                 nv_mask(dev, 0x004038, 0xc0771100, info->mpll_ctrl);
 300                 nv_wr32(dev, 0x00403c, info->mpll_coef);
 301         default:
 302                 nv_mask(dev, 0x004020, 0xc0771100, info->mpll_ctrl);
 303                 nv_wr32(dev, 0x004024, info->mpll_coef);
 304                 break;
 305         }
 306         udelay(100);
 307         nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000);
 308
 309         /* re-enable normal operation of memory controller */
 310         nv_wr32(dev, 0x1002dc, 0x00000000);
 311         nv_mask(dev, 0x100210, 0x80000000, 0x80000000);
 312         udelay(100);
 313
 314         /* execute memory reset script from vbios */
 315         if (!bit_table(dev, 'M', &M))
 316                 nouveau_bios_init_exec(dev, ROM16(M.data[0]));
 317
 318         /* make sure we're in vblank (hopefully the same one as before), and
 319          * then re-enable crtc memory access
 320          */
 321         for (i = 0; i < 2; i++) {
 322                 if (!(crtc_mask & (1 << i)))
 323                         continue;
 324                 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
 325                 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01);
 326                 nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i]);
 327         }
 328
 329         /* resume engines */
 330 resume:
 331         nv_wr32(dev, 0x003250, 0x00000001);
 332         nv_mask(dev, 0x003220, 0x00000001, 0x00000001);
 333         nv_wr32(dev, 0x003200, 0x00000001);
 334         nv_wr32(dev, 0x002500, 0x00000001);
 335         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 336
 337         kfree(info);
 338 }