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[S390] Remove error checking from copy_oldmem_page()
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nv50_crtc.c
blob882080e0b4f5c2932db3ccfa91976de88f92d3ba
1 /*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "drmP.h"
28 #include "drm_mode.h"
29 #include "drm_crtc_helper.h"
30
31 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
32 #include "nouveau_reg.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_hw.h"
35 #include "nouveau_encoder.h"
36 #include "nouveau_crtc.h"
37 #include "nouveau_fb.h"
38 #include "nouveau_connector.h"
39 #include "nv50_display.h"
40
41 static void
42 nv50_crtc_lut_load(struct drm_crtc *crtc)
43 {
44 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
46 int i;
47
48 NV_DEBUG_KMS(crtc->dev, "\n");
49
50 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
52 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
53 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
54 }
55
56 if (nv_crtc->lut.depth == 30) {
57 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
58 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
59 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
60 }
61 }
62
63 int
64 nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
65 {
66 struct drm_device *dev = nv_crtc->base.dev;
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_channel *evo = nv50_display(dev)->master;
69 int index = nv_crtc->index, ret;
70
71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
73
74 if (blanked) {
75 nv_crtc->cursor.hide(nv_crtc, false);
76
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
78 if (ret) {
79 NV_ERROR(dev, "no space while blanking crtc\n");
80 return ret;
81 }
82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
84 OUT_RING(evo, 0);
85 if (dev_priv->chipset != 0x50) {
86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
88 }
89
90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
92 } else {
93 if (nv_crtc->cursor.visible)
94 nv_crtc->cursor.show(nv_crtc, false);
95 else
96 nv_crtc->cursor.hide(nv_crtc, false);
97
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
99 if (ret) {
100 NV_ERROR(dev, "no space while unblanking crtc\n");
101 return ret;
102 }
103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
105 NV50_EVO_CRTC_CLUT_MODE_OFF :
106 NV50_EVO_CRTC_CLUT_MODE_ON);
107 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8);
108 if (dev_priv->chipset != 0x50) {
109 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
110 OUT_RING(evo, NvEvoVRAM);
111 }
112
113 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
114 OUT_RING(evo, nv_crtc->fb.offset >> 8);
115 OUT_RING(evo, 0);
116 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
117 if (dev_priv->chipset != 0x50)
118 if (nv_crtc->fb.tile_flags == 0x7a00 ||
119 nv_crtc->fb.tile_flags == 0xfe00)
120 OUT_RING(evo, NvEvoFB32);
121 else
122 if (nv_crtc->fb.tile_flags == 0x7000)
123 OUT_RING(evo, NvEvoFB16);
124 else
125 OUT_RING(evo, NvEvoVRAM_LP);
126 else
127 OUT_RING(evo, NvEvoVRAM_LP);
128 }
129
130 nv_crtc->fb.blanked = blanked;
131 return 0;
132 }
133
134 static int
135 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
136 {
137 struct drm_device *dev = nv_crtc->base.dev;
138 struct nouveau_channel *evo = nv50_display(dev)->master;
139 int ret;
140
141 NV_DEBUG_KMS(dev, "\n");
142
143 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
144 if (ret) {
145 NV_ERROR(dev, "no space while setting dither\n");
146 return ret;
147 }
148
149 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
150 if (on)
151 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
152 else
153 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
154
155 if (update) {
156 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
157 OUT_RING(evo, 0);
158 FIRE_RING(evo);
159 }
160
161 return 0;
162 }
163
164 struct nouveau_connector *
165 nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
166 {
167 struct drm_device *dev = nv_crtc->base.dev;
168 struct drm_connector *connector;
169 struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
170
171 /* The safest approach is to find an encoder with the right crtc, that
172 * is also linked to a connector. */
173 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
174 if (connector->encoder)
175 if (connector->encoder->crtc == crtc)
176 return nouveau_connector(connector);
177 }
178
179 return NULL;
180 }
181
182 static int
183 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
184 {
185 struct nouveau_connector *nv_connector =
186 nouveau_crtc_connector_get(nv_crtc);
187 struct drm_device *dev = nv_crtc->base.dev;
188 struct nouveau_channel *evo = nv50_display(dev)->master;
189 struct drm_display_mode *native_mode = NULL;
190 struct drm_display_mode *mode = &nv_crtc->base.mode;
191 uint32_t outX, outY, horiz, vert;
192 int ret;
193
194 NV_DEBUG_KMS(dev, "\n");
195
196 switch (scaling_mode) {
197 case DRM_MODE_SCALE_NONE:
198 break;
199 default:
200 if (!nv_connector || !nv_connector->native_mode) {
201 NV_ERROR(dev, "No native mode, forcing panel scaling\n");
202 scaling_mode = DRM_MODE_SCALE_NONE;
203 } else {
204 native_mode = nv_connector->native_mode;
205 }
206 break;
207 }
208
209 switch (scaling_mode) {
210 case DRM_MODE_SCALE_ASPECT:
211 horiz = (native_mode->hdisplay << 19) / mode->hdisplay;
212 vert = (native_mode->vdisplay << 19) / mode->vdisplay;
213
214 if (vert > horiz) {
215 outX = (mode->hdisplay * horiz) >> 19;
216 outY = (mode->vdisplay * horiz) >> 19;
217 } else {
218 outX = (mode->hdisplay * vert) >> 19;
219 outY = (mode->vdisplay * vert) >> 19;
220 }
221 break;
222 case DRM_MODE_SCALE_FULLSCREEN:
223 outX = native_mode->hdisplay;
224 outY = native_mode->vdisplay;
225 break;
226 case DRM_MODE_SCALE_CENTER:
227 case DRM_MODE_SCALE_NONE:
228 default:
229 outX = mode->hdisplay;
230 outY = mode->vdisplay;
231 break;
232 }
233
234 ret = RING_SPACE(evo, update ? 7 : 5);
235 if (ret)
236 return ret;
237
238 /* Got a better name for SCALER_ACTIVE? */
239 /* One day i've got to really figure out why this is needed. */
240 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
241 if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ||
242 (mode->flags & DRM_MODE_FLAG_INTERLACE) ||
243 mode->hdisplay != outX || mode->vdisplay != outY) {
244 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
245 } else {
246 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
247 }
248
249 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
250 OUT_RING(evo, outY << 16 | outX);
251 OUT_RING(evo, outY << 16 | outX);
252
253 if (update) {
254 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
255 OUT_RING(evo, 0);
256 FIRE_RING(evo);
257 }
258
259 return 0;
260 }
261
262 int
263 nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
264 {
265 struct drm_nouveau_private *dev_priv = dev->dev_private;
266 struct pll_lims pll;
267 uint32_t reg1, reg2;
268 int ret, N1, M1, N2, M2, P;
269
270 ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll);
271 if (ret)
272 return ret;
273
274 if (pll.vco2.maxfreq) {
275 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
276 if (ret <= 0)
277 return 0;
278
279 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
280 pclk, ret, N1, M1, N2, M2, P);
281
282 reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00;
283 reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00;
284 nv_wr32(dev, pll.reg + 0, 0x10000611);
285 nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1);
286 nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
287 } else
288 if (dev_priv->chipset < NV_C0) {
289 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
290 if (ret <= 0)
291 return 0;
292
293 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
294 pclk, ret, N1, N2, M1, P);
295
296 reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000;
297 nv_wr32(dev, pll.reg + 0, 0x50000610);
298 nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
299 nv_wr32(dev, pll.reg + 8, N2);
300 } else {
301 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
302 if (ret <= 0)
303 return 0;
304
305 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
306 pclk, ret, N1, N2, M1, P);
307
308 nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100);
309 nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1);
310 nv_wr32(dev, pll.reg + 0x10, N2 << 16);
311 }
312
313 return 0;
314 }
315
316 static void
317 nv50_crtc_destroy(struct drm_crtc *crtc)
318 {
319 struct drm_device *dev;
320 struct nouveau_crtc *nv_crtc;
321
322 if (!crtc)
323 return;
324
325 dev = crtc->dev;
326 nv_crtc = nouveau_crtc(crtc);
327
328 NV_DEBUG_KMS(dev, "\n");
329
330 drm_crtc_cleanup(&nv_crtc->base);
331
332 nouveau_bo_unmap(nv_crtc->lut.nvbo);
333 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
334 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
335 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
336 kfree(nv_crtc->mode);
337 kfree(nv_crtc);
338 }
339
340 int
341 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
342 uint32_t buffer_handle, uint32_t width, uint32_t height)
343 {
344 struct drm_device *dev = crtc->dev;
345 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
346 struct nouveau_bo *cursor = NULL;
347 struct drm_gem_object *gem;
348 int ret = 0, i;
349
350 if (!buffer_handle) {
351 nv_crtc->cursor.hide(nv_crtc, true);
352 return 0;
353 }
354
355 if (width != 64 || height != 64)
356 return -EINVAL;
357
358 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
359 if (!gem)
360 return -ENOENT;
361 cursor = nouveau_gem_object(gem);
362
363 ret = nouveau_bo_map(cursor);
364 if (ret)
365 goto out;
366
367 /* The simple will do for now. */
368 for (i = 0; i < 64 * 64; i++)
369 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
370
371 nouveau_bo_unmap(cursor);
372
373 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset);
374 nv_crtc->cursor.show(nv_crtc, true);
375
376 out:
377 drm_gem_object_unreference_unlocked(gem);
378 return ret;
379 }
380
381 int
382 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
383 {
384 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
385
386 nv_crtc->cursor.set_pos(nv_crtc, x, y);
387 return 0;
388 }
389
390 static void
391 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
392 uint32_t start, uint32_t size)
393 {
394 int end = (start + size > 256) ? 256 : start + size, i;
395 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
396
397 for (i = start; i < end; i++) {
398 nv_crtc->lut.r[i] = r[i];
399 nv_crtc->lut.g[i] = g[i];
400 nv_crtc->lut.b[i] = b[i];
401 }
402
403 /* We need to know the depth before we upload, but it's possible to
404 * get called before a framebuffer is bound. If this is the case,
405 * mark the lut values as dirty by setting depth==0, and it'll be
406 * uploaded on the first mode_set_base()
407 */
408 if (!nv_crtc->base.fb) {
409 nv_crtc->lut.depth = 0;
410 return;
411 }
412
413 nv50_crtc_lut_load(crtc);
414 }
415
416 static void
417 nv50_crtc_save(struct drm_crtc *crtc)
418 {
419 NV_ERROR(crtc->dev, "!!\n");
420 }
421
422 static void
423 nv50_crtc_restore(struct drm_crtc *crtc)
424 {
425 NV_ERROR(crtc->dev, "!!\n");
426 }
427
428 static const struct drm_crtc_funcs nv50_crtc_funcs = {
429 .save = nv50_crtc_save,
430 .restore = nv50_crtc_restore,
431 .cursor_set = nv50_crtc_cursor_set,
432 .cursor_move = nv50_crtc_cursor_move,
433 .gamma_set = nv50_crtc_gamma_set,
434 .set_config = drm_crtc_helper_set_config,
435 .page_flip = nouveau_crtc_page_flip,
436 .destroy = nv50_crtc_destroy,
437 };
438
439 static void
440 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
441 {
442 }
443
444 static int
445 nv50_crtc_wait_complete(struct drm_crtc *crtc)
446 {
447 struct drm_device *dev = crtc->dev;
448 struct drm_nouveau_private *dev_priv = dev->dev_private;
449 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
450 struct nv50_display *disp = nv50_display(dev);
451 struct nouveau_channel *evo = disp->master;
452 u64 start;
453 int ret;
454
455 ret = RING_SPACE(evo, 6);
456 if (ret)
457 return ret;
458 BEGIN_RING(evo, 0, 0x0084, 1);
459 OUT_RING (evo, 0x80000000);
460 BEGIN_RING(evo, 0, 0x0080, 1);
461 OUT_RING (evo, 0);
462 BEGIN_RING(evo, 0, 0x0084, 1);
463 OUT_RING (evo, 0x00000000);
464
465 nv_wo32(disp->ntfy, 0x000, 0x00000000);
466 FIRE_RING (evo);
467
468 start = ptimer->read(dev);
469 do {
470 if (nv_ro32(disp->ntfy, 0x000))
471 return 0;
472 } while (ptimer->read(dev) - start < 2000000000ULL);
473
474 return -EBUSY;
475 }
476
477 static void
478 nv50_crtc_prepare(struct drm_crtc *crtc)
479 {
480 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
481 struct drm_device *dev = crtc->dev;
482
483 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
484
485 nv50_display_flip_stop(crtc);
486 drm_vblank_pre_modeset(dev, nv_crtc->index);
487 nv50_crtc_blank(nv_crtc, true);
488 }
489
490 static void
491 nv50_crtc_commit(struct drm_crtc *crtc)
492 {
493 struct drm_device *dev = crtc->dev;
494 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
495
496 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
497
498 nv50_crtc_blank(nv_crtc, false);
499 drm_vblank_post_modeset(dev, nv_crtc->index);
500 nv50_crtc_wait_complete(crtc);
501 nv50_display_flip_next(crtc, crtc->fb, NULL);
502 }
503
504 static bool
505 nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
506 struct drm_display_mode *adjusted_mode)
507 {
508 return true;
509 }
510
511 static int
512 nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
513 struct drm_framebuffer *passed_fb,
514 int x, int y, bool atomic)
515 {
516 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
517 struct drm_device *dev = nv_crtc->base.dev;
518 struct drm_nouveau_private *dev_priv = dev->dev_private;
519 struct nouveau_channel *evo = nv50_display(dev)->master;
520 struct drm_framebuffer *drm_fb;
521 struct nouveau_framebuffer *fb;
522 int ret;
523
524 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
525
526 /* no fb bound */
527 if (!atomic && !crtc->fb) {
528 NV_DEBUG_KMS(dev, "No FB bound\n");
529 return 0;
530 }
531
532 /* If atomic, we want to switch to the fb we were passed, so
533 * now we update pointers to do that. (We don't pin; just
534 * assume we're already pinned and update the base address.)
535 */
536 if (atomic) {
537 drm_fb = passed_fb;
538 fb = nouveau_framebuffer(passed_fb);
539 } else {
540 drm_fb = crtc->fb;
541 fb = nouveau_framebuffer(crtc->fb);
542 /* If not atomic, we can go ahead and pin, and unpin the
543 * old fb we were passed.
544 */
545 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
546 if (ret)
547 return ret;
548
549 if (passed_fb) {
550 struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
551 nouveau_bo_unpin(ofb->nvbo);
552 }
553 }
554
555 nv_crtc->fb.offset = fb->nvbo->bo.offset;
556 nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo);
557 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
558 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
559 ret = RING_SPACE(evo, 2);
560 if (ret)
561 return ret;
562
563 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
564 OUT_RING (evo, fb->r_dma);
565 }
566
567 ret = RING_SPACE(evo, 12);
568 if (ret)
569 return ret;
570
571 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
572 OUT_RING (evo, nv_crtc->fb.offset >> 8);
573 OUT_RING (evo, 0);
574 OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width);
575 OUT_RING (evo, fb->r_pitch);
576 OUT_RING (evo, fb->r_format);
577
578 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
579 OUT_RING (evo, fb->base.depth == 8 ?
580 NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
581
582 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
583 OUT_RING (evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
584 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
585 OUT_RING (evo, (y << 16) | x);
586
587 if (nv_crtc->lut.depth != fb->base.depth) {
588 nv_crtc->lut.depth = fb->base.depth;
589 nv50_crtc_lut_load(crtc);
590 }
591
592 return 0;
593 }
594
595 static int
596 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
597 struct drm_display_mode *adjusted_mode, int x, int y,
598 struct drm_framebuffer *old_fb)
599 {
600 struct drm_device *dev = crtc->dev;
601 struct nouveau_channel *evo = nv50_display(dev)->master;
602 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
603 struct nouveau_connector *nv_connector = NULL;
604 uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
605 uint32_t hunk1, vunk1, vunk2a, vunk2b;
606 int ret;
607
608 /* Find the connector attached to this CRTC */
609 nv_connector = nouveau_crtc_connector_get(nv_crtc);
610
611 *nv_crtc->mode = *adjusted_mode;
612
613 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
614
615 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
616 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
617 hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
618 vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
619 /* I can't give this a proper name, anyone else can? */
620 hunk1 = adjusted_mode->htotal -
621 adjusted_mode->hsync_start + adjusted_mode->hdisplay;
622 vunk1 = adjusted_mode->vtotal -
623 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
624 /* Another strange value, this time only for interlaced adjusted_modes. */
625 vunk2a = 2 * adjusted_mode->vtotal -
626 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
627 vunk2b = adjusted_mode->vtotal -
628 adjusted_mode->vsync_start + adjusted_mode->vtotal;
629
630 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
631 vsync_dur /= 2;
632 vsync_start_to_end /= 2;
633 vunk1 /= 2;
634 vunk2a /= 2;
635 vunk2b /= 2;
636 /* magic */
637 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
638 vsync_start_to_end -= 1;
639 vunk1 -= 1;
640 vunk2a -= 1;
641 vunk2b -= 1;
642 }
643 }
644
645 ret = RING_SPACE(evo, 17);
646 if (ret)
647 return ret;
648
649 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
650 OUT_RING(evo, adjusted_mode->clock | 0x800000);
651 OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
652
653 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
654 OUT_RING(evo, 0);
655 OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
656 OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
657 OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
658 (hsync_start_to_end - 1));
659 OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
660
661 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
662 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
663 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
664 } else {
665 OUT_RING(evo, 0);
666 OUT_RING(evo, 0);
667 }
668
669 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
670 OUT_RING(evo, 0);
671
672 /* This is the actual resolution of the mode. */
673 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
674 OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
675 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
676 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
677
678 nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
679 nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
680
681 return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
682 }
683
684 static int
685 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
686 struct drm_framebuffer *old_fb)
687 {
688 int ret;
689
690 nv50_display_flip_stop(crtc);
691 ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
692 if (ret)
693 return ret;
694
695 ret = nv50_crtc_wait_complete(crtc);
696 if (ret)
697 return ret;
698
699 return nv50_display_flip_next(crtc, crtc->fb, NULL);
700 }
701
702 static int
703 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
704 struct drm_framebuffer *fb,
705 int x, int y, enum mode_set_atomic state)
706 {
707 int ret;
708
709 nv50_display_flip_stop(crtc);
710 ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true);
711 if (ret)
712 return ret;
713
714 return nv50_crtc_wait_complete(crtc);
715 }
716
717 static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
718 .dpms = nv50_crtc_dpms,
719 .prepare = nv50_crtc_prepare,
720 .commit = nv50_crtc_commit,
721 .mode_fixup = nv50_crtc_mode_fixup,
722 .mode_set = nv50_crtc_mode_set,
723 .mode_set_base = nv50_crtc_mode_set_base,
724 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
725 .load_lut = nv50_crtc_lut_load,
726 };
727
728 int
729 nv50_crtc_create(struct drm_device *dev, int index)
730 {
731 struct nouveau_crtc *nv_crtc = NULL;
732 int ret, i;
733
734 NV_DEBUG_KMS(dev, "\n");
735
736 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
737 if (!nv_crtc)
738 return -ENOMEM;
739
740 nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
741 if (!nv_crtc->mode) {
742 kfree(nv_crtc);
743 return -ENOMEM;
744 }
745
746 /* Default CLUT parameters, will be activated on the hw upon
747 * first mode set.
748 */
749 for (i = 0; i < 256; i++) {
750 nv_crtc->lut.r[i] = i << 8;
751 nv_crtc->lut.g[i] = i << 8;
752 nv_crtc->lut.b[i] = i << 8;
753 }
754 nv_crtc->lut.depth = 0;
755
756 ret = nouveau_bo_new(dev, 4096, 0x100, TTM_PL_FLAG_VRAM,
757 0, 0x0000, &nv_crtc->lut.nvbo);
758 if (!ret) {
759 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
760 if (!ret)
761 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
762 if (ret)
763 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
764 }
765
766 if (ret) {
767 kfree(nv_crtc->mode);
768 kfree(nv_crtc);
769 return ret;
770 }
771
772 nv_crtc->index = index;
773
774 /* set function pointers */
775 nv_crtc->set_dither = nv50_crtc_set_dither;
776 nv_crtc->set_scale = nv50_crtc_set_scale;
777
778 drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
779 drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
780 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
781
782 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
783 0, 0x0000, &nv_crtc->cursor.nvbo);
784 if (!ret) {
785 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
786 if (!ret)
787 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
788 if (ret)
789 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
790 }
791
792 nv50_cursor_init(nv_crtc);
793 return 0;
794 }
Linux with added FPC-III support