drivers/gpu/drm/nouveau/nv50_gpio.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_hw.h"
  28
  29 #include "nv50_display.h"
  30
  31 static void nv50_gpio_isr(struct drm_device *dev);
  32 static void nv50_gpio_isr_bh(struct work_struct *work);
  33
  34 struct nv50_gpio_priv {
  35         struct list_head handlers;
  36         spinlock_t lock;
  37 };
  38
  39 struct nv50_gpio_handler {
  40         struct drm_device *dev;
  41         struct list_head head;
  42         struct work_struct work;
  43         bool inhibit;
  44
  45         struct dcb_gpio_entry *gpio;
  46
  47         void (*handler)(void *data, int state);
  48         void *data;
  49 };
  50
  51 static int
  52 nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
  53 {
  54         const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
  55
  56         if (gpio->line >= 32)
  57                 return -EINVAL;
  58
  59         *reg = nv50_gpio_reg[gpio->line >> 3];
  60         *shift = (gpio->line & 7) << 2;
  61         return 0;
  62 }
  63
  64 int
  65 nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
  66 {
  67         struct dcb_gpio_entry *gpio;
  68         uint32_t r, s, v;
  69
  70         gpio = nouveau_bios_gpio_entry(dev, tag);
  71         if (!gpio)
  72                 return -ENOENT;
  73
  74         if (nv50_gpio_location(gpio, &r, &s))
  75                 return -EINVAL;
  76
  77         v = nv_rd32(dev, r) >> (s + 2);
  78         return ((v & 1) == (gpio->state[1] & 1));
  79 }
  80
  81 int
  82 nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
  83 {
  84         struct dcb_gpio_entry *gpio;
  85         uint32_t r, s, v;
  86
  87         gpio = nouveau_bios_gpio_entry(dev, tag);
  88         if (!gpio)
  89                 return -ENOENT;
  90
  91         if (nv50_gpio_location(gpio, &r, &s))
  92                 return -EINVAL;
  93
  94         v  = nv_rd32(dev, r) & ~(0x3 << s);
  95         v |= (gpio->state[state] ^ 2) << s;
  96         nv_wr32(dev, r, v);
  97         return 0;
  98 }
  99
 100 int
 101 nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
 102 {
 103         struct dcb_gpio_entry *gpio;
 104         u32 v;
 105
 106         gpio = nouveau_bios_gpio_entry(dev, tag);
 107         if (!gpio)
 108                 return -ENOENT;
 109
 110         v  = nv_rd32(dev, 0x00d610 + (gpio->line * 4));
 111         v &= 0x00004000;
 112         return (!!v == (gpio->state[1] & 1));
 113 }
 114
 115 int
 116 nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
 117 {
 118         struct dcb_gpio_entry *gpio;
 119         u32 v;
 120
 121         gpio = nouveau_bios_gpio_entry(dev, tag);
 122         if (!gpio)
 123                 return -ENOENT;
 124
 125         v = gpio->state[state] ^ 2;
 126
 127         nv_mask(dev, 0x00d610 + (gpio->line * 4), 0x00003000, v << 12);
 128         return 0;
 129 }
 130
 131 int
 132 nv50_gpio_irq_register(struct drm_device *dev, enum dcb_gpio_tag tag,
 133                        void (*handler)(void *, int), void *data)
 134 {
 135         struct drm_nouveau_private *dev_priv = dev->dev_private;
 136         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 137         struct nv50_gpio_priv *priv = pgpio->priv;
 138         struct nv50_gpio_handler *gpioh;
 139         struct dcb_gpio_entry *gpio;
 140         unsigned long flags;
 141
 142         gpio = nouveau_bios_gpio_entry(dev, tag);
 143         if (!gpio)
 144                 return -ENOENT;
 145
 146         gpioh = kzalloc(sizeof(*gpioh), GFP_KERNEL);
 147         if (!gpioh)
 148                 return -ENOMEM;
 149
 150         INIT_WORK(&gpioh->work, nv50_gpio_isr_bh);
 151         gpioh->dev  = dev;
 152         gpioh->gpio = gpio;
 153         gpioh->handler = handler;
 154         gpioh->data = data;
 155
 156         spin_lock_irqsave(&priv->lock, flags);
 157         list_add(&gpioh->head, &priv->handlers);
 158         spin_unlock_irqrestore(&priv->lock, flags);
 159         return 0;
 160 }
 161
 162 void
 163 nv50_gpio_irq_unregister(struct drm_device *dev, enum dcb_gpio_tag tag,
 164                          void (*handler)(void *, int), void *data)
 165 {
 166         struct drm_nouveau_private *dev_priv = dev->dev_private;
 167         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 168         struct nv50_gpio_priv *priv = pgpio->priv;
 169         struct nv50_gpio_handler *gpioh, *tmp;
 170         struct dcb_gpio_entry *gpio;
 171         LIST_HEAD(tofree);
 172         unsigned long flags;
 173
 174         gpio = nouveau_bios_gpio_entry(dev, tag);
 175         if (!gpio)
 176                 return;
 177
 178         spin_lock_irqsave(&priv->lock, flags);
 179         list_for_each_entry_safe(gpioh, tmp, &priv->handlers, head) {
 180                 if (gpioh->gpio != gpio ||
 181                     gpioh->handler != handler ||
 182                     gpioh->data != data)
 183                         continue;
 184                 list_move(&gpioh->head, &tofree);
 185         }
 186         spin_unlock_irqrestore(&priv->lock, flags);
 187
 188         list_for_each_entry_safe(gpioh, tmp, &tofree, head) {
 189                 flush_work_sync(&gpioh->work);
 190                 kfree(gpioh);
 191         }
 192 }
 193
 194 bool
 195 nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
 196 {
 197         struct dcb_gpio_entry *gpio;
 198         u32 reg, mask;
 199
 200         gpio = nouveau_bios_gpio_entry(dev, tag);
 201         if (!gpio)
 202                 return false;
 203
 204         reg  = gpio->line < 16 ? 0xe050 : 0xe070;
 205         mask = 0x00010001 << (gpio->line & 0xf);
 206
 207         nv_wr32(dev, reg + 4, mask);
 208         reg = nv_mask(dev, reg + 0, mask, on ? mask : 0);
 209         return (reg & mask) == mask;
 210 }
 211
 212 static int
 213 nv50_gpio_create(struct drm_device *dev)
 214 {
 215         struct drm_nouveau_private *dev_priv = dev->dev_private;
 216         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 217         struct nv50_gpio_priv *priv;
 218
 219         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 220         if (!priv)
 221                 return -ENOMEM;
 222
 223         INIT_LIST_HEAD(&priv->handlers);
 224         spin_lock_init(&priv->lock);
 225         pgpio->priv = priv;
 226         return 0;
 227 }
 228
 229 static void
 230 nv50_gpio_destroy(struct drm_device *dev)
 231 {
 232         struct drm_nouveau_private *dev_priv = dev->dev_private;
 233         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 234
 235         kfree(pgpio->priv);
 236         pgpio->priv = NULL;
 237 }
 238
 239 int
 240 nv50_gpio_init(struct drm_device *dev)
 241 {
 242         struct drm_nouveau_private *dev_priv = dev->dev_private;
 243         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 244         int ret;
 245
 246         if (!pgpio->priv) {
 247                 ret = nv50_gpio_create(dev);
 248                 if (ret)
 249                         return ret;
 250         }
 251
 252         /* disable, and ack any pending gpio interrupts */
 253         nv_wr32(dev, 0xe050, 0x00000000);
 254         nv_wr32(dev, 0xe054, 0xffffffff);
 255         if (dev_priv->chipset >= 0x90) {
 256                 nv_wr32(dev, 0xe070, 0x00000000);
 257                 nv_wr32(dev, 0xe074, 0xffffffff);
 258         }
 259
 260         nouveau_irq_register(dev, 21, nv50_gpio_isr);
 261         return 0;
 262 }
 263
 264 void
 265 nv50_gpio_fini(struct drm_device *dev)
 266 {
 267         struct drm_nouveau_private *dev_priv = dev->dev_private;
 268
 269         nv_wr32(dev, 0xe050, 0x00000000);
 270         if (dev_priv->chipset >= 0x90)
 271                 nv_wr32(dev, 0xe070, 0x00000000);
 272         nouveau_irq_unregister(dev, 21);
 273
 274         nv50_gpio_destroy(dev);
 275 }
 276
 277 static void
 278 nv50_gpio_isr_bh(struct work_struct *work)
 279 {
 280         struct nv50_gpio_handler *gpioh =
 281                 container_of(work, struct nv50_gpio_handler, work);
 282         struct drm_nouveau_private *dev_priv = gpioh->dev->dev_private;
 283         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 284         struct nv50_gpio_priv *priv = pgpio->priv;
 285         unsigned long flags;
 286         int state;
 287
 288         state = pgpio->get(gpioh->dev, gpioh->gpio->tag);
 289         if (state < 0)
 290                 return;
 291
 292         gpioh->handler(gpioh->data, state);
 293
 294         spin_lock_irqsave(&priv->lock, flags);
 295         gpioh->inhibit = false;
 296         spin_unlock_irqrestore(&priv->lock, flags);
 297 }
 298
 299 static void
 300 nv50_gpio_isr(struct drm_device *dev)
 301 {
 302         struct drm_nouveau_private *dev_priv = dev->dev_private;
 303         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 304         struct nv50_gpio_priv *priv = pgpio->priv;
 305         struct nv50_gpio_handler *gpioh;
 306         u32 intr0, intr1 = 0;
 307         u32 hi, lo, ch;
 308
 309         intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
 310         if (dev_priv->chipset >= 0x90)
 311                 intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
 312
 313         hi = (intr0 & 0x0000ffff) | (intr1 << 16);
 314         lo = (intr0 >> 16) | (intr1 & 0xffff0000);
 315         ch = hi | lo;
 316
 317         nv_wr32(dev, 0xe054, intr0);
 318         if (dev_priv->chipset >= 0x90)
 319                 nv_wr32(dev, 0xe074, intr1);
 320
 321         spin_lock(&priv->lock);
 322         list_for_each_entry(gpioh, &priv->handlers, head) {
 323                 if (!(ch & (1 << gpioh->gpio->line)))
 324                         continue;
 325
 326                 if (gpioh->inhibit)
 327                         continue;
 328                 gpioh->inhibit = true;
 329
 330                 schedule_work(&gpioh->work);
 331         }
 332         spin_unlock(&priv->lock);
 333 }