drivers/gpu/drm/nouveau/nv50_pm.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_bios.h"
  28 #include "nouveau_pm.h"
  29
  30 struct nv50_pm_state {
  31         struct nouveau_pm_level *perflvl;
  32         struct pll_lims pll;
  33         enum pll_types type;
  34         int N, M, P;
  35 };
  36
  37 int
  38 nv50_pm_clock_get(struct drm_device *dev, u32 id)
  39 {
  40         struct pll_lims pll;
  41         int P, N, M, ret;
  42         u32 reg0, reg1;
  43
  44         ret = get_pll_limits(dev, id, &pll);
  45         if (ret)
  46                 return ret;
  47
  48         reg0 = nv_rd32(dev, pll.reg + 0);
  49         reg1 = nv_rd32(dev, pll.reg + 4);
  50
  51         if ((reg0 & 0x80000000) == 0) {
  52                 if (id == PLL_SHADER) {
  53                         NV_DEBUG(dev, "Shader PLL is disabled. "
  54                                 "Shader clock is twice the core\n");
  55                         ret = nv50_pm_clock_get(dev, PLL_CORE);
  56                         if (ret > 0)
  57                                 return ret << 1;
  58                 } else if (id == PLL_MEMORY) {
  59                         NV_DEBUG(dev, "Memory PLL is disabled. "
  60                                 "Memory clock is equal to the ref_clk\n");
  61                         return pll.refclk;
  62                 }
  63         }
  64
  65         P = (reg0 & 0x00070000) >> 16;
  66         N = (reg1 & 0x0000ff00) >> 8;
  67         M = (reg1 & 0x000000ff);
  68
  69         return ((pll.refclk * N / M) >> P);
  70 }
  71
  72 void *
  73 nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
  74                   u32 id, int khz)
  75 {
  76         struct nv50_pm_state *state;
  77         int dummy, ret;
  78
  79         state = kzalloc(sizeof(*state), GFP_KERNEL);
  80         if (!state)
  81                 return ERR_PTR(-ENOMEM);
  82         state->type = id;
  83         state->perflvl = perflvl;
  84
  85         ret = get_pll_limits(dev, id, &state->pll);
  86         if (ret < 0) {
  87                 kfree(state);
  88                 return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
  89         }
  90
  91         ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M,
  92                             &dummy, &dummy, &state->P);
  93         if (ret < 0) {
  94                 kfree(state);
  95                 return ERR_PTR(ret);
  96         }
  97
  98         return state;
  99 }
 100
 101 void
 102 nv50_pm_clock_set(struct drm_device *dev, void *pre_state)
 103 {
 104         struct nv50_pm_state *state = pre_state;
 105         struct nouveau_pm_level *perflvl = state->perflvl;
 106         u32 reg = state->pll.reg, tmp;
 107         struct bit_entry BIT_M;
 108         u16 script;
 109         int N = state->N;
 110         int M = state->M;
 111         int P = state->P;
 112
 113         if (state->type == PLL_MEMORY && perflvl->memscript &&
 114             bit_table(dev, 'M', &BIT_M) == 0 &&
 115             BIT_M.version == 1 && BIT_M.length >= 0x0b) {
 116                 script = ROM16(BIT_M.data[0x05]);
 117                 if (script)
 118                         nouveau_bios_run_init_table(dev, script, NULL, -1);
 119                 script = ROM16(BIT_M.data[0x07]);
 120                 if (script)
 121                         nouveau_bios_run_init_table(dev, script, NULL, -1);
 122                 script = ROM16(BIT_M.data[0x09]);
 123                 if (script)
 124                         nouveau_bios_run_init_table(dev, script, NULL, -1);
 125
 126                 nouveau_bios_run_init_table(dev, perflvl->memscript, NULL, -1);
 127         }
 128
 129         if (state->type == PLL_MEMORY) {
 130                 nv_wr32(dev, 0x100210, 0);
 131                 nv_wr32(dev, 0x1002dc, 1);
 132         }
 133
 134         tmp  = nv_rd32(dev, reg + 0) & 0xfff8ffff;
 135         tmp |= 0x80000000 | (P << 16);
 136         nv_wr32(dev, reg + 0, tmp);
 137         nv_wr32(dev, reg + 4, (N << 8) | M);
 138
 139         if (state->type == PLL_MEMORY) {
 140                 nv_wr32(dev, 0x1002dc, 0);
 141                 nv_wr32(dev, 0x100210, 0x80000000);
 142         }
 143
 144         kfree(state);
 145 }
 146