2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <asm/unaligned.h>
27 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
28 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
29 PORT_RC | PORT_PLC | PORT_PE)
31 /* usb 1.1 root hub device descriptor */
32 static u8 usb_bos_descriptor
[] = {
33 USB_DT_BOS_SIZE
, /* __u8 bLength, 5 bytes */
34 USB_DT_BOS
, /* __u8 bDescriptorType */
35 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
36 0x1, /* __u8 bNumDeviceCaps */
37 /* First device capability */
38 USB_DT_USB_SS_CAP_SIZE
, /* __u8 bLength, 10 bytes */
39 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
40 USB_SS_CAP_TYPE
, /* bDevCapabilityType, SUPERSPEED_USB */
41 0x00, /* bmAttributes, LTM off by default */
42 USB_5GBPS_OPERATION
, 0x00, /* wSpeedsSupported, 5Gbps only */
43 0x03, /* bFunctionalitySupport,
45 0x00, /* bU1DevExitLat, set later. */
46 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
50 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
51 struct usb_hub_descriptor
*desc
, int ports
)
55 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
56 desc
->bHubContrCurrent
= 0;
58 desc
->bNbrPorts
= ports
;
59 /* Ugh, these should be #defines, FIXME */
60 /* Using table 11-13 in USB 2.0 spec. */
62 /* Bits 1:0 - support port power switching, or power always on */
63 if (HCC_PPC(xhci
->hcc_params
))
67 /* Bit 2 - root hubs are not part of a compound device */
68 /* Bits 4:3 - individual port over current protection */
70 /* Bits 6:5 - no TTs in root ports */
71 /* Bit 7 - no port indicators */
72 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
75 /* Fill in the USB 2.0 roothub descriptor */
76 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
77 struct usb_hub_descriptor
*desc
)
81 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
85 ports
= xhci
->num_usb2_ports
;
87 xhci_common_hub_descriptor(xhci
, desc
, ports
);
88 desc
->bDescriptorType
= 0x29;
89 temp
= 1 + (ports
/ 8);
90 desc
->bDescLength
= 7 + 2 * temp
;
92 /* The Device Removable bits are reported on a byte granularity.
93 * If the port doesn't exist within that byte, the bit is set to 0.
95 memset(port_removable
, 0, sizeof(port_removable
));
96 for (i
= 0; i
< ports
; i
++) {
97 portsc
= xhci_readl(xhci
, xhci
->usb3_ports
[i
]);
98 /* If a device is removable, PORTSC reports a 0, same as in the
99 * hub descriptor DeviceRemovable bits.
101 if (portsc
& PORT_DEV_REMOVE
)
102 /* This math is hairy because bit 0 of DeviceRemovable
103 * is reserved, and bit 1 is for port 1, etc.
105 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
108 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
109 * ports on it. The USB 2.0 specification says that there are two
110 * variable length fields at the end of the hub descriptor:
111 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
112 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
113 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
114 * 0xFF, so we initialize the both arrays (DeviceRemovable and
115 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
116 * set of ports that actually exist.
118 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
119 sizeof(desc
->u
.hs
.DeviceRemovable
));
120 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
121 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
123 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
124 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
128 /* Fill in the USB 3.0 roothub descriptor */
129 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
130 struct usb_hub_descriptor
*desc
)
137 ports
= xhci
->num_usb3_ports
;
138 xhci_common_hub_descriptor(xhci
, desc
, ports
);
139 desc
->bDescriptorType
= 0x2a;
140 desc
->bDescLength
= 12;
142 /* header decode latency should be zero for roothubs,
143 * see section 4.23.5.2.
145 desc
->u
.ss
.bHubHdrDecLat
= 0;
146 desc
->u
.ss
.wHubDelay
= 0;
149 /* bit 0 is reserved, bit 1 is for port 1, etc. */
150 for (i
= 0; i
< ports
; i
++) {
151 portsc
= xhci_readl(xhci
, xhci
->usb3_ports
[i
]);
152 if (portsc
& PORT_DEV_REMOVE
)
153 port_removable
|= 1 << (i
+ 1);
155 memset(&desc
->u
.ss
.DeviceRemovable
,
156 (__force __u16
) cpu_to_le16(port_removable
),
160 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
161 struct usb_hub_descriptor
*desc
)
164 if (hcd
->speed
== HCD_USB3
)
165 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
167 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
171 static unsigned int xhci_port_speed(unsigned int port_status
)
173 if (DEV_LOWSPEED(port_status
))
174 return USB_PORT_STAT_LOW_SPEED
;
175 if (DEV_HIGHSPEED(port_status
))
176 return USB_PORT_STAT_HIGH_SPEED
;
178 * FIXME: Yes, we should check for full speed, but the core uses that as
179 * a default in portspeed() in usb/core/hub.c (which is the only place
180 * USB_PORT_STAT_*_SPEED is used).
186 * These bits are Read Only (RO) and should be saved and written to the
187 * registers: 0, 3, 10:13, 30
188 * connect status, over-current status, port speed, and device removable.
189 * connect status and port speed are also sticky - meaning they're in
190 * the AUX well and they aren't changed by a hot, warm, or cold reset.
192 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
194 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
195 * bits 5:8, 9, 14:15, 25:27
196 * link state, port power, port indicator state, "wake on" enable state
198 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
200 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
203 #define XHCI_PORT_RW1S ((1<<4))
205 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
206 * bits 1, 17, 18, 19, 20, 21, 22, 23
207 * port enable/disable, and
208 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
209 * over-current, reset, link state, and L1 change
211 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
213 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
216 #define XHCI_PORT_RW ((1<<16))
218 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
221 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
224 * Given a port state, this function returns a value that would result in the
225 * port being in the same state, if the value was written to the port status
227 * Save Read Only (RO) bits and save read/write bits where
228 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
229 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
231 u32
xhci_port_state_to_neutral(u32 state
)
233 /* Save read-only status and port state */
234 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
238 * find slot id based on port number.
239 * @port: The one-based port number from one of the two split roothubs.
241 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
246 enum usb_device_speed speed
;
249 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
252 speed
= xhci
->devs
[i
]->udev
->speed
;
253 if (((speed
== USB_SPEED_SUPER
) == (hcd
->speed
== HCD_USB3
))
254 && xhci
->devs
[i
]->fake_port
== port
) {
265 * It issues stop endpoint command for EP 0 to 30. And wait the last command
267 * suspend will set to 1, if suspend bit need to set in command.
269 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
271 struct xhci_virt_device
*virt_dev
;
272 struct xhci_command
*cmd
;
279 virt_dev
= xhci
->devs
[slot_id
];
280 cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
282 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
286 spin_lock_irqsave(&xhci
->lock
, flags
);
287 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
288 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
)
289 xhci_queue_stop_endpoint(xhci
, slot_id
, i
, suspend
);
291 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
292 list_add_tail(&cmd
->cmd_list
, &virt_dev
->cmd_list
);
293 xhci_queue_stop_endpoint(xhci
, slot_id
, 0, suspend
);
294 xhci_ring_cmd_db(xhci
);
295 spin_unlock_irqrestore(&xhci
->lock
, flags
);
297 /* Wait for last stop endpoint command to finish */
298 timeleft
= wait_for_completion_interruptible_timeout(
300 USB_CTRL_SET_TIMEOUT
);
302 xhci_warn(xhci
, "%s while waiting for stop endpoint command\n",
303 timeleft
== 0 ? "Timeout" : "Signal");
304 spin_lock_irqsave(&xhci
->lock
, flags
);
305 /* The timeout might have raced with the event ring handler, so
306 * only delete from the list if the item isn't poisoned.
308 if (cmd
->cmd_list
.next
!= LIST_POISON1
)
309 list_del(&cmd
->cmd_list
);
310 spin_unlock_irqrestore(&xhci
->lock
, flags
);
312 goto command_cleanup
;
316 xhci_free_command(xhci
, cmd
);
321 * Ring device, it rings the all doorbells unconditionally.
323 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
327 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++)
328 if (xhci
->devs
[slot_id
]->eps
[i
].ring
&&
329 xhci
->devs
[slot_id
]->eps
[i
].ring
->dequeue
)
330 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
335 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
336 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
338 /* Don't allow the USB core to disable SuperSpeed ports. */
339 if (hcd
->speed
== HCD_USB3
) {
340 xhci_dbg(xhci
, "Ignoring request to disable "
341 "SuperSpeed port.\n");
345 /* Write 1 to disable the port */
346 xhci_writel(xhci
, port_status
| PORT_PE
, addr
);
347 port_status
= xhci_readl(xhci
, addr
);
348 xhci_dbg(xhci
, "disable port, actual port %d status = 0x%x\n",
349 wIndex
, port_status
);
352 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
353 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
355 char *port_change_bit
;
359 case USB_PORT_FEAT_C_RESET
:
361 port_change_bit
= "reset";
363 case USB_PORT_FEAT_C_BH_PORT_RESET
:
365 port_change_bit
= "warm(BH) reset";
367 case USB_PORT_FEAT_C_CONNECTION
:
369 port_change_bit
= "connect";
371 case USB_PORT_FEAT_C_OVER_CURRENT
:
373 port_change_bit
= "over-current";
375 case USB_PORT_FEAT_C_ENABLE
:
377 port_change_bit
= "enable/disable";
379 case USB_PORT_FEAT_C_SUSPEND
:
381 port_change_bit
= "suspend/resume";
383 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
385 port_change_bit
= "link state";
388 /* Should never happen */
391 /* Change bits are all write 1 to clear */
392 xhci_writel(xhci
, port_status
| status
, addr
);
393 port_status
= xhci_readl(xhci
, addr
);
394 xhci_dbg(xhci
, "clear port %s change, actual port %d status = 0x%x\n",
395 port_change_bit
, wIndex
, port_status
);
398 static int xhci_get_ports(struct usb_hcd
*hcd
, __le32 __iomem
***port_array
)
401 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
403 if (hcd
->speed
== HCD_USB3
) {
404 max_ports
= xhci
->num_usb3_ports
;
405 *port_array
= xhci
->usb3_ports
;
407 max_ports
= xhci
->num_usb2_ports
;
408 *port_array
= xhci
->usb2_ports
;
414 void xhci_set_link_state(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
415 int port_id
, u32 link_state
)
419 temp
= xhci_readl(xhci
, port_array
[port_id
]);
420 temp
= xhci_port_state_to_neutral(temp
);
421 temp
&= ~PORT_PLS_MASK
;
422 temp
|= PORT_LINK_STROBE
| link_state
;
423 xhci_writel(xhci
, temp
, port_array
[port_id
]);
426 /* Test and clear port RWC bit */
427 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
428 int port_id
, u32 port_bit
)
432 temp
= xhci_readl(xhci
, port_array
[port_id
]);
433 if (temp
& port_bit
) {
434 temp
= xhci_port_state_to_neutral(temp
);
436 xhci_writel(xhci
, temp
, port_array
[port_id
]);
440 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
441 u16 wIndex
, char *buf
, u16 wLength
)
443 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
448 __le32 __iomem
**port_array
;
450 struct xhci_bus_state
*bus_state
;
453 max_ports
= xhci_get_ports(hcd
, &port_array
);
454 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
456 spin_lock_irqsave(&xhci
->lock
, flags
);
459 /* No power source, over-current reported per port */
462 case GetHubDescriptor
:
463 /* Check to make sure userspace is asking for the USB 3.0 hub
464 * descriptor for the USB 3.0 roothub. If not, we stall the
465 * endpoint, like external hubs do.
467 if (hcd
->speed
== HCD_USB3
&&
468 (wLength
< USB_DT_SS_HUB_SIZE
||
469 wValue
!= (USB_DT_SS_HUB
<< 8))) {
470 xhci_dbg(xhci
, "Wrong hub descriptor type for "
471 "USB 3.0 roothub.\n");
474 xhci_hub_descriptor(hcd
, xhci
,
475 (struct usb_hub_descriptor
*) buf
);
477 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
478 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
481 if (hcd
->speed
!= HCD_USB3
)
484 memcpy(buf
, &usb_bos_descriptor
,
485 USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
);
486 temp
= xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params3
);
487 buf
[12] = HCS_U1_LATENCY(temp
);
488 put_unaligned_le16(HCS_U2_LATENCY(temp
), &buf
[13]);
490 spin_unlock_irqrestore(&xhci
->lock
, flags
);
491 return USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
493 if (!wIndex
|| wIndex
> max_ports
)
497 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
498 if (temp
== 0xffffffff) {
502 xhci_dbg(xhci
, "get port status, actual port %d status = 0x%x\n", wIndex
, temp
);
504 /* wPortChange bits */
506 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
508 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
509 if ((temp
& PORT_OCC
))
510 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
511 if ((temp
& PORT_RC
))
512 status
|= USB_PORT_STAT_C_RESET
<< 16;
514 if (hcd
->speed
== HCD_USB3
) {
515 if ((temp
& PORT_PLC
))
516 status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
517 if ((temp
& PORT_WRC
))
518 status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
521 if (hcd
->speed
!= HCD_USB3
) {
522 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
523 && (temp
& PORT_POWER
))
524 status
|= USB_PORT_STAT_SUSPEND
;
526 if ((temp
& PORT_PLS_MASK
) == XDEV_RESUME
&&
527 !DEV_SUPERSPEED(temp
)) {
528 if ((temp
& PORT_RESET
) || !(temp
& PORT_PE
))
530 if (time_after_eq(jiffies
,
531 bus_state
->resume_done
[wIndex
])) {
532 xhci_dbg(xhci
, "Resume USB2 port %d\n",
534 bus_state
->resume_done
[wIndex
] = 0;
535 xhci_set_link_state(xhci
, port_array
, wIndex
,
537 xhci_dbg(xhci
, "set port %d resume\n",
539 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
542 xhci_dbg(xhci
, "slot_id is zero\n");
545 xhci_ring_device(xhci
, slot_id
);
546 bus_state
->port_c_suspend
|= 1 << wIndex
;
547 bus_state
->suspended_ports
&= ~(1 << wIndex
);
550 * The resume has been signaling for less than
551 * 20ms. Report the port status as SUSPEND,
552 * let the usbcore check port status again
553 * and clear resume signaling later.
555 status
|= USB_PORT_STAT_SUSPEND
;
558 if ((temp
& PORT_PLS_MASK
) == XDEV_U0
559 && (temp
& PORT_POWER
)
560 && (bus_state
->suspended_ports
& (1 << wIndex
))) {
561 bus_state
->suspended_ports
&= ~(1 << wIndex
);
562 if (hcd
->speed
!= HCD_USB3
)
563 bus_state
->port_c_suspend
|= 1 << wIndex
;
565 if (temp
& PORT_CONNECT
) {
566 status
|= USB_PORT_STAT_CONNECTION
;
567 status
|= xhci_port_speed(temp
);
570 status
|= USB_PORT_STAT_ENABLE
;
572 status
|= USB_PORT_STAT_OVERCURRENT
;
573 if (temp
& PORT_RESET
)
574 status
|= USB_PORT_STAT_RESET
;
575 if (temp
& PORT_POWER
) {
576 if (hcd
->speed
== HCD_USB3
)
577 status
|= USB_SS_PORT_STAT_POWER
;
579 status
|= USB_PORT_STAT_POWER
;
581 /* Port Link State */
582 if (hcd
->speed
== HCD_USB3
) {
583 /* resume state is a xHCI internal state.
584 * Do not report it to usb core.
586 if ((temp
& PORT_PLS_MASK
) != XDEV_RESUME
)
587 status
|= (temp
& PORT_PLS_MASK
);
589 if (bus_state
->port_c_suspend
& (1 << wIndex
))
590 status
|= 1 << USB_PORT_FEAT_C_SUSPEND
;
591 xhci_dbg(xhci
, "Get port status returned 0x%x\n", status
);
592 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
595 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
596 link_state
= (wIndex
& 0xff00) >> 3;
598 if (!wIndex
|| wIndex
> max_ports
)
601 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
602 if (temp
== 0xffffffff) {
606 temp
= xhci_port_state_to_neutral(temp
);
607 /* FIXME: What new port features do we need to support? */
609 case USB_PORT_FEAT_SUSPEND
:
610 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
611 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
612 /* Resume the port to U0 first */
613 xhci_set_link_state(xhci
, port_array
, wIndex
,
615 spin_unlock_irqrestore(&xhci
->lock
, flags
);
617 spin_lock_irqsave(&xhci
->lock
, flags
);
619 /* In spec software should not attempt to suspend
620 * a port unless the port reports that it is in the
621 * enabled (PED = ‘1’,PLS < ‘3’) state.
623 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
624 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
625 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
626 xhci_warn(xhci
, "USB core suspending device "
627 "not in U0/U1/U2.\n");
631 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
634 xhci_warn(xhci
, "slot_id is zero\n");
637 /* unlock to execute stop endpoint commands */
638 spin_unlock_irqrestore(&xhci
->lock
, flags
);
639 xhci_stop_device(xhci
, slot_id
, 1);
640 spin_lock_irqsave(&xhci
->lock
, flags
);
642 xhci_set_link_state(xhci
, port_array
, wIndex
, XDEV_U3
);
644 spin_unlock_irqrestore(&xhci
->lock
, flags
);
645 msleep(10); /* wait device to enter */
646 spin_lock_irqsave(&xhci
->lock
, flags
);
648 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
649 bus_state
->suspended_ports
|= 1 << wIndex
;
651 case USB_PORT_FEAT_LINK_STATE
:
652 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
653 /* Software should not attempt to set
654 * port link state above '5' (Rx.Detect) and the port
657 if ((temp
& PORT_PE
) == 0 ||
658 (link_state
> USB_SS_PORT_LS_RX_DETECT
)) {
659 xhci_warn(xhci
, "Cannot set link state.\n");
663 if (link_state
== USB_SS_PORT_LS_U3
) {
664 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
667 /* unlock to execute stop endpoint
669 spin_unlock_irqrestore(&xhci
->lock
,
671 xhci_stop_device(xhci
, slot_id
, 1);
672 spin_lock_irqsave(&xhci
->lock
, flags
);
676 xhci_set_link_state(xhci
, port_array
, wIndex
,
679 spin_unlock_irqrestore(&xhci
->lock
, flags
);
680 msleep(20); /* wait device to enter */
681 spin_lock_irqsave(&xhci
->lock
, flags
);
683 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
684 if (link_state
== USB_SS_PORT_LS_U3
)
685 bus_state
->suspended_ports
|= 1 << wIndex
;
687 case USB_PORT_FEAT_POWER
:
689 * Turn on ports, even if there isn't per-port switching.
690 * HC will report connect events even before this is set.
691 * However, khubd will ignore the roothub events until
692 * the roothub is registered.
694 xhci_writel(xhci
, temp
| PORT_POWER
,
697 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
698 xhci_dbg(xhci
, "set port power, actual port %d status = 0x%x\n", wIndex
, temp
);
700 case USB_PORT_FEAT_RESET
:
701 temp
= (temp
| PORT_RESET
);
702 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
704 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
705 xhci_dbg(xhci
, "set port reset, actual port %d status = 0x%x\n", wIndex
, temp
);
707 case USB_PORT_FEAT_BH_PORT_RESET
:
709 xhci_writel(xhci
, temp
, port_array
[wIndex
]);
711 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
716 /* unblock any posted writes */
717 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
719 case ClearPortFeature
:
720 if (!wIndex
|| wIndex
> max_ports
)
723 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
724 if (temp
== 0xffffffff) {
728 /* FIXME: What new port features do we need to support? */
729 temp
= xhci_port_state_to_neutral(temp
);
731 case USB_PORT_FEAT_SUSPEND
:
732 temp
= xhci_readl(xhci
, port_array
[wIndex
]);
733 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
734 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
735 if (temp
& PORT_RESET
)
737 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
738 if ((temp
& PORT_PE
) == 0)
741 xhci_set_link_state(xhci
, port_array
, wIndex
,
743 spin_unlock_irqrestore(&xhci
->lock
, flags
);
745 spin_lock_irqsave(&xhci
->lock
, flags
);
746 xhci_set_link_state(xhci
, port_array
, wIndex
,
749 bus_state
->port_c_suspend
|= 1 << wIndex
;
751 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
754 xhci_dbg(xhci
, "slot_id is zero\n");
757 xhci_ring_device(xhci
, slot_id
);
759 case USB_PORT_FEAT_C_SUSPEND
:
760 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
761 case USB_PORT_FEAT_C_RESET
:
762 case USB_PORT_FEAT_C_BH_PORT_RESET
:
763 case USB_PORT_FEAT_C_CONNECTION
:
764 case USB_PORT_FEAT_C_OVER_CURRENT
:
765 case USB_PORT_FEAT_C_ENABLE
:
766 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
767 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
768 port_array
[wIndex
], temp
);
770 case USB_PORT_FEAT_ENABLE
:
771 xhci_disable_port(hcd
, xhci
, wIndex
,
772 port_array
[wIndex
], temp
);
780 /* "stall" on error */
783 spin_unlock_irqrestore(&xhci
->lock
, flags
);
788 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
789 * Ports are 0-indexed from the HCD point of view,
790 * and 1-indexed from the USB core pointer of view.
792 * Note that the status change bits will be cleared as soon as a port status
793 * change event is generated, so we use the saved status from that event.
795 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
801 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
803 __le32 __iomem
**port_array
;
804 struct xhci_bus_state
*bus_state
;
806 max_ports
= xhci_get_ports(hcd
, &port_array
);
807 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
809 /* Initial status is no changes */
810 retval
= (max_ports
+ 8) / 8;
811 memset(buf
, 0, retval
);
814 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
;
816 spin_lock_irqsave(&xhci
->lock
, flags
);
817 /* For each port, did anything change? If so, set that bit in buf. */
818 for (i
= 0; i
< max_ports
; i
++) {
819 temp
= xhci_readl(xhci
, port_array
[i
]);
820 if (temp
== 0xffffffff) {
824 if ((temp
& mask
) != 0 ||
825 (bus_state
->port_c_suspend
& 1 << i
) ||
826 (bus_state
->resume_done
[i
] && time_after_eq(
827 jiffies
, bus_state
->resume_done
[i
]))) {
828 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
832 spin_unlock_irqrestore(&xhci
->lock
, flags
);
833 return status
? retval
: 0;
838 int xhci_bus_suspend(struct usb_hcd
*hcd
)
840 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
841 int max_ports
, port_index
;
842 __le32 __iomem
**port_array
;
843 struct xhci_bus_state
*bus_state
;
846 max_ports
= xhci_get_ports(hcd
, &port_array
);
847 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
849 spin_lock_irqsave(&xhci
->lock
, flags
);
851 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
852 port_index
= max_ports
;
853 while (port_index
--) {
854 if (bus_state
->resume_done
[port_index
] != 0) {
855 spin_unlock_irqrestore(&xhci
->lock
, flags
);
856 xhci_dbg(xhci
, "suspend failed because "
857 "port %d is resuming\n",
864 port_index
= max_ports
;
865 bus_state
->bus_suspended
= 0;
866 while (port_index
--) {
867 /* suspend the port if the port is not suspended */
871 t1
= xhci_readl(xhci
, port_array
[port_index
]);
872 t2
= xhci_port_state_to_neutral(t1
);
874 if ((t1
& PORT_PE
) && !(t1
& PORT_PLS_MASK
)) {
875 xhci_dbg(xhci
, "port %d not suspended\n", port_index
);
876 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
879 spin_unlock_irqrestore(&xhci
->lock
, flags
);
880 xhci_stop_device(xhci
, slot_id
, 1);
881 spin_lock_irqsave(&xhci
->lock
, flags
);
883 t2
&= ~PORT_PLS_MASK
;
884 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
885 set_bit(port_index
, &bus_state
->bus_suspended
);
887 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
888 if (t1
& PORT_CONNECT
) {
889 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
890 t2
&= ~PORT_WKCONN_E
;
892 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
893 t2
&= ~PORT_WKDISC_E
;
896 t2
&= ~PORT_WAKE_BITS
;
898 t1
= xhci_port_state_to_neutral(t1
);
900 xhci_writel(xhci
, t2
, port_array
[port_index
]);
902 if (hcd
->speed
!= HCD_USB3
) {
903 /* enable remote wake up for USB 2.0 */
904 __le32 __iomem
*addr
;
907 /* Add one to the port status register address to get
908 * the port power control register address.
910 addr
= port_array
[port_index
] + 1;
911 tmp
= xhci_readl(xhci
, addr
);
913 xhci_writel(xhci
, tmp
, addr
);
916 hcd
->state
= HC_STATE_SUSPENDED
;
917 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
918 spin_unlock_irqrestore(&xhci
->lock
, flags
);
922 int xhci_bus_resume(struct usb_hcd
*hcd
)
924 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
925 int max_ports
, port_index
;
926 __le32 __iomem
**port_array
;
927 struct xhci_bus_state
*bus_state
;
931 max_ports
= xhci_get_ports(hcd
, &port_array
);
932 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
934 if (time_before(jiffies
, bus_state
->next_statechange
))
937 spin_lock_irqsave(&xhci
->lock
, flags
);
938 if (!HCD_HW_ACCESSIBLE(hcd
)) {
939 spin_unlock_irqrestore(&xhci
->lock
, flags
);
944 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
946 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
948 port_index
= max_ports
;
949 while (port_index
--) {
950 /* Check whether need resume ports. If needed
951 resume port and disable remote wakeup */
955 temp
= xhci_readl(xhci
, port_array
[port_index
]);
956 if (DEV_SUPERSPEED(temp
))
957 temp
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
959 temp
&= ~(PORT_RWC_BITS
| PORT_WAKE_BITS
);
960 if (test_bit(port_index
, &bus_state
->bus_suspended
) &&
961 (temp
& PORT_PLS_MASK
)) {
962 if (DEV_SUPERSPEED(temp
)) {
963 xhci_set_link_state(xhci
, port_array
,
964 port_index
, XDEV_U0
);
966 xhci_set_link_state(xhci
, port_array
,
967 port_index
, XDEV_RESUME
);
969 spin_unlock_irqrestore(&xhci
->lock
, flags
);
971 spin_lock_irqsave(&xhci
->lock
, flags
);
973 xhci_set_link_state(xhci
, port_array
,
974 port_index
, XDEV_U0
);
976 /* wait for the port to enter U0 and report port link
979 spin_unlock_irqrestore(&xhci
->lock
, flags
);
981 spin_lock_irqsave(&xhci
->lock
, flags
);
984 xhci_test_and_clear_bit(xhci
, port_array
, port_index
,
987 slot_id
= xhci_find_slot_id_by_port(hcd
,
988 xhci
, port_index
+ 1);
990 xhci_ring_device(xhci
, slot_id
);
992 xhci_writel(xhci
, temp
, port_array
[port_index
]);
994 if (hcd
->speed
!= HCD_USB3
) {
995 /* disable remote wake up for USB 2.0 */
996 __le32 __iomem
*addr
;
999 /* Add one to the port status register address to get
1000 * the port power control register address.
1002 addr
= port_array
[port_index
] + 1;
1003 tmp
= xhci_readl(xhci
, addr
);
1005 xhci_writel(xhci
, tmp
, addr
);
1009 (void) xhci_readl(xhci
, &xhci
->op_regs
->command
);
1011 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1012 /* re-enable irqs */
1013 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1015 xhci_writel(xhci
, temp
, &xhci
->op_regs
->command
);
1016 temp
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1018 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1022 #endif /* CONFIG_PM */