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xfrm: Fix NULL pointer dereference in xfrm_input when skb_dst_force clears the dst_entry.
[linux/fpc-iii.git] / drivers / iio / adc / cpcap-adc.c
blob9ad60421d360539db31636b65baf42fe4bf67824
1 /*
2 * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
3 *
4 * Rewritten for Linux IIO framework with some code based on
5 * earlier driver found in the Motorola Linux kernel:
6 *
7 * Copyright (C) 2009-2010 Motorola, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/delay.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regmap.h>
30
31 #include <linux/iio/buffer.h>
32 #include <linux/iio/driver.h>
33 #include <linux/iio/iio.h>
34 #include <linux/iio/kfifo_buf.h>
35 #include <linux/mfd/motorola-cpcap.h>
36
37 /* Register CPCAP_REG_ADCC1 bits */
38 #define CPCAP_BIT_ADEN_AUTO_CLR BIT(15) /* Currently unused */
39 #define CPCAP_BIT_CAL_MODE BIT(14) /* Set with BIT_RAND0 */
40 #define CPCAP_BIT_ADC_CLK_SEL1 BIT(13) /* Currently unused */
41 #define CPCAP_BIT_ADC_CLK_SEL0 BIT(12) /* Currently unused */
42 #define CPCAP_BIT_ATOX BIT(11)
43 #define CPCAP_BIT_ATO3 BIT(10)
44 #define CPCAP_BIT_ATO2 BIT(9)
45 #define CPCAP_BIT_ATO1 BIT(8)
46 #define CPCAP_BIT_ATO0 BIT(7)
47 #define CPCAP_BIT_ADA2 BIT(6)
48 #define CPCAP_BIT_ADA1 BIT(5)
49 #define CPCAP_BIT_ADA0 BIT(4)
50 #define CPCAP_BIT_AD_SEL1 BIT(3) /* Set for bank1 */
51 #define CPCAP_BIT_RAND1 BIT(2) /* Set for channel 16 & 17 */
52 #define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */
53 #define CPCAP_BIT_ADEN BIT(0) /* Currently unused */
54
55 #define CPCAP_REG_ADCC1_DEFAULTS (CPCAP_BIT_ADEN_AUTO_CLR | \
56 CPCAP_BIT_ADC_CLK_SEL0 | \
57 CPCAP_BIT_RAND1)
58
59 /* Register CPCAP_REG_ADCC2 bits */
60 #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */
61 #define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */
62 #define CPCAP_BIT_ADTRIG_ONESHOT BIT(13) /* Set for !TIMING_IMM */
63 #define CPCAP_BIT_ASC BIT(12) /* Set for TIMING_IMM */
64 #define CPCAP_BIT_ATOX_PS_FACTOR BIT(11)
65 #define CPCAP_BIT_ADC_PS_FACTOR1 BIT(10)
66 #define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9)
67 #define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */
68 #define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */
69 #define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Bias for AD0_BATTDETB */
70 #define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */
71 #define CPCAP_BIT_LIADC BIT(4) /* Currently unused */
72 #define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */
73 #define CPCAP_BIT_TS_M2 BIT(2) /* Currently unused */
74 #define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */
75 #define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */
76
77 #define CPCAP_REG_ADCC2_DEFAULTS (CPCAP_BIT_AD4_SELECT | \
78 CPCAP_BIT_ADTRIG_DIS | \
79 CPCAP_BIT_LIADC | \
80 CPCAP_BIT_TS_M2 | \
81 CPCAP_BIT_TS_M1)
82
83 #define CPCAP_MAX_TEMP_LVL 27
84 #define CPCAP_FOUR_POINT_TWO_ADC 801
85 #define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530
86 #define ST_ADC_CAL_CHRGI_LOW_THRESHOLD 494
87 #define ST_ADC_CAL_BATTI_HIGH_THRESHOLD 530
88 #define ST_ADC_CAL_BATTI_LOW_THRESHOLD 494
89 #define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3
90
91 #define CPCAP_ADC_MAX_RETRIES 5 /* Calibration */
92
93 /**
94 * struct cpcap_adc_ato - timing settings for cpcap adc
95 *
96 * Unfortunately no cpcap documentation available, please document when
97 * using these.
98 */
99 struct cpcap_adc_ato {
100 unsigned short ato_in;
101 unsigned short atox_in;
102 unsigned short adc_ps_factor_in;
103 unsigned short atox_ps_factor_in;
104 unsigned short ato_out;
105 unsigned short atox_out;
106 unsigned short adc_ps_factor_out;
107 unsigned short atox_ps_factor_out;
108 };
109
110 /**
111 * struct cpcap-adc - cpcap adc device driver data
112 * @reg: cpcap regmap
113 * @dev: struct device
114 * @vendor: cpcap vendor
115 * @irq: interrupt
116 * @lock: mutex
117 * @ato: request timings
118 * @wq_data_avail: work queue
119 * @done: work done
120 */
121 struct cpcap_adc {
122 struct regmap *reg;
123 struct device *dev;
124 u16 vendor;
125 int irq;
126 struct mutex lock; /* ADC register access lock */
127 const struct cpcap_adc_ato *ato;
128 wait_queue_head_t wq_data_avail;
129 bool done;
130 };
131
132 /**
133 * enum cpcap_adc_channel - cpcap adc channels
134 */
135 enum cpcap_adc_channel {
136 /* Bank0 channels */
137 CPCAP_ADC_AD0, /* Battery temperature */
138 CPCAP_ADC_BATTP, /* Battery voltage */
139 CPCAP_ADC_VBUS, /* USB VBUS voltage */
140 CPCAP_ADC_AD3, /* Die temperature when charging */
141 CPCAP_ADC_BPLUS_AD4, /* Another battery or system voltage */
142 CPCAP_ADC_CHG_ISENSE, /* Calibrated charge current */
143 CPCAP_ADC_BATTI, /* Calibrated system current */
144 CPCAP_ADC_USB_ID, /* USB OTG ID, unused on droid 4? */
145
146 /* Bank1 channels */
147 CPCAP_ADC_AD8, /* Seems unused */
148 CPCAP_ADC_AD9, /* Seems unused */
149 CPCAP_ADC_LICELL, /* Maybe system voltage? Always 3V */
150 CPCAP_ADC_HV_BATTP, /* Another battery detection? */
151 CPCAP_ADC_TSX1_AD12, /* Seems unused, for touchscreen? */
152 CPCAP_ADC_TSX2_AD13, /* Seems unused, for touchscreen? */
153 CPCAP_ADC_TSY1_AD14, /* Seems unused, for touchscreen? */
154 CPCAP_ADC_TSY2_AD15, /* Seems unused, for touchscreen? */
155
156 /* Remuxed channels using bank0 entries */
157 CPCAP_ADC_BATTP_PI16, /* Alternative mux mode for BATTP */
158 CPCAP_ADC_BATTI_PI17, /* Alternative mux mode for BATTI */
159
160 CPCAP_ADC_CHANNEL_NUM,
161 };
162
163 /**
164 * enum cpcap_adc_timing - cpcap adc timing options
165 *
166 * CPCAP_ADC_TIMING_IMM seems to be immediate with no timings.
167 * Please document when using.
168 */
169 enum cpcap_adc_timing {
170 CPCAP_ADC_TIMING_IMM,
171 CPCAP_ADC_TIMING_IN,
172 CPCAP_ADC_TIMING_OUT,
173 };
174
175 /**
176 * struct cpcap_adc_phasing_tbl - cpcap phasing table
177 * @offset: offset in the phasing table
178 * @multiplier: multiplier in the phasing table
179 * @divider: divider in the phasing table
180 * @min: minimum value
181 * @max: maximum value
182 */
183 struct cpcap_adc_phasing_tbl {
184 short offset;
185 unsigned short multiplier;
186 unsigned short divider;
187 short min;
188 short max;
189 };
190
191 /**
192 * struct cpcap_adc_conversion_tbl - cpcap conversion table
193 * @conv_type: conversion type
194 * @align_offset: align offset
195 * @conv_offset: conversion offset
196 * @cal_offset: calibration offset
197 * @multiplier: conversion multiplier
198 * @divider: conversion divider
199 */
200 struct cpcap_adc_conversion_tbl {
201 enum iio_chan_info_enum conv_type;
202 int align_offset;
203 int conv_offset;
204 int cal_offset;
205 int multiplier;
206 int divider;
207 };
208
209 /**
210 * struct cpcap_adc_request - cpcap adc request
211 * @channel: request channel
212 * @phase_tbl: channel phasing table
213 * @conv_tbl: channel conversion table
214 * @bank_index: channel index within the bank
215 * @timing: timing settings
216 * @result: result
217 */
218 struct cpcap_adc_request {
219 int channel;
220 const struct cpcap_adc_phasing_tbl *phase_tbl;
221 const struct cpcap_adc_conversion_tbl *conv_tbl;
222 int bank_index;
223 enum cpcap_adc_timing timing;
224 int result;
225 };
226
227 /* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */
228 static const struct cpcap_adc_phasing_tbl bank_phasing[] = {
229 /* Bank0 */
230 [CPCAP_ADC_AD0] = {0, 0x80, 0x80, 0, 1023},
231 [CPCAP_ADC_BATTP] = {0, 0x80, 0x80, 0, 1023},
232 [CPCAP_ADC_VBUS] = {0, 0x80, 0x80, 0, 1023},
233 [CPCAP_ADC_AD3] = {0, 0x80, 0x80, 0, 1023},
234 [CPCAP_ADC_BPLUS_AD4] = {0, 0x80, 0x80, 0, 1023},
235 [CPCAP_ADC_CHG_ISENSE] = {0, 0x80, 0x80, -512, 511},
236 [CPCAP_ADC_BATTI] = {0, 0x80, 0x80, -512, 511},
237 [CPCAP_ADC_USB_ID] = {0, 0x80, 0x80, 0, 1023},
238
239 /* Bank1 */
240 [CPCAP_ADC_AD8] = {0, 0x80, 0x80, 0, 1023},
241 [CPCAP_ADC_AD9] = {0, 0x80, 0x80, 0, 1023},
242 [CPCAP_ADC_LICELL] = {0, 0x80, 0x80, 0, 1023},
243 [CPCAP_ADC_HV_BATTP] = {0, 0x80, 0x80, 0, 1023},
244 [CPCAP_ADC_TSX1_AD12] = {0, 0x80, 0x80, 0, 1023},
245 [CPCAP_ADC_TSX2_AD13] = {0, 0x80, 0x80, 0, 1023},
246 [CPCAP_ADC_TSY1_AD14] = {0, 0x80, 0x80, 0, 1023},
247 [CPCAP_ADC_TSY2_AD15] = {0, 0x80, 0x80, 0, 1023},
248 };
249
250 /*
251 * Conversion table for channels. Updated during init based on calibration.
252 * Here too channels 16 & 17 use BATTP and BATTI.
253 */
254 static struct cpcap_adc_conversion_tbl bank_conversion[] = {
255 /* Bank0 */
256 [CPCAP_ADC_AD0] = {
257 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
258 },
259 [CPCAP_ADC_BATTP] = {
260 IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
261 },
262 [CPCAP_ADC_VBUS] = {
263 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 10000, 1023,
264 },
265 [CPCAP_ADC_AD3] = {
266 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1,
267 },
268 [CPCAP_ADC_BPLUS_AD4] = {
269 IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023,
270 },
271 [CPCAP_ADC_CHG_ISENSE] = {
272 IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
273 },
274 [CPCAP_ADC_BATTI] = {
275 IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023,
276 },
277 [CPCAP_ADC_USB_ID] = {
278 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
279 },
280
281 /* Bank1 */
282 [CPCAP_ADC_AD8] = {
283 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
284 },
285 [CPCAP_ADC_AD9] = {
286 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
287 },
288 [CPCAP_ADC_LICELL] = {
289 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 3400, 1023,
290 },
291 [CPCAP_ADC_HV_BATTP] = {
292 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
293 },
294 [CPCAP_ADC_TSX1_AD12] = {
295 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
296 },
297 [CPCAP_ADC_TSX2_AD13] = {
298 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
299 },
300 [CPCAP_ADC_TSY1_AD14] = {
301 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
302 },
303 [CPCAP_ADC_TSY2_AD15] = {
304 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1,
305 },
306 };
307
308 /*
309 * Temperature lookup table of register values to milliCelcius.
310 * REVISIT: Check the duplicate 0x3ff entry in a freezer
311 */
312 static const int temp_map[CPCAP_MAX_TEMP_LVL][2] = {
313 { 0x03ff, -40000 },
314 { 0x03ff, -35000 },
315 { 0x03ef, -30000 },
316 { 0x03b2, -25000 },
317 { 0x036c, -20000 },
318 { 0x0320, -15000 },
319 { 0x02d0, -10000 },
320 { 0x027f, -5000 },
321 { 0x022f, 0 },
322 { 0x01e4, 5000 },
323 { 0x019f, 10000 },
324 { 0x0161, 15000 },
325 { 0x012b, 20000 },
326 { 0x00fc, 25000 },
327 { 0x00d4, 30000 },
328 { 0x00b2, 35000 },
329 { 0x0095, 40000 },
330 { 0x007d, 45000 },
331 { 0x0069, 50000 },
332 { 0x0059, 55000 },
333 { 0x004b, 60000 },
334 { 0x003f, 65000 },
335 { 0x0036, 70000 },
336 { 0x002e, 75000 },
337 { 0x0027, 80000 },
338 { 0x0022, 85000 },
339 { 0x001d, 90000 },
340 };
341
342 #define CPCAP_CHAN(_type, _index, _address, _datasheet_name) { \
343 .type = (_type), \
344 .address = (_address), \
345 .indexed = 1, \
346 .channel = (_index), \
347 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
348 BIT(IIO_CHAN_INFO_PROCESSED), \
349 .scan_index = (_index), \
350 .scan_type = { \
351 .sign = 'u', \
352 .realbits = 10, \
353 .storagebits = 16, \
354 .endianness = IIO_CPU, \
355 }, \
356 .datasheet_name = (_datasheet_name), \
357 }
358
359 /*
360 * The datasheet names are from Motorola mapphone Linux kernel except
361 * for the last two which might be uncalibrated charge voltage and
362 * current.
363 */
364 static const struct iio_chan_spec cpcap_adc_channels[] = {
365 /* Bank0 */
366 CPCAP_CHAN(IIO_TEMP, 0, CPCAP_REG_ADCD0, "battdetb"),
367 CPCAP_CHAN(IIO_VOLTAGE, 1, CPCAP_REG_ADCD1, "battp"),
368 CPCAP_CHAN(IIO_VOLTAGE, 2, CPCAP_REG_ADCD2, "vbus"),
369 CPCAP_CHAN(IIO_TEMP, 3, CPCAP_REG_ADCD3, "ad3"),
370 CPCAP_CHAN(IIO_VOLTAGE, 4, CPCAP_REG_ADCD4, "ad4"),
371 CPCAP_CHAN(IIO_CURRENT, 5, CPCAP_REG_ADCD5, "chg_isense"),
372 CPCAP_CHAN(IIO_CURRENT, 6, CPCAP_REG_ADCD6, "batti"),
373 CPCAP_CHAN(IIO_VOLTAGE, 7, CPCAP_REG_ADCD7, "usb_id"),
374
375 /* Bank1 */
376 CPCAP_CHAN(IIO_CURRENT, 8, CPCAP_REG_ADCD0, "ad8"),
377 CPCAP_CHAN(IIO_VOLTAGE, 9, CPCAP_REG_ADCD1, "ad9"),
378 CPCAP_CHAN(IIO_VOLTAGE, 10, CPCAP_REG_ADCD2, "licell"),
379 CPCAP_CHAN(IIO_VOLTAGE, 11, CPCAP_REG_ADCD3, "hv_battp"),
380 CPCAP_CHAN(IIO_VOLTAGE, 12, CPCAP_REG_ADCD4, "tsx1_ad12"),
381 CPCAP_CHAN(IIO_VOLTAGE, 13, CPCAP_REG_ADCD5, "tsx2_ad13"),
382 CPCAP_CHAN(IIO_VOLTAGE, 14, CPCAP_REG_ADCD6, "tsy1_ad14"),
383 CPCAP_CHAN(IIO_VOLTAGE, 15, CPCAP_REG_ADCD7, "tsy2_ad15"),
384
385 /* There are two registers with multiplexed functionality */
386 CPCAP_CHAN(IIO_VOLTAGE, 16, CPCAP_REG_ADCD0, "chg_vsense"),
387 CPCAP_CHAN(IIO_CURRENT, 17, CPCAP_REG_ADCD1, "batti2"),
388 };
389
390 static irqreturn_t cpcap_adc_irq_thread(int irq, void *data)
391 {
392 struct iio_dev *indio_dev = data;
393 struct cpcap_adc *ddata = iio_priv(indio_dev);
394 int error;
395
396 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
397 CPCAP_BIT_ADTRIG_DIS,
398 CPCAP_BIT_ADTRIG_DIS);
399 if (error)
400 return IRQ_NONE;
401
402 ddata->done = true;
403 wake_up_interruptible(&ddata->wq_data_avail);
404
405 return IRQ_HANDLED;
406 }
407
408 /* ADC calibration functions */
409 static void cpcap_adc_setup_calibrate(struct cpcap_adc *ddata,
410 enum cpcap_adc_channel chan)
411 {
412 unsigned int value = 0;
413 unsigned long timeout = jiffies + msecs_to_jiffies(3000);
414 int error;
415
416 if ((chan != CPCAP_ADC_CHG_ISENSE) &&
417 (chan != CPCAP_ADC_BATTI))
418 return;
419
420 value |= CPCAP_BIT_CAL_MODE | CPCAP_BIT_RAND0;
421 value |= ((chan << 4) &
422 (CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | CPCAP_BIT_ADA0));
423
424 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
425 CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
426 CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
427 CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
428 CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
429 CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
430 CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
431 value);
432 if (error)
433 return;
434
435 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
436 CPCAP_BIT_ATOX_PS_FACTOR |
437 CPCAP_BIT_ADC_PS_FACTOR1 |
438 CPCAP_BIT_ADC_PS_FACTOR0,
439 0);
440 if (error)
441 return;
442
443 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
444 CPCAP_BIT_ADTRIG_DIS,
445 CPCAP_BIT_ADTRIG_DIS);
446 if (error)
447 return;
448
449 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
450 CPCAP_BIT_ASC,
451 CPCAP_BIT_ASC);
452 if (error)
453 return;
454
455 do {
456 schedule_timeout_uninterruptible(1);
457 error = regmap_read(ddata->reg, CPCAP_REG_ADCC2, &value);
458 if (error)
459 return;
460 } while ((value & CPCAP_BIT_ASC) && time_before(jiffies, timeout));
461
462 if (value & CPCAP_BIT_ASC)
463 dev_err(ddata->dev,
464 "Timeout waiting for calibration to complete\n");
465
466 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
467 CPCAP_BIT_CAL_MODE, 0);
468 if (error)
469 return;
470 }
471
472 static int cpcap_adc_calibrate_one(struct cpcap_adc *ddata,
473 int channel,
474 u16 calibration_register,
475 int lower_threshold,
476 int upper_threshold)
477 {
478 unsigned int calibration_data[2];
479 unsigned short cal_data_diff;
480 int i, error;
481
482 for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
483 calibration_data[0] = 0;
484 calibration_data[1] = 0;
485 cal_data_diff = 0;
486 cpcap_adc_setup_calibrate(ddata, channel);
487 error = regmap_read(ddata->reg, calibration_register,
488 &calibration_data[0]);
489 if (error)
490 return error;
491 cpcap_adc_setup_calibrate(ddata, channel);
492 error = regmap_read(ddata->reg, calibration_register,
493 &calibration_data[1]);
494 if (error)
495 return error;
496
497 if (calibration_data[0] > calibration_data[1])
498 cal_data_diff =
499 calibration_data[0] - calibration_data[1];
500 else
501 cal_data_diff =
502 calibration_data[1] - calibration_data[0];
503
504 if (((calibration_data[1] >= lower_threshold) &&
505 (calibration_data[1] <= upper_threshold) &&
506 (cal_data_diff <= ST_ADC_CALIBRATE_DIFF_THRESHOLD)) ||
507 (ddata->vendor == CPCAP_VENDOR_TI)) {
508 bank_conversion[channel].cal_offset =
509 ((short)calibration_data[1] * -1) + 512;
510 dev_dbg(ddata->dev, "ch%i calibration complete: %i\n",
511 channel, bank_conversion[channel].cal_offset);
512 break;
513 }
514 usleep_range(5000, 10000);
515 }
516
517 return 0;
518 }
519
520 static int cpcap_adc_calibrate(struct cpcap_adc *ddata)
521 {
522 int error;
523
524 error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_CHG_ISENSE,
525 CPCAP_REG_ADCAL1,
526 ST_ADC_CAL_CHRGI_LOW_THRESHOLD,
527 ST_ADC_CAL_CHRGI_HIGH_THRESHOLD);
528 if (error)
529 return error;
530
531 error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_BATTI,
532 CPCAP_REG_ADCAL2,
533 ST_ADC_CAL_BATTI_LOW_THRESHOLD,
534 ST_ADC_CAL_BATTI_HIGH_THRESHOLD);
535 if (error)
536 return error;
537
538 return 0;
539 }
540
541 /* ADC setup, read and scale functions */
542 static void cpcap_adc_setup_bank(struct cpcap_adc *ddata,
543 struct cpcap_adc_request *req)
544 {
545 const struct cpcap_adc_ato *ato = ddata->ato;
546 unsigned short value1 = 0;
547 unsigned short value2 = 0;
548 int error;
549
550 if (!ato)
551 return;
552
553 switch (req->channel) {
554 case CPCAP_ADC_AD0:
555 value2 |= CPCAP_BIT_THERMBIAS_EN;
556 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
557 CPCAP_BIT_THERMBIAS_EN,
558 value2);
559 if (error)
560 return;
561 usleep_range(800, 1000);
562 break;
563 case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
564 value1 |= CPCAP_BIT_AD_SEL1;
565 break;
566 case CPCAP_ADC_BATTP_PI16 ... CPCAP_ADC_BATTI_PI17:
567 value1 |= CPCAP_BIT_RAND1;
568 default:
569 break;
570 }
571
572 switch (req->timing) {
573 case CPCAP_ADC_TIMING_IN:
574 value1 |= ato->ato_in;
575 value1 |= ato->atox_in;
576 value2 |= ato->adc_ps_factor_in;
577 value2 |= ato->atox_ps_factor_in;
578 break;
579 case CPCAP_ADC_TIMING_OUT:
580 value1 |= ato->ato_out;
581 value1 |= ato->atox_out;
582 value2 |= ato->adc_ps_factor_out;
583 value2 |= ato->atox_ps_factor_out;
584 break;
585
586 case CPCAP_ADC_TIMING_IMM:
587 default:
588 break;
589 }
590
591 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
592 CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX |
593 CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 |
594 CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 |
595 CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 |
596 CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 |
597 CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0,
598 value1);
599 if (error)
600 return;
601
602 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
603 CPCAP_BIT_ATOX_PS_FACTOR |
604 CPCAP_BIT_ADC_PS_FACTOR1 |
605 CPCAP_BIT_ADC_PS_FACTOR0 |
606 CPCAP_BIT_THERMBIAS_EN,
607 value2);
608 if (error)
609 return;
610
611 if (req->timing == CPCAP_ADC_TIMING_IMM) {
612 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
613 CPCAP_BIT_ADTRIG_DIS,
614 CPCAP_BIT_ADTRIG_DIS);
615 if (error)
616 return;
617
618 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
619 CPCAP_BIT_ASC,
620 CPCAP_BIT_ASC);
621 if (error)
622 return;
623 } else {
624 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
625 CPCAP_BIT_ADTRIG_ONESHOT,
626 CPCAP_BIT_ADTRIG_ONESHOT);
627 if (error)
628 return;
629
630 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
631 CPCAP_BIT_ADTRIG_DIS, 0);
632 if (error)
633 return;
634 }
635 }
636
637 static int cpcap_adc_start_bank(struct cpcap_adc *ddata,
638 struct cpcap_adc_request *req)
639 {
640 int i, error;
641
642 req->timing = CPCAP_ADC_TIMING_IMM;
643 ddata->done = false;
644
645 for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) {
646 cpcap_adc_setup_bank(ddata, req);
647 error = wait_event_interruptible_timeout(ddata->wq_data_avail,
648 ddata->done,
649 msecs_to_jiffies(50));
650 if (error > 0)
651 return 0;
652
653 if (error == 0) {
654 error = -ETIMEDOUT;
655 continue;
656 }
657
658 if (error < 0)
659 return error;
660 }
661
662 return error;
663 }
664
665 static int cpcap_adc_stop_bank(struct cpcap_adc *ddata)
666 {
667 int error;
668
669 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1,
670 0xffff,
671 CPCAP_REG_ADCC1_DEFAULTS);
672 if (error)
673 return error;
674
675 return regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2,
676 0xffff,
677 CPCAP_REG_ADCC2_DEFAULTS);
678 }
679
680 static void cpcap_adc_phase(struct cpcap_adc_request *req)
681 {
682 const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
683 const struct cpcap_adc_phasing_tbl *phase_tbl = req->phase_tbl;
684 int index = req->channel;
685
686 /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
687 switch (req->channel) {
688 case CPCAP_ADC_BATTP:
689 case CPCAP_ADC_BATTP_PI16:
690 index = req->bank_index;
691 req->result -= phase_tbl[index].offset;
692 req->result -= CPCAP_FOUR_POINT_TWO_ADC;
693 req->result *= phase_tbl[index].multiplier;
694 if (phase_tbl[index].divider == 0)
695 return;
696 req->result /= phase_tbl[index].divider;
697 req->result += CPCAP_FOUR_POINT_TWO_ADC;
698 break;
699 case CPCAP_ADC_BATTI_PI17:
700 index = req->bank_index;
701 /* fallthrough */
702 default:
703 req->result += conv_tbl[index].cal_offset;
704 req->result += conv_tbl[index].align_offset;
705 req->result *= phase_tbl[index].multiplier;
706 if (phase_tbl[index].divider == 0)
707 return;
708 req->result /= phase_tbl[index].divider;
709 req->result += phase_tbl[index].offset;
710 break;
711 }
712
713 if (req->result < phase_tbl[index].min)
714 req->result = phase_tbl[index].min;
715 else if (req->result > phase_tbl[index].max)
716 req->result = phase_tbl[index].max;
717 }
718
719 /* Looks up temperatures in a table and calculates averages if needed */
720 static int cpcap_adc_table_to_millicelcius(unsigned short value)
721 {
722 int i, result = 0, alpha;
723
724 if (value <= temp_map[CPCAP_MAX_TEMP_LVL - 1][0])
725 return temp_map[CPCAP_MAX_TEMP_LVL - 1][1];
726
727 if (value >= temp_map[0][0])
728 return temp_map[0][1];
729
730 for (i = 0; i < CPCAP_MAX_TEMP_LVL - 1; i++) {
731 if ((value <= temp_map[i][0]) &&
732 (value >= temp_map[i + 1][0])) {
733 if (value == temp_map[i][0]) {
734 result = temp_map[i][1];
735 } else if (value == temp_map[i + 1][0]) {
736 result = temp_map[i + 1][1];
737 } else {
738 alpha = ((value - temp_map[i][0]) * 1000) /
739 (temp_map[i + 1][0] - temp_map[i][0]);
740
741 result = temp_map[i][1] +
742 ((alpha * (temp_map[i + 1][1] -
743 temp_map[i][1])) / 1000);
744 }
745 break;
746 }
747 }
748
749 return result;
750 }
751
752 static void cpcap_adc_convert(struct cpcap_adc_request *req)
753 {
754 const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl;
755 int index = req->channel;
756
757 /* Remuxed channels 16 and 17 use BATTP and BATTI entries */
758 switch (req->channel) {
759 case CPCAP_ADC_BATTP_PI16:
760 index = CPCAP_ADC_BATTP;
761 break;
762 case CPCAP_ADC_BATTI_PI17:
763 index = CPCAP_ADC_BATTI;
764 break;
765 default:
766 break;
767 }
768
769 /* No conversion for raw channels */
770 if (conv_tbl[index].conv_type == IIO_CHAN_INFO_RAW)
771 return;
772
773 /* Temperatures use a lookup table instead of conversion table */
774 if ((req->channel == CPCAP_ADC_AD0) ||
775 (req->channel == CPCAP_ADC_AD3)) {
776 req->result =
777 cpcap_adc_table_to_millicelcius(req->result);
778
779 return;
780 }
781
782 /* All processed channels use a conversion table */
783 req->result *= conv_tbl[index].multiplier;
784 if (conv_tbl[index].divider == 0)
785 return;
786 req->result /= conv_tbl[index].divider;
787 req->result += conv_tbl[index].conv_offset;
788 }
789
790 /*
791 * REVISIT: Check if timed sampling can use multiple channels at the
792 * same time. If not, replace channel_mask with just channel.
793 */
794 static int cpcap_adc_read_bank_scaled(struct cpcap_adc *ddata,
795 struct cpcap_adc_request *req)
796 {
797 int calibration_data, error, addr;
798
799 if (ddata->vendor == CPCAP_VENDOR_TI) {
800 error = regmap_read(ddata->reg, CPCAP_REG_ADCAL1,
801 &calibration_data);
802 if (error)
803 return error;
804 bank_conversion[CPCAP_ADC_CHG_ISENSE].cal_offset =
805 ((short)calibration_data * -1) + 512;
806
807 error = regmap_read(ddata->reg, CPCAP_REG_ADCAL2,
808 &calibration_data);
809 if (error)
810 return error;
811 bank_conversion[CPCAP_ADC_BATTI].cal_offset =
812 ((short)calibration_data * -1) + 512;
813 }
814
815 addr = CPCAP_REG_ADCD0 + req->bank_index * 4;
816
817 error = regmap_read(ddata->reg, addr, &req->result);
818 if (error)
819 return error;
820
821 req->result &= 0x3ff;
822 cpcap_adc_phase(req);
823 cpcap_adc_convert(req);
824
825 return 0;
826 }
827
828 static int cpcap_adc_init_request(struct cpcap_adc_request *req,
829 int channel)
830 {
831 req->channel = channel;
832 req->phase_tbl = bank_phasing;
833 req->conv_tbl = bank_conversion;
834
835 switch (channel) {
836 case CPCAP_ADC_AD0 ... CPCAP_ADC_USB_ID:
837 req->bank_index = channel;
838 break;
839 case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15:
840 req->bank_index = channel - 8;
841 break;
842 case CPCAP_ADC_BATTP_PI16:
843 req->bank_index = CPCAP_ADC_BATTP;
844 break;
845 case CPCAP_ADC_BATTI_PI17:
846 req->bank_index = CPCAP_ADC_BATTI;
847 break;
848 default:
849 return -EINVAL;
850 }
851
852 return 0;
853 }
854
855 static int cpcap_adc_read_st_die_temp(struct cpcap_adc *ddata,
856 int addr, int *val)
857 {
858 int error;
859
860 error = regmap_read(ddata->reg, addr, val);
861 if (error)
862 return error;
863
864 *val -= 282;
865 *val *= 114;
866 *val += 25000;
867
868 return 0;
869 }
870
871 static int cpcap_adc_read(struct iio_dev *indio_dev,
872 struct iio_chan_spec const *chan,
873 int *val, int *val2, long mask)
874 {
875 struct cpcap_adc *ddata = iio_priv(indio_dev);
876 struct cpcap_adc_request req;
877 int error;
878
879 error = cpcap_adc_init_request(&req, chan->channel);
880 if (error)
881 return error;
882
883 switch (mask) {
884 case IIO_CHAN_INFO_RAW:
885 mutex_lock(&ddata->lock);
886 error = cpcap_adc_start_bank(ddata, &req);
887 if (error)
888 goto err_unlock;
889 error = regmap_read(ddata->reg, chan->address, val);
890 if (error)
891 goto err_unlock;
892 error = cpcap_adc_stop_bank(ddata);
893 if (error)
894 goto err_unlock;
895 mutex_unlock(&ddata->lock);
896 break;
897 case IIO_CHAN_INFO_PROCESSED:
898 mutex_lock(&ddata->lock);
899 error = cpcap_adc_start_bank(ddata, &req);
900 if (error)
901 goto err_unlock;
902 if ((ddata->vendor == CPCAP_VENDOR_ST) &&
903 (chan->channel == CPCAP_ADC_AD3)) {
904 error = cpcap_adc_read_st_die_temp(ddata,
905 chan->address,
906 &req.result);
907 if (error)
908 goto err_unlock;
909 } else {
910 error = cpcap_adc_read_bank_scaled(ddata, &req);
911 if (error)
912 goto err_unlock;
913 }
914 error = cpcap_adc_stop_bank(ddata);
915 if (error)
916 goto err_unlock;
917 mutex_unlock(&ddata->lock);
918 *val = req.result;
919 break;
920 default:
921 return -EINVAL;
922 }
923
924 return IIO_VAL_INT;
925
926 err_unlock:
927 mutex_unlock(&ddata->lock);
928 dev_err(ddata->dev, "error reading ADC: %i\n", error);
929
930 return error;
931 }
932
933 static const struct iio_info cpcap_adc_info = {
934 .read_raw = &cpcap_adc_read,
935 };
936
937 /*
938 * Configuration for Motorola mapphone series such as droid 4.
939 * Copied from the Motorola mapphone kernel tree.
940 */
941 static const struct cpcap_adc_ato mapphone_adc = {
942 .ato_in = 0x0480,
943 .atox_in = 0,
944 .adc_ps_factor_in = 0x0200,
945 .atox_ps_factor_in = 0,
946 .ato_out = 0,
947 .atox_out = 0,
948 .adc_ps_factor_out = 0,
949 .atox_ps_factor_out = 0,
950 };
951
952 static const struct of_device_id cpcap_adc_id_table[] = {
953 {
954 .compatible = "motorola,cpcap-adc",
955 },
956 {
957 .compatible = "motorola,mapphone-cpcap-adc",
958 .data = &mapphone_adc,
959 },
960 { /* sentinel */ },
961 };
962 MODULE_DEVICE_TABLE(of, cpcap_adc_id_table);
963
964 static int cpcap_adc_probe(struct platform_device *pdev)
965 {
966 const struct of_device_id *match;
967 struct cpcap_adc *ddata;
968 struct iio_dev *indio_dev;
969 int error;
970
971 match = of_match_device(of_match_ptr(cpcap_adc_id_table),
972 &pdev->dev);
973 if (!match)
974 return -EINVAL;
975
976 if (!match->data) {
977 dev_err(&pdev->dev, "no configuration data found\n");
978
979 return -ENODEV;
980 }
981
982 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ddata));
983 if (!indio_dev) {
984 dev_err(&pdev->dev, "failed to allocate iio device\n");
985
986 return -ENOMEM;
987 }
988 ddata = iio_priv(indio_dev);
989 ddata->ato = match->data;
990 ddata->dev = &pdev->dev;
991
992 mutex_init(&ddata->lock);
993 init_waitqueue_head(&ddata->wq_data_avail);
994
995 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
996 indio_dev->dev.parent = &pdev->dev;
997 indio_dev->dev.of_node = pdev->dev.of_node;
998 indio_dev->channels = cpcap_adc_channels;
999 indio_dev->num_channels = ARRAY_SIZE(cpcap_adc_channels);
1000 indio_dev->name = dev_name(&pdev->dev);
1001 indio_dev->info = &cpcap_adc_info;
1002
1003 ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
1004 if (!ddata->reg)
1005 return -ENODEV;
1006
1007 error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor);
1008 if (error)
1009 return error;
1010
1011 platform_set_drvdata(pdev, indio_dev);
1012
1013 ddata->irq = platform_get_irq_byname(pdev, "adcdone");
1014 if (ddata->irq < 0)
1015 return -ENODEV;
1016
1017 error = devm_request_threaded_irq(&pdev->dev, ddata->irq, NULL,
1018 cpcap_adc_irq_thread,
1019 IRQF_TRIGGER_NONE,
1020 "cpcap-adc", indio_dev);
1021 if (error) {
1022 dev_err(&pdev->dev, "could not get irq: %i\n",
1023 error);
1024
1025 return error;
1026 }
1027
1028 error = cpcap_adc_calibrate(ddata);
1029 if (error)
1030 return error;
1031
1032 dev_info(&pdev->dev, "CPCAP ADC device probed\n");
1033
1034 return devm_iio_device_register(&pdev->dev, indio_dev);
1035 }
1036
1037 static struct platform_driver cpcap_adc_driver = {
1038 .driver = {
1039 .name = "cpcap_adc",
1040 .of_match_table = of_match_ptr(cpcap_adc_id_table),
1041 },
1042 .probe = cpcap_adc_probe,
1043 };
1044
1045 module_platform_driver(cpcap_adc_driver);
1046
1047 MODULE_ALIAS("platform:cpcap_adc");
1048 MODULE_DESCRIPTION("CPCAP ADC driver");
1049 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com");
1050 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support