| blob | a598ce9035f59aec49fa543266ba4dc238154893 |
1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs.
14 */
16 #include "armada-xp.dtsi"
18 / {
19 model = "Marvell Armada XP MV78260 SoC";
20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 };
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
32 cpu@0 {
33 device_type = "cpu";
34 compatible = "marvell,sheeva-v7";
35 reg = <0>;
36 clocks = <&cpuclk 0>;
37 };
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "marvell,sheeva-v7";
42 reg = <1>;
43 clocks = <&cpuclk 1>;
44 };
45 };
47 soc {
48 /*
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
51 * x4 only.
52 */
53 pcie-controller {
54 compatible = "marvell,armada-xp-pcie";
55 status = "disabled";
56 device_type = "pci";
58 #address-cells = <3>;
59 #size-cells = <2>;
61 bus-range = <0x00 0xff>;
63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
66 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
67 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
68 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
69 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
70 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
71 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
72 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
73 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
74 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
75 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
76 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
77 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
78 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
79 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
80 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
82 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
83 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
84 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
85 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
86 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
87 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
88 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
89 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
91 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
92 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
94 pcie@1,0 {
95 device_type = "pci";
96 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
97 reg = <0x0800 0 0 0 0>;
98 #address-cells = <3>;
99 #size-cells = <2>;
100 #interrupt-cells = <1>;
101 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
102 0x81000000 0 0 0x81000000 0x1 0 1 0>;
103 interrupt-map-mask = <0 0 0 0>;
104 interrupt-map = <0 0 0 0 &mpic 58>;
105 marvell,pcie-port = <0>;
106 marvell,pcie-lane = <0>;
107 clocks = <&gateclk 5>;
108 status = "disabled";
109 };
111 pcie@2,0 {
112 device_type = "pci";
113 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
114 reg = <0x1000 0 0 0 0>;
115 #address-cells = <3>;
116 #size-cells = <2>;
117 #interrupt-cells = <1>;
118 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
119 0x81000000 0 0 0x81000000 0x2 0 1 0>;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &mpic 59>;
122 marvell,pcie-port = <0>;
123 marvell,pcie-lane = <1>;
124 clocks = <&gateclk 6>;
125 status = "disabled";
126 };
128 pcie@3,0 {
129 device_type = "pci";
130 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
131 reg = <0x1800 0 0 0 0>;
132 #address-cells = <3>;
133 #size-cells = <2>;
134 #interrupt-cells = <1>;
135 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
136 0x81000000 0 0 0x81000000 0x3 0 1 0>;
137 interrupt-map-mask = <0 0 0 0>;
138 interrupt-map = <0 0 0 0 &mpic 60>;
139 marvell,pcie-port = <0>;
140 marvell,pcie-lane = <2>;
141 clocks = <&gateclk 7>;
142 status = "disabled";
143 };
145 pcie@4,0 {
146 device_type = "pci";
147 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
148 reg = <0x2000 0 0 0 0>;
149 #address-cells = <3>;
150 #size-cells = <2>;
151 #interrupt-cells = <1>;
152 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
153 0x81000000 0 0 0x81000000 0x4 0 1 0>;
154 interrupt-map-mask = <0 0 0 0>;
155 interrupt-map = <0 0 0 0 &mpic 61>;
156 marvell,pcie-port = <0>;
157 marvell,pcie-lane = <3>;
158 clocks = <&gateclk 8>;
159 status = "disabled";
160 };
162 pcie@5,0 {
163 device_type = "pci";
164 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
165 reg = <0x2800 0 0 0 0>;
166 #address-cells = <3>;
167 #size-cells = <2>;
168 #interrupt-cells = <1>;
169 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
170 0x81000000 0 0 0x81000000 0x5 0 1 0>;
171 interrupt-map-mask = <0 0 0 0>;
172 interrupt-map = <0 0 0 0 &mpic 62>;
173 marvell,pcie-port = <1>;
174 marvell,pcie-lane = <0>;
175 clocks = <&gateclk 9>;
176 status = "disabled";
177 };
179 pcie@6,0 {
180 device_type = "pci";
181 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
182 reg = <0x3000 0 0 0 0>;
183 #address-cells = <3>;
184 #size-cells = <2>;
185 #interrupt-cells = <1>;
186 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
187 0x81000000 0 0 0x81000000 0x6 0 1 0>;
188 interrupt-map-mask = <0 0 0 0>;
189 interrupt-map = <0 0 0 0 &mpic 63>;
190 marvell,pcie-port = <1>;
191 marvell,pcie-lane = <1>;
192 clocks = <&gateclk 10>;
193 status = "disabled";
194 };
196 pcie@7,0 {
197 device_type = "pci";
198 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
199 reg = <0x3800 0 0 0 0>;
200 #address-cells = <3>;
201 #size-cells = <2>;
202 #interrupt-cells = <1>;
203 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
204 0x81000000 0 0 0x81000000 0x7 0 1 0>;
205 interrupt-map-mask = <0 0 0 0>;
206 interrupt-map = <0 0 0 0 &mpic 64>;
207 marvell,pcie-port = <1>;
208 marvell,pcie-lane = <2>;
209 clocks = <&gateclk 11>;
210 status = "disabled";
211 };
213 pcie@8,0 {
214 device_type = "pci";
215 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
216 reg = <0x4000 0 0 0 0>;
217 #address-cells = <3>;
218 #size-cells = <2>;
219 #interrupt-cells = <1>;
220 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
221 0x81000000 0 0 0x81000000 0x8 0 1 0>;
222 interrupt-map-mask = <0 0 0 0>;
223 interrupt-map = <0 0 0 0 &mpic 65>;
224 marvell,pcie-port = <1>;
225 marvell,pcie-lane = <3>;
226 clocks = <&gateclk 12>;
227 status = "disabled";
228 };
230 pcie@9,0 {
231 device_type = "pci";
232 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
233 reg = <0x4800 0 0 0 0>;
234 #address-cells = <3>;
235 #size-cells = <2>;
236 #interrupt-cells = <1>;
237 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
238 0x81000000 0 0 0x81000000 0x9 0 1 0>;
239 interrupt-map-mask = <0 0 0 0>;
240 interrupt-map = <0 0 0 0 &mpic 99>;
241 marvell,pcie-port = <2>;
242 marvell,pcie-lane = <0>;
243 clocks = <&gateclk 26>;
244 status = "disabled";
245 };
246 };
248 internal-regs {
249 pinctrl {
250 compatible = "marvell,mv78260-pinctrl";
251 reg = <0x18000 0x38>;
253 sdio_pins: sdio-pins {
254 marvell,pins = "mpp30", "mpp31", "mpp32",
255 "mpp33", "mpp34", "mpp35";
256 marvell,function = "sd0";
257 };
258 };
260 gpio0: gpio@18100 {
261 compatible = "marvell,orion-gpio";
262 reg = <0x18100 0x40>;
263 ngpios = <32>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 interrupts = <82>, <83>, <84>, <85>;
269 };
271 gpio1: gpio@18140 {
272 compatible = "marvell,orion-gpio";
273 reg = <0x18140 0x40>;
274 ngpios = <32>;
275 gpio-controller;
276 #gpio-cells = <2>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
279 interrupts = <87>, <88>, <89>, <90>;
280 };
282 gpio2: gpio@18180 {
283 compatible = "marvell,orion-gpio";
284 reg = <0x18180 0x40>;
285 ngpios = <3>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 interrupts = <91>;
291 };
293 ethernet@34000 {
294 compatible = "marvell,armada-370-neta";
295 reg = <0x34000 0x4000>;
296 interrupts = <14>;
297 clocks = <&gateclk 1>;
298 status = "disabled";
299 };
300 };
301 };
302 };