1 /include/ "skeleton.dtsi"
4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC";
18 compatible = "marvell,pj4a", "marvell,sheeva-v7";
20 next-level-cache = <&l2>;
26 compatible = "marvell,tauros2-cache";
27 marvell,tauros2-cache-features = <0>;
31 compatible = "simple-bus";
34 interrupt-parent = <&intc>;
36 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
37 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
38 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
39 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
40 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
41 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
42 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
43 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
46 compatible = "marvell,orion-timer";
48 interrupt-parent = <&bridge_intc>;
49 interrupts = <1>, <2>;
50 clocks = <&core_clk 0>;
53 intc: main-interrupt-ctrl@20200 {
54 compatible = "marvell,orion-intc";
56 #interrupt-cells = <1>;
57 reg = <0x20200 0x10>, <0x20210 0x10>;
60 bridge_intc: bridge-interrupt-ctrl@20110 {
61 compatible = "marvell,orion-bridge-intc";
63 #interrupt-cells = <1>;
66 marvell,#interrupts = <5>;
69 core_clk: core-clocks@d0214 {
70 compatible = "marvell,dove-core-clock";
75 gate_clk: clock-gating-ctrl@d0038 {
76 compatible = "marvell,dove-gating-clock";
78 clocks = <&core_clk 0>;
82 thermal: thermal-diode@d001c {
83 compatible = "marvell,dove-thermal";
84 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
88 compatible = "ns16550a";
89 reg = <0x12000 0x100>;
92 clocks = <&core_clk 0>;
97 compatible = "ns16550a";
98 reg = <0x12100 0x100>;
101 clocks = <&core_clk 0>;
102 pinctrl-0 = <&pmx_uart1>;
103 pinctrl-names = "default";
107 uart2: serial@12200 {
108 compatible = "ns16550a";
109 reg = <0x12000 0x100>;
112 clocks = <&core_clk 0>;
116 uart3: serial@12300 {
117 compatible = "ns16550a";
118 reg = <0x12100 0x100>;
121 clocks = <&core_clk 0>;
125 gpio0: gpio-ctrl@d0400 {
126 compatible = "marvell,orion-gpio";
129 reg = <0xd0400 0x20>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 interrupts = <12>, <13>, <14>, <60>;
136 gpio1: gpio-ctrl@d0420 {
137 compatible = "marvell,orion-gpio";
140 reg = <0xd0420 0x20>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
147 gpio2: gpio-ctrl@e8400 {
148 compatible = "marvell,orion-gpio";
151 reg = <0xe8400 0x0c>;
155 pinctrl: pin-ctrl@d0200 {
156 compatible = "marvell,dove-pinctrl";
157 reg = <0xd0200 0x10>;
158 clocks = <&gate_clk 22>;
160 pmx_gpio_0: pmx-gpio-0 {
161 marvell,pins = "mpp0";
162 marvell,function = "gpio";
165 pmx_gpio_1: pmx-gpio-1 {
166 marvell,pins = "mpp1";
167 marvell,function = "gpio";
170 pmx_gpio_2: pmx-gpio-2 {
171 marvell,pins = "mpp2";
172 marvell,function = "gpio";
175 pmx_gpio_3: pmx-gpio-3 {
176 marvell,pins = "mpp3";
177 marvell,function = "gpio";
180 pmx_gpio_4: pmx-gpio-4 {
181 marvell,pins = "mpp4";
182 marvell,function = "gpio";
185 pmx_gpio_5: pmx-gpio-5 {
186 marvell,pins = "mpp5";
187 marvell,function = "gpio";
190 pmx_gpio_6: pmx-gpio-6 {
191 marvell,pins = "mpp6";
192 marvell,function = "gpio";
195 pmx_gpio_7: pmx-gpio-7 {
196 marvell,pins = "mpp7";
197 marvell,function = "gpio";
200 pmx_gpio_8: pmx-gpio-8 {
201 marvell,pins = "mpp8";
202 marvell,function = "gpio";
205 pmx_gpio_9: pmx-gpio-9 {
206 marvell,pins = "mpp9";
207 marvell,function = "gpio";
210 pmx_gpio_10: pmx-gpio-10 {
211 marvell,pins = "mpp10";
212 marvell,function = "gpio";
215 pmx_gpio_11: pmx-gpio-11 {
216 marvell,pins = "mpp11";
217 marvell,function = "gpio";
220 pmx_gpio_12: pmx-gpio-12 {
221 marvell,pins = "mpp12";
222 marvell,function = "gpio";
225 pmx_gpio_13: pmx-gpio-13 {
226 marvell,pins = "mpp13";
227 marvell,function = "gpio";
230 pmx_gpio_14: pmx-gpio-14 {
231 marvell,pins = "mpp14";
232 marvell,function = "gpio";
235 pmx_gpio_15: pmx-gpio-15 {
236 marvell,pins = "mpp15";
237 marvell,function = "gpio";
240 pmx_gpio_16: pmx-gpio-16 {
241 marvell,pins = "mpp16";
242 marvell,function = "gpio";
245 pmx_gpio_17: pmx-gpio-17 {
246 marvell,pins = "mpp17";
247 marvell,function = "gpio";
250 pmx_gpio_18: pmx-gpio-18 {
251 marvell,pins = "mpp18";
252 marvell,function = "gpio";
255 pmx_gpio_19: pmx-gpio-19 {
256 marvell,pins = "mpp19";
257 marvell,function = "gpio";
260 pmx_gpio_20: pmx-gpio-20 {
261 marvell,pins = "mpp20";
262 marvell,function = "gpio";
265 pmx_gpio_21: pmx-gpio-21 {
266 marvell,pins = "mpp21";
267 marvell,function = "gpio";
270 pmx_camera: pmx-camera {
271 marvell,pins = "mpp_camera";
272 marvell,function = "camera";
275 pmx_camera_gpio: pmx-camera-gpio {
276 marvell,pins = "mpp_camera";
277 marvell,function = "gpio";
280 pmx_sdio0: pmx-sdio0 {
281 marvell,pins = "mpp_sdio0";
282 marvell,function = "sdio0";
285 pmx_sdio0_gpio: pmx-sdio0-gpio {
286 marvell,pins = "mpp_sdio0";
287 marvell,function = "gpio";
290 pmx_sdio1: pmx-sdio1 {
291 marvell,pins = "mpp_sdio1";
292 marvell,function = "sdio1";
295 pmx_sdio1_gpio: pmx-sdio1-gpio {
296 marvell,pins = "mpp_sdio1";
297 marvell,function = "gpio";
300 pmx_audio1_gpio: pmx-audio1-gpio {
301 marvell,pins = "mpp_audio1";
302 marvell,function = "gpio";
306 marvell,pins = "mpp_spi0";
307 marvell,function = "spi0";
310 pmx_spi0_gpio: pmx-spi0-gpio {
311 marvell,pins = "mpp_spi0";
312 marvell,function = "gpio";
315 pmx_uart1: pmx-uart1 {
316 marvell,pins = "mpp_uart1";
317 marvell,function = "uart1";
320 pmx_uart1_gpio: pmx-uart1-gpio {
321 marvell,pins = "mpp_uart1";
322 marvell,function = "gpio";
326 marvell,pins = "mpp_nand";
327 marvell,function = "nand";
330 pmx_nand_gpo: pmx-nand-gpo {
331 marvell,pins = "mpp_nand";
332 marvell,function = "gpo";
336 spi0: spi-ctrl@10600 {
337 compatible = "marvell,orion-spi";
338 #address-cells = <1>;
342 reg = <0x10600 0x28>;
343 clocks = <&core_clk 0>;
344 pinctrl-0 = <&pmx_spi0>;
345 pinctrl-names = "default";
349 spi1: spi-ctrl@14600 {
350 compatible = "marvell,orion-spi";
351 #address-cells = <1>;
355 reg = <0x14600 0x28>;
356 clocks = <&core_clk 0>;
360 i2c0: i2c-ctrl@11000 {
361 compatible = "marvell,mv64xxx-i2c";
362 reg = <0x11000 0x20>;
363 #address-cells = <1>;
366 clock-frequency = <400000>;
368 clocks = <&core_clk 0>;
372 ehci0: usb-host@50000 {
373 compatible = "marvell,orion-ehci";
374 reg = <0x50000 0x1000>;
376 clocks = <&gate_clk 0>;
380 ehci1: usb-host@51000 {
381 compatible = "marvell,orion-ehci";
382 reg = <0x51000 0x1000>;
384 clocks = <&gate_clk 1>;
388 sdio0: sdio-host@92000 {
389 compatible = "marvell,dove-sdhci";
390 reg = <0x92000 0x100>;
391 interrupts = <35>, <37>;
392 clocks = <&gate_clk 8>;
393 pinctrl-0 = <&pmx_sdio0>;
394 pinctrl-names = "default";
398 sdio1: sdio-host@90000 {
399 compatible = "marvell,dove-sdhci";
400 reg = <0x90000 0x100>;
401 interrupts = <36>, <38>;
402 clocks = <&gate_clk 9>;
403 pinctrl-0 = <&pmx_sdio1>;
404 pinctrl-names = "default";
408 sata0: sata-host@a0000 {
409 compatible = "marvell,orion-sata";
410 reg = <0xa0000 0x2400>;
412 clocks = <&gate_clk 3>;
417 rtc: real-time-clock@d8500 {
418 compatible = "marvell,orion-rtc";
419 reg = <0xd8500 0x20>;
422 crypto: crypto-engine@30000 {
423 compatible = "marvell,orion-crypto";
424 reg = <0x30000 0x10000>,
426 reg-names = "regs", "sram";
428 clocks = <&gate_clk 15>;
432 xor0: dma-engine@60800 {
433 compatible = "marvell,orion-xor";
436 clocks = <&gate_clk 23>;
453 xor1: dma-engine@60900 {
454 compatible = "marvell,orion-xor";
457 clocks = <&gate_clk 24>;
474 mdio: mdio-bus@72004 {
475 compatible = "marvell,orion-mdio";
476 #address-cells = <1>;
478 reg = <0x72004 0x84>;
480 clocks = <&gate_clk 2>;
483 ethphy: ethernet-phy {
484 device-type = "ethernet-phy";
485 /* set phy address in board file */
489 eth: ethernet-controller@72000 {
490 compatible = "marvell,orion-eth";
491 #address-cells = <1>;
493 reg = <0x72000 0x4000>;
494 clocks = <&gate_clk 2>;
495 marvell,tx-checksum-limit = <1600>;
499 device_type = "network";
500 compatible = "marvell,orion-eth-port";
503 /* overwrite MAC address in bootloader */
504 local-mac-address = [00 00 00 00 00 00];
505 phy-handle = <ðphy>;