| blob | ccd55c2fdb67e3a69402021709275108a96a6f75 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "skeleton.dtsi"
15 / {
16 aliases {
17 gpio0 = &gpio1;
18 gpio1 = &gpio2;
19 gpio2 = &gpio3;
20 gpio3 = &gpio4;
21 gpio4 = &gpio5;
22 gpio5 = &gpio6;
23 gpio6 = &gpio7;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 spi0 = &ecspi1;
33 spi1 = &ecspi2;
34 spi2 = &ecspi3;
35 spi3 = &ecspi4;
36 };
38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
41 #address-cells = <1>;
42 #size-cells = <1>;
43 interrupt-controller;
44 reg = <0x00a01000 0x1000>,
45 <0x00a00100 0x100>;
46 };
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
55 };
57 ckih1 {
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
60 };
62 osc {
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
65 };
66 };
68 soc {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
73 ranges;
75 dma_apbh: dma-apbh@00110000 {
76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
80 #dma-cells = <1>;
81 dma-channels = <4>;
82 clocks = <&clks 106>;
83 };
85 gpmi: gpmi-nand@00112000 {
86 compatible = "fsl,imx6q-gpmi-nand";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
91 interrupts = <0 15 0x04>;
92 interrupt-names = "bch";
93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
97 dmas = <&dma_apbh 0>;
98 dma-names = "rx-tx";
99 status = "disabled";
100 };
102 timer@00a00600 {
103 compatible = "arm,cortex-a9-twd-timer";
104 reg = <0x00a00600 0x20>;
105 interrupts = <1 13 0xf01>;
106 clocks = <&clks 15>;
107 };
109 L2: l2-cache@00a02000 {
110 compatible = "arm,pl310-cache";
111 reg = <0x00a02000 0x1000>;
112 interrupts = <0 92 0x04>;
113 cache-unified;
114 cache-level = <2>;
115 arm,tag-latency = <4 2 3>;
116 arm,data-latency = <4 2 3>;
117 };
119 pmu {
120 compatible = "arm,cortex-a9-pmu";
121 interrupts = <0 94 0x04>;
122 };
124 aips-bus@02000000 { /* AIPS1 */
125 compatible = "fsl,aips-bus", "simple-bus";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 reg = <0x02000000 0x100000>;
129 ranges;
131 spba-bus@02000000 {
132 compatible = "fsl,spba-bus", "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 reg = <0x02000000 0x40000>;
136 ranges;
138 spdif: spdif@02004000 {
139 reg = <0x02004000 0x4000>;
140 interrupts = <0 52 0x04>;
141 };
143 ecspi1: ecspi@02008000 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
147 reg = <0x02008000 0x4000>;
148 interrupts = <0 31 0x04>;
149 clocks = <&clks 112>, <&clks 112>;
150 clock-names = "ipg", "per";
151 status = "disabled";
152 };
154 ecspi2: ecspi@0200c000 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
158 reg = <0x0200c000 0x4000>;
159 interrupts = <0 32 0x04>;
160 clocks = <&clks 113>, <&clks 113>;
161 clock-names = "ipg", "per";
162 status = "disabled";
163 };
165 ecspi3: ecspi@02010000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>;
170 interrupts = <0 33 0x04>;
171 clocks = <&clks 114>, <&clks 114>;
172 clock-names = "ipg", "per";
173 status = "disabled";
174 };
176 ecspi4: ecspi@02014000 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
180 reg = <0x02014000 0x4000>;
181 interrupts = <0 34 0x04>;
182 clocks = <&clks 115>, <&clks 115>;
183 clock-names = "ipg", "per";
184 status = "disabled";
185 };
187 uart1: serial@02020000 {
188 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
189 reg = <0x02020000 0x4000>;
190 interrupts = <0 26 0x04>;
191 clocks = <&clks 160>, <&clks 161>;
192 clock-names = "ipg", "per";
193 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
194 dma-names = "rx", "tx";
195 status = "disabled";
196 };
198 esai: esai@02024000 {
199 reg = <0x02024000 0x4000>;
200 interrupts = <0 51 0x04>;
201 };
203 ssi1: ssi@02028000 {
204 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
205 reg = <0x02028000 0x4000>;
206 interrupts = <0 46 0x04>;
207 clocks = <&clks 178>;
208 dmas = <&sdma 37 1 0>,
209 <&sdma 38 1 0>;
210 dma-names = "rx", "tx";
211 fsl,fifo-depth = <15>;
212 fsl,ssi-dma-events = <38 37>;
213 status = "disabled";
214 };
216 ssi2: ssi@0202c000 {
217 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
218 reg = <0x0202c000 0x4000>;
219 interrupts = <0 47 0x04>;
220 clocks = <&clks 179>;
221 dmas = <&sdma 41 1 0>,
222 <&sdma 42 1 0>;
223 dma-names = "rx", "tx";
224 fsl,fifo-depth = <15>;
225 fsl,ssi-dma-events = <42 41>;
226 status = "disabled";
227 };
229 ssi3: ssi@02030000 {
230 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
231 reg = <0x02030000 0x4000>;
232 interrupts = <0 48 0x04>;
233 clocks = <&clks 180>;
234 dmas = <&sdma 45 1 0>,
235 <&sdma 46 1 0>;
236 dma-names = "rx", "tx";
237 fsl,fifo-depth = <15>;
238 fsl,ssi-dma-events = <46 45>;
239 status = "disabled";
240 };
242 asrc: asrc@02034000 {
243 reg = <0x02034000 0x4000>;
244 interrupts = <0 50 0x04>;
245 };
247 spba@0203c000 {
248 reg = <0x0203c000 0x4000>;
249 };
250 };
252 vpu: vpu@02040000 {
253 reg = <0x02040000 0x3c000>;
254 interrupts = <0 3 0x04 0 12 0x04>;
255 };
257 aipstz@0207c000 { /* AIPSTZ1 */
258 reg = <0x0207c000 0x4000>;
259 };
261 pwm1: pwm@02080000 {
262 #pwm-cells = <2>;
263 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
264 reg = <0x02080000 0x4000>;
265 interrupts = <0 83 0x04>;
266 clocks = <&clks 62>, <&clks 145>;
267 clock-names = "ipg", "per";
268 };
270 pwm2: pwm@02084000 {
271 #pwm-cells = <2>;
272 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
273 reg = <0x02084000 0x4000>;
274 interrupts = <0 84 0x04>;
275 clocks = <&clks 62>, <&clks 146>;
276 clock-names = "ipg", "per";
277 };
279 pwm3: pwm@02088000 {
280 #pwm-cells = <2>;
281 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
282 reg = <0x02088000 0x4000>;
283 interrupts = <0 85 0x04>;
284 clocks = <&clks 62>, <&clks 147>;
285 clock-names = "ipg", "per";
286 };
288 pwm4: pwm@0208c000 {
289 #pwm-cells = <2>;
290 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
291 reg = <0x0208c000 0x4000>;
292 interrupts = <0 86 0x04>;
293 clocks = <&clks 62>, <&clks 148>;
294 clock-names = "ipg", "per";
295 };
297 can1: flexcan@02090000 {
298 compatible = "fsl,imx6q-flexcan";
299 reg = <0x02090000 0x4000>;
300 interrupts = <0 110 0x04>;
301 clocks = <&clks 108>, <&clks 109>;
302 clock-names = "ipg", "per";
303 };
305 can2: flexcan@02094000 {
306 compatible = "fsl,imx6q-flexcan";
307 reg = <0x02094000 0x4000>;
308 interrupts = <0 111 0x04>;
309 clocks = <&clks 110>, <&clks 111>;
310 clock-names = "ipg", "per";
311 };
313 gpt: gpt@02098000 {
314 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
315 reg = <0x02098000 0x4000>;
316 interrupts = <0 55 0x04>;
317 clocks = <&clks 119>, <&clks 120>;
318 clock-names = "ipg", "per";
319 };
321 gpio1: gpio@0209c000 {
322 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
323 reg = <0x0209c000 0x4000>;
324 interrupts = <0 66 0x04 0 67 0x04>;
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 };
331 gpio2: gpio@020a0000 {
332 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
333 reg = <0x020a0000 0x4000>;
334 interrupts = <0 68 0x04 0 69 0x04>;
335 gpio-controller;
336 #gpio-cells = <2>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339 };
341 gpio3: gpio@020a4000 {
342 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
343 reg = <0x020a4000 0x4000>;
344 interrupts = <0 70 0x04 0 71 0x04>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 };
351 gpio4: gpio@020a8000 {
352 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
353 reg = <0x020a8000 0x4000>;
354 interrupts = <0 72 0x04 0 73 0x04>;
355 gpio-controller;
356 #gpio-cells = <2>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
359 };
361 gpio5: gpio@020ac000 {
362 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
363 reg = <0x020ac000 0x4000>;
364 interrupts = <0 74 0x04 0 75 0x04>;
365 gpio-controller;
366 #gpio-cells = <2>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 };
371 gpio6: gpio@020b0000 {
372 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
373 reg = <0x020b0000 0x4000>;
374 interrupts = <0 76 0x04 0 77 0x04>;
375 gpio-controller;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 };
381 gpio7: gpio@020b4000 {
382 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
383 reg = <0x020b4000 0x4000>;
384 interrupts = <0 78 0x04 0 79 0x04>;
385 gpio-controller;
386 #gpio-cells = <2>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
389 };
391 kpp: kpp@020b8000 {
392 reg = <0x020b8000 0x4000>;
393 interrupts = <0 82 0x04>;
394 };
396 wdog1: wdog@020bc000 {
397 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
398 reg = <0x020bc000 0x4000>;
399 interrupts = <0 80 0x04>;
400 clocks = <&clks 0>;
401 };
403 wdog2: wdog@020c0000 {
404 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
405 reg = <0x020c0000 0x4000>;
406 interrupts = <0 81 0x04>;
407 clocks = <&clks 0>;
408 status = "disabled";
409 };
411 clks: ccm@020c4000 {
412 compatible = "fsl,imx6q-ccm";
413 reg = <0x020c4000 0x4000>;
414 interrupts = <0 87 0x04 0 88 0x04>;
415 #clock-cells = <1>;
416 };
418 anatop: anatop@020c8000 {
419 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
420 reg = <0x020c8000 0x1000>;
421 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
423 regulator-1p1@110 {
424 compatible = "fsl,anatop-regulator";
425 regulator-name = "vdd1p1";
426 regulator-min-microvolt = <800000>;
427 regulator-max-microvolt = <1375000>;
428 regulator-always-on;
429 anatop-reg-offset = <0x110>;
430 anatop-vol-bit-shift = <8>;
431 anatop-vol-bit-width = <5>;
432 anatop-min-bit-val = <4>;
433 anatop-min-voltage = <800000>;
434 anatop-max-voltage = <1375000>;
435 };
437 regulator-3p0@120 {
438 compatible = "fsl,anatop-regulator";
439 regulator-name = "vdd3p0";
440 regulator-min-microvolt = <2800000>;
441 regulator-max-microvolt = <3150000>;
442 regulator-always-on;
443 anatop-reg-offset = <0x120>;
444 anatop-vol-bit-shift = <8>;
445 anatop-vol-bit-width = <5>;
446 anatop-min-bit-val = <0>;
447 anatop-min-voltage = <2625000>;
448 anatop-max-voltage = <3400000>;
449 };
451 regulator-2p5@130 {
452 compatible = "fsl,anatop-regulator";
453 regulator-name = "vdd2p5";
454 regulator-min-microvolt = <2000000>;
455 regulator-max-microvolt = <2750000>;
456 regulator-always-on;
457 anatop-reg-offset = <0x130>;
458 anatop-vol-bit-shift = <8>;
459 anatop-vol-bit-width = <5>;
460 anatop-min-bit-val = <0>;
461 anatop-min-voltage = <2000000>;
462 anatop-max-voltage = <2750000>;
463 };
465 reg_arm: regulator-vddcore@140 {
466 compatible = "fsl,anatop-regulator";
467 regulator-name = "cpu";
468 regulator-min-microvolt = <725000>;
469 regulator-max-microvolt = <1450000>;
470 regulator-always-on;
471 anatop-reg-offset = <0x140>;
472 anatop-vol-bit-shift = <0>;
473 anatop-vol-bit-width = <5>;
474 anatop-delay-reg-offset = <0x170>;
475 anatop-delay-bit-shift = <24>;
476 anatop-delay-bit-width = <2>;
477 anatop-min-bit-val = <1>;
478 anatop-min-voltage = <725000>;
479 anatop-max-voltage = <1450000>;
480 };
482 reg_pu: regulator-vddpu@140 {
483 compatible = "fsl,anatop-regulator";
484 regulator-name = "vddpu";
485 regulator-min-microvolt = <725000>;
486 regulator-max-microvolt = <1450000>;
487 regulator-always-on;
488 anatop-reg-offset = <0x140>;
489 anatop-vol-bit-shift = <9>;
490 anatop-vol-bit-width = <5>;
491 anatop-delay-reg-offset = <0x170>;
492 anatop-delay-bit-shift = <26>;
493 anatop-delay-bit-width = <2>;
494 anatop-min-bit-val = <1>;
495 anatop-min-voltage = <725000>;
496 anatop-max-voltage = <1450000>;
497 };
499 reg_soc: regulator-vddsoc@140 {
500 compatible = "fsl,anatop-regulator";
501 regulator-name = "vddsoc";
502 regulator-min-microvolt = <725000>;
503 regulator-max-microvolt = <1450000>;
504 regulator-always-on;
505 anatop-reg-offset = <0x140>;
506 anatop-vol-bit-shift = <18>;
507 anatop-vol-bit-width = <5>;
508 anatop-delay-reg-offset = <0x170>;
509 anatop-delay-bit-shift = <28>;
510 anatop-delay-bit-width = <2>;
511 anatop-min-bit-val = <1>;
512 anatop-min-voltage = <725000>;
513 anatop-max-voltage = <1450000>;
514 };
515 };
517 tempmon: tempmon {
518 compatible = "fsl,imx6q-tempmon";
519 interrupts = <0 49 0x04>;
520 fsl,tempmon = <&anatop>;
521 fsl,tempmon-data = <&ocotp>;
522 };
524 usbphy1: usbphy@020c9000 {
525 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
526 reg = <0x020c9000 0x1000>;
527 interrupts = <0 44 0x04>;
528 clocks = <&clks 182>;
529 };
531 usbphy2: usbphy@020ca000 {
532 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
533 reg = <0x020ca000 0x1000>;
534 interrupts = <0 45 0x04>;
535 clocks = <&clks 183>;
536 };
538 snvs@020cc000 {
539 compatible = "fsl,sec-v4.0-mon", "simple-bus";
540 #address-cells = <1>;
541 #size-cells = <1>;
542 ranges = <0 0x020cc000 0x4000>;
544 snvs-rtc-lp@34 {
545 compatible = "fsl,sec-v4.0-mon-rtc-lp";
546 reg = <0x34 0x58>;
547 interrupts = <0 19 0x04 0 20 0x04>;
548 };
549 };
551 epit1: epit@020d0000 { /* EPIT1 */
552 reg = <0x020d0000 0x4000>;
553 interrupts = <0 56 0x04>;
554 };
556 epit2: epit@020d4000 { /* EPIT2 */
557 reg = <0x020d4000 0x4000>;
558 interrupts = <0 57 0x04>;
559 };
561 src: src@020d8000 {
562 compatible = "fsl,imx6q-src", "fsl,imx51-src";
563 reg = <0x020d8000 0x4000>;
564 interrupts = <0 91 0x04 0 96 0x04>;
565 #reset-cells = <1>;
566 };
568 gpc: gpc@020dc000 {
569 compatible = "fsl,imx6q-gpc";
570 reg = <0x020dc000 0x4000>;
571 interrupts = <0 89 0x04 0 90 0x04>;
572 };
574 gpr: iomuxc-gpr@020e0000 {
575 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
576 reg = <0x020e0000 0x38>;
577 };
579 iomuxc: iomuxc@020e0000 {
580 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
581 reg = <0x020e0000 0x4000>;
583 audmux {
584 pinctrl_audmux_1: audmux-1 {
585 fsl,pins = <
586 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
587 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
588 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
589 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
590 >;
591 };
593 pinctrl_audmux_2: audmux-2 {
594 fsl,pins = <
595 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
596 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
597 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
598 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
599 >;
600 };
602 pinctrl_audmux_3: audmux-3 {
603 fsl,pins = <
604 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
605 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
606 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
607 >;
608 };
609 };
611 ecspi1 {
612 pinctrl_ecspi1_1: ecspi1grp-1 {
613 fsl,pins = <
614 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
615 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
616 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
617 >;
618 };
620 pinctrl_ecspi1_2: ecspi1grp-2 {
621 fsl,pins = <
622 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
623 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
624 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
625 >;
626 };
627 };
629 ecspi3 {
630 pinctrl_ecspi3_1: ecspi3grp-1 {
631 fsl,pins = <
632 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
633 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
634 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
635 >;
636 };
637 };
639 enet {
640 pinctrl_enet_1: enetgrp-1 {
641 fsl,pins = <
642 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
643 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
644 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
645 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
646 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
647 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
648 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
649 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
650 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
651 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
652 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
653 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
654 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
655 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
656 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
657 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
658 >;
659 };
661 pinctrl_enet_2: enetgrp-2 {
662 fsl,pins = <
663 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
664 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
665 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
666 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
667 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
668 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
669 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
670 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
671 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
672 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
673 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
674 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
675 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
676 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
677 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
678 >;
679 };
681 pinctrl_enet_3: enetgrp-3 {
682 fsl,pins = <
683 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
684 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
685 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
686 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
687 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
688 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
689 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
690 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
691 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
692 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
693 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
694 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
695 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
696 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
697 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
698 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
699 >;
700 };
701 };
703 esai {
704 pinctrl_esai_1: esaigrp-1 {
705 fsl,pins = <
706 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
707 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
708 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
709 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
710 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
711 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
712 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
713 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
714 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
715 >;
716 };
718 pinctrl_esai_2: esaigrp-2 {
719 fsl,pins = <
720 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
721 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
722 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
723 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
724 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
725 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
726 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
727 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
728 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
729 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
730 >;
731 };
732 };
734 flexcan1 {
735 pinctrl_flexcan1_1: flexcan1grp-1 {
736 fsl,pins = <
737 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
738 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
739 >;
740 };
742 pinctrl_flexcan1_2: flexcan1grp-2 {
743 fsl,pins = <
744 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
745 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
746 >;
747 };
748 };
750 flexcan2 {
751 pinctrl_flexcan2_1: flexcan2grp-1 {
752 fsl,pins = <
753 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
754 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
755 >;
756 };
757 };
759 gpmi-nand {
760 pinctrl_gpmi_nand_1: gpmi-nand-1 {
761 fsl,pins = <
762 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
763 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
764 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
765 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
766 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
767 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
768 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
769 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
770 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
771 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
772 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
773 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
774 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
775 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
776 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
777 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
778 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
779 >;
780 };
781 };
783 hdmi_hdcp {
784 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
785 fsl,pins = <
786 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
787 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
788 >;
789 };
791 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
792 fsl,pins = <
793 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
794 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
795 >;
796 };
798 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
799 fsl,pins = <
800 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
801 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
802 >;
803 };
804 };
806 hdmi_cec {
807 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
808 fsl,pins = <
809 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
810 >;
811 };
813 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
814 fsl,pins = <
815 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
816 >;
817 };
818 };
820 i2c1 {
821 pinctrl_i2c1_1: i2c1grp-1 {
822 fsl,pins = <
823 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
824 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
825 >;
826 };
828 pinctrl_i2c1_2: i2c1grp-2 {
829 fsl,pins = <
830 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
831 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
832 >;
833 };
834 };
836 i2c2 {
837 pinctrl_i2c2_1: i2c2grp-1 {
838 fsl,pins = <
839 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
840 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
841 >;
842 };
844 pinctrl_i2c2_2: i2c2grp-2 {
845 fsl,pins = <
846 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
847 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
848 >;
849 };
851 pinctrl_i2c2_3: i2c2grp-3 {
852 fsl,pins = <
853 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
854 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
855 >;
856 };
857 };
859 i2c3 {
860 pinctrl_i2c3_1: i2c3grp-1 {
861 fsl,pins = <
862 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
863 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
864 >;
865 };
867 pinctrl_i2c3_2: i2c3grp-2 {
868 fsl,pins = <
869 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
870 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
871 >;
872 };
874 pinctrl_i2c3_3: i2c3grp-3 {
875 fsl,pins = <
876 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
877 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
878 >;
879 };
881 pinctrl_i2c3_4: i2c3grp-4 {
882 fsl,pins = <
883 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
884 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
885 >;
886 };
887 };
889 ipu1 {
890 pinctrl_ipu1_1: ipu1grp-1 {
891 fsl,pins = <
892 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
893 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
894 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
895 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
896 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
897 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
898 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
899 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
900 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
901 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
902 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
903 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
904 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
905 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
906 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
907 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
908 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
909 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
910 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
911 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
912 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
913 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
914 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
915 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
916 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
917 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
918 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
919 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
920 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
921 >;
922 };
924 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
925 fsl,pins = <
926 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
927 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
928 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
929 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
930 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
931 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
932 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
933 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
934 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
935 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
936 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
937 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
938 >;
939 };
941 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
942 fsl,pins = <
943 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
944 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
945 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
946 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
947 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
948 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
949 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
950 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
951 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
952 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
953 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
954 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
955 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
956 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
957 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
958 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
959 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
960 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
961 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
962 >;
963 };
964 };
966 mlb {
967 pinctrl_mlb_1: mlbgrp-1 {
968 fsl,pins = <
969 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
970 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
971 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
972 >;
973 };
975 pinctrl_mlb_2: mlbgrp-2 {
976 fsl,pins = <
977 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
978 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
979 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
980 >;
981 };
982 };
984 pwm0 {
985 pinctrl_pwm0_1: pwm0grp-1 {
986 fsl,pins = <
987 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
988 >;
989 };
990 };
992 pwm3 {
993 pinctrl_pwm3_1: pwm3grp-1 {
994 fsl,pins = <
995 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
996 >;
997 };
998 };
1000 spdif {
1001 pinctrl_spdif_1: spdifgrp-1 {
1002 fsl,pins = <
1003 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1004 >;
1005 };
1007 pinctrl_spdif_2: spdifgrp-2 {
1008 fsl,pins = <
1009 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1010 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1011 >;
1012 };
1013 };
1015 uart1 {
1016 pinctrl_uart1_1: uart1grp-1 {
1017 fsl,pins = <
1018 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1019 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1020 >;
1021 };
1022 };
1024 uart2 {
1025 pinctrl_uart2_1: uart2grp-1 {
1026 fsl,pins = <
1027 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1028 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1029 >;
1030 };
1032 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1033 fsl,pins = <
1034 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1035 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1036 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1037 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1038 >;
1039 };
1040 };
1042 uart3 {
1043 pinctrl_uart3_1: uart3grp-1 {
1044 fsl,pins = <
1045 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1046 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1047 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1048 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1049 >;
1050 };
1052 pinctrl_uart3_2: uart3grp-2 {
1053 fsl,pins = <
1054 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1055 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1056 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1057 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1058 >;
1059 };
1060 };
1062 uart4 {
1063 pinctrl_uart4_1: uart4grp-1 {
1064 fsl,pins = <
1065 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1066 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1067 >;
1068 };
1069 };
1071 usbotg {
1072 pinctrl_usbotg_1: usbotggrp-1 {
1073 fsl,pins = <
1074 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1075 >;
1076 };
1078 pinctrl_usbotg_2: usbotggrp-2 {
1079 fsl,pins = <
1080 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1081 >;
1082 };
1083 };
1085 usbh2 {
1086 pinctrl_usbh2_1: usbh2grp-1 {
1087 fsl,pins = <
1088 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1089 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1090 >;
1091 };
1093 pinctrl_usbh2_2: usbh2grp-2 {
1094 fsl,pins = <
1095 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1096 >;
1097 };
1098 };
1100 usbh3 {
1101 pinctrl_usbh3_1: usbh3grp-1 {
1102 fsl,pins = <
1103 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1104 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1105 >;
1106 };
1108 pinctrl_usbh3_2: usbh3grp-2 {
1109 fsl,pins = <
1110 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1111 >;
1112 };
1113 };
1115 usdhc1 {
1116 pinctrl_usdhc1_1: usdhc1grp-1 {
1117 fsl,pins = <
1118 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1119 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1120 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1121 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1122 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1123 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1124 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1125 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1126 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1127 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1128 >;
1129 };
1131 pinctrl_usdhc1_2: usdhc1grp-2 {
1132 fsl,pins = <
1133 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1134 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1135 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1136 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1137 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1138 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1139 >;
1140 };
1141 };
1143 usdhc2 {
1144 pinctrl_usdhc2_1: usdhc2grp-1 {
1145 fsl,pins = <
1146 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1147 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1148 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1149 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1150 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1151 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1152 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1153 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1154 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1155 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1156 >;
1157 };
1159 pinctrl_usdhc2_2: usdhc2grp-2 {
1160 fsl,pins = <
1161 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1162 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1163 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1164 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1165 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1166 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1167 >;
1168 };
1169 };
1171 usdhc3 {
1172 pinctrl_usdhc3_1: usdhc3grp-1 {
1173 fsl,pins = <
1174 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1175 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1176 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1177 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1178 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1179 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1180 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1181 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1182 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1183 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1184 >;
1185 };
1187 pinctrl_usdhc3_2: usdhc3grp-2 {
1188 fsl,pins = <
1189 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1190 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1191 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1192 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1193 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1194 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1195 >;
1196 };
1197 };
1199 usdhc4 {
1200 pinctrl_usdhc4_1: usdhc4grp-1 {
1201 fsl,pins = <
1202 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1203 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1204 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1205 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1206 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1207 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1208 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1209 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1210 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1211 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1212 >;
1213 };
1215 pinctrl_usdhc4_2: usdhc4grp-2 {
1216 fsl,pins = <
1217 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1218 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1219 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1220 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1221 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1222 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1223 >;
1224 };
1225 };
1227 weim {
1228 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1229 fsl,pins = <
1230 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1231 >;
1232 };
1234 pinctrl_weim_nor_1: weim_norgrp-1 {
1235 fsl,pins = <
1236 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1237 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1238 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1239 /* data */
1240 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1241 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1242 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1243 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1244 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1245 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1246 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1247 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1248 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1249 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1250 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1251 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1252 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1253 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1254 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1255 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1256 /* address */
1257 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1258 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1259 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1260 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1261 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1262 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1263 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1264 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1265 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1266 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1267 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1268 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1269 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1270 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1271 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1272 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1273 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1274 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1275 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1276 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1277 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1278 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1279 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1280 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1281 >;
1282 };
1283 };
1284 };
1286 ldb: ldb@020e0008 {
1287 #address-cells = <1>;
1288 #size-cells = <0>;
1289 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1290 gpr = <&gpr>;
1291 status = "disabled";
1293 lvds-channel@0 {
1294 reg = <0>;
1295 status = "disabled";
1296 };
1298 lvds-channel@1 {
1299 reg = <1>;
1300 status = "disabled";
1301 };
1302 };
1304 dcic1: dcic@020e4000 {
1305 reg = <0x020e4000 0x4000>;
1306 interrupts = <0 124 0x04>;
1307 };
1309 dcic2: dcic@020e8000 {
1310 reg = <0x020e8000 0x4000>;
1311 interrupts = <0 125 0x04>;
1312 };
1314 sdma: sdma@020ec000 {
1315 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1316 reg = <0x020ec000 0x4000>;
1317 interrupts = <0 2 0x04>;
1318 clocks = <&clks 155>, <&clks 155>;
1319 clock-names = "ipg", "ahb";
1320 #dma-cells = <3>;
1321 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1322 };
1323 };
1325 aips-bus@02100000 { /* AIPS2 */
1326 compatible = "fsl,aips-bus", "simple-bus";
1327 #address-cells = <1>;
1328 #size-cells = <1>;
1329 reg = <0x02100000 0x100000>;
1330 ranges;
1332 caam@02100000 {
1333 reg = <0x02100000 0x40000>;
1334 interrupts = <0 105 0x04 0 106 0x04>;
1335 };
1337 aipstz@0217c000 { /* AIPSTZ2 */
1338 reg = <0x0217c000 0x4000>;
1339 };
1341 usbotg: usb@02184000 {
1342 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1343 reg = <0x02184000 0x200>;
1344 interrupts = <0 43 0x04>;
1345 clocks = <&clks 162>;
1346 fsl,usbphy = <&usbphy1>;
1347 fsl,usbmisc = <&usbmisc 0>;
1348 status = "disabled";
1349 };
1351 usbh1: usb@02184200 {
1352 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1353 reg = <0x02184200 0x200>;
1354 interrupts = <0 40 0x04>;
1355 clocks = <&clks 162>;
1356 fsl,usbphy = <&usbphy2>;
1357 fsl,usbmisc = <&usbmisc 1>;
1358 status = "disabled";
1359 };
1361 usbh2: usb@02184400 {
1362 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1363 reg = <0x02184400 0x200>;
1364 interrupts = <0 41 0x04>;
1365 clocks = <&clks 162>;
1366 fsl,usbmisc = <&usbmisc 2>;
1367 status = "disabled";
1368 };
1370 usbh3: usb@02184600 {
1371 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1372 reg = <0x02184600 0x200>;
1373 interrupts = <0 42 0x04>;
1374 clocks = <&clks 162>;
1375 fsl,usbmisc = <&usbmisc 3>;
1376 status = "disabled";
1377 };
1379 usbmisc: usbmisc@02184800 {
1380 #index-cells = <1>;
1381 compatible = "fsl,imx6q-usbmisc";
1382 reg = <0x02184800 0x200>;
1383 clocks = <&clks 162>;
1384 };
1386 fec: ethernet@02188000 {
1387 compatible = "fsl,imx6q-fec";
1388 reg = <0x02188000 0x4000>;
1389 interrupts = <0 118 0x04 0 119 0x04>;
1390 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1391 clock-names = "ipg", "ahb", "ptp";
1392 status = "disabled";
1393 };
1395 mlb@0218c000 {
1396 reg = <0x0218c000 0x4000>;
1397 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1398 };
1400 usdhc1: usdhc@02190000 {
1401 compatible = "fsl,imx6q-usdhc";
1402 reg = <0x02190000 0x4000>;
1403 interrupts = <0 22 0x04>;
1404 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1405 clock-names = "ipg", "ahb", "per";
1406 bus-width = <4>;
1407 status = "disabled";
1408 };
1410 usdhc2: usdhc@02194000 {
1411 compatible = "fsl,imx6q-usdhc";
1412 reg = <0x02194000 0x4000>;
1413 interrupts = <0 23 0x04>;
1414 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1415 clock-names = "ipg", "ahb", "per";
1416 bus-width = <4>;
1417 status = "disabled";
1418 };
1420 usdhc3: usdhc@02198000 {
1421 compatible = "fsl,imx6q-usdhc";
1422 reg = <0x02198000 0x4000>;
1423 interrupts = <0 24 0x04>;
1424 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1425 clock-names = "ipg", "ahb", "per";
1426 bus-width = <4>;
1427 status = "disabled";
1428 };
1430 usdhc4: usdhc@0219c000 {
1431 compatible = "fsl,imx6q-usdhc";
1432 reg = <0x0219c000 0x4000>;
1433 interrupts = <0 25 0x04>;
1434 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1435 clock-names = "ipg", "ahb", "per";
1436 bus-width = <4>;
1437 status = "disabled";
1438 };
1440 i2c1: i2c@021a0000 {
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1443 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1444 reg = <0x021a0000 0x4000>;
1445 interrupts = <0 36 0x04>;
1446 clocks = <&clks 125>;
1447 status = "disabled";
1448 };
1450 i2c2: i2c@021a4000 {
1451 #address-cells = <1>;
1452 #size-cells = <0>;
1453 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1454 reg = <0x021a4000 0x4000>;
1455 interrupts = <0 37 0x04>;
1456 clocks = <&clks 126>;
1457 status = "disabled";
1458 };
1460 i2c3: i2c@021a8000 {
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1464 reg = <0x021a8000 0x4000>;
1465 interrupts = <0 38 0x04>;
1466 clocks = <&clks 127>;
1467 status = "disabled";
1468 };
1470 romcp@021ac000 {
1471 reg = <0x021ac000 0x4000>;
1472 };
1474 mmdc0: mmdc@021b0000 { /* MMDC0 */
1475 compatible = "fsl,imx6q-mmdc";
1476 reg = <0x021b0000 0x4000>;
1477 };
1479 mmdc1: mmdc@021b4000 { /* MMDC1 */
1480 reg = <0x021b4000 0x4000>;
1481 };
1483 weim: weim@021b8000 {
1484 compatible = "fsl,imx6q-weim";
1485 reg = <0x021b8000 0x4000>;
1486 interrupts = <0 14 0x04>;
1487 clocks = <&clks 196>;
1488 };
1490 ocotp: ocotp@021bc000 {
1491 compatible = "fsl,imx6q-ocotp", "syscon";
1492 reg = <0x021bc000 0x4000>;
1493 };
1495 tzasc@021d0000 { /* TZASC1 */
1496 reg = <0x021d0000 0x4000>;
1497 interrupts = <0 108 0x04>;
1498 };
1500 tzasc@021d4000 { /* TZASC2 */
1501 reg = <0x021d4000 0x4000>;
1502 interrupts = <0 109 0x04>;
1503 };
1505 audmux: audmux@021d8000 {
1506 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1507 reg = <0x021d8000 0x4000>;
1508 status = "disabled";
1509 };
1511 mipi@021dc000 { /* MIPI-CSI */
1512 reg = <0x021dc000 0x4000>;
1513 };
1515 mipi@021e0000 { /* MIPI-DSI */
1516 reg = <0x021e0000 0x4000>;
1517 };
1519 vdoa@021e4000 {
1520 reg = <0x021e4000 0x4000>;
1521 interrupts = <0 18 0x04>;
1522 };
1524 uart2: serial@021e8000 {
1525 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1526 reg = <0x021e8000 0x4000>;
1527 interrupts = <0 27 0x04>;
1528 clocks = <&clks 160>, <&clks 161>;
1529 clock-names = "ipg", "per";
1530 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1531 dma-names = "rx", "tx";
1532 status = "disabled";
1533 };
1535 uart3: serial@021ec000 {
1536 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1537 reg = <0x021ec000 0x4000>;
1538 interrupts = <0 28 0x04>;
1539 clocks = <&clks 160>, <&clks 161>;
1540 clock-names = "ipg", "per";
1541 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1542 dma-names = "rx", "tx";
1543 status = "disabled";
1544 };
1546 uart4: serial@021f0000 {
1547 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1548 reg = <0x021f0000 0x4000>;
1549 interrupts = <0 29 0x04>;
1550 clocks = <&clks 160>, <&clks 161>;
1551 clock-names = "ipg", "per";
1552 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1553 dma-names = "rx", "tx";
1554 status = "disabled";
1555 };
1557 uart5: serial@021f4000 {
1558 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1559 reg = <0x021f4000 0x4000>;
1560 interrupts = <0 30 0x04>;
1561 clocks = <&clks 160>, <&clks 161>;
1562 clock-names = "ipg", "per";
1563 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1564 dma-names = "rx", "tx";
1565 status = "disabled";
1566 };
1567 };
1569 ipu1: ipu@02400000 {
1570 #crtc-cells = <1>;
1571 compatible = "fsl,imx6q-ipu";
1572 reg = <0x02400000 0x400000>;
1573 interrupts = <0 6 0x4 0 5 0x4>;
1574 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1575 clock-names = "bus", "di0", "di1";
1576 resets = <&src 2>;
1577 };
1578 };
1579 };