arch/arm/boot/dts/tegra30.dtsi

   1 #include <dt-bindings/clock/tegra30-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/interrupt-controller/arm-gic.h>
   4
   5 #include "skeleton.dtsi"
   6
   7 / {
   8         compatible = "nvidia,tegra30";
   9         interrupt-parent = <&intc>;
  10
  11         aliases {
  12                 serial0 = &uarta;
  13                 serial1 = &uartb;
  14                 serial2 = &uartc;
  15                 serial3 = &uartd;
  16                 serial4 = &uarte;
  17         };
  18
  19         pcie-controller {
  20                 compatible = "nvidia,tegra30-pcie";
  21                 device_type = "pci";
  22                 reg = <0x00003000 0x00000800   /* PADS registers */
  23                        0x00003800 0x00000200   /* AFI registers */
  24                        0x10000000 0x10000000>; /* configuration space */
  25                 reg-names = "pads", "afi", "cs";
  26                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  27                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  28                 interrupt-names = "intr", "msi";
  29
  30                 bus-range = <0x00 0xff>;
  31                 #address-cells = <3>;
  32                 #size-cells = <2>;
  33
  34                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  35                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  36                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  37                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  38                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  39                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  40
  41                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  42                          <&tegra_car TEGRA30_CLK_AFI>,
  43                          <&tegra_car TEGRA30_CLK_PCIEX>,
  44                          <&tegra_car TEGRA30_CLK_PLL_E>,
  45                          <&tegra_car TEGRA30_CLK_CML0>;
  46                 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
  47                 status = "disabled";
  48
  49                 pci@1,0 {
  50                         device_type = "pci";
  51                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  52                         reg = <0x000800 0 0 0 0>;
  53                         status = "disabled";
  54
  55                         #address-cells = <3>;
  56                         #size-cells = <2>;
  57                         ranges;
  58
  59                         nvidia,num-lanes = <2>;
  60                 };
  61
  62                 pci@2,0 {
  63                         device_type = "pci";
  64                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  65                         reg = <0x001000 0 0 0 0>;
  66                         status = "disabled";
  67
  68                         #address-cells = <3>;
  69                         #size-cells = <2>;
  70                         ranges;
  71
  72                         nvidia,num-lanes = <2>;
  73                 };
  74
  75                 pci@3,0 {
  76                         device_type = "pci";
  77                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  78                         reg = <0x001800 0 0 0 0>;
  79                         status = "disabled";
  80
  81                         #address-cells = <3>;
  82                         #size-cells = <2>;
  83                         ranges;
  84
  85                         nvidia,num-lanes = <2>;
  86                 };
  87         };
  88
  89         host1x {
  90                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  91                 reg = <0x50000000 0x00024000>;
  92                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  93                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  94                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
  95
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98
  99                 ranges = <0x54000000 0x54000000 0x04000000>;
 100
 101                 mpe {
 102                         compatible = "nvidia,tegra30-mpe";
 103                         reg = <0x54040000 0x00040000>;
 104                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 105                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 106                 };
 107
 108                 vi {
 109                         compatible = "nvidia,tegra30-vi";
 110                         reg = <0x54080000 0x00040000>;
 111                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 113                 };
 114
 115                 epp {
 116                         compatible = "nvidia,tegra30-epp";
 117                         reg = <0x540c0000 0x00040000>;
 118                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 120                 };
 121
 122                 isp {
 123                         compatible = "nvidia,tegra30-isp";
 124                         reg = <0x54100000 0x00040000>;
 125                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 127                 };
 128
 129                 gr2d {
 130                         compatible = "nvidia,tegra30-gr2d";
 131                         reg = <0x54140000 0x00040000>;
 132                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 133                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 134                 };
 135
 136                 gr3d {
 137                         compatible = "nvidia,tegra30-gr3d";
 138                         reg = <0x54180000 0x00040000>;
 139                         clocks = <&tegra_car 24 &tegra_car 98>;
 140                         clock-names = "3d", "3d2";
 141                 };
 142
 143                 dc@54200000 {
 144                         compatible = "nvidia,tegra30-dc";
 145                         reg = <0x54200000 0x00040000>;
 146                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 148                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 149                         clock-names = "disp1", "parent";
 150
 151                         rgb {
 152                                 status = "disabled";
 153                         };
 154                 };
 155
 156                 dc@54240000 {
 157                         compatible = "nvidia,tegra30-dc";
 158                         reg = <0x54240000 0x00040000>;
 159                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 160                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 161                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 162                         clock-names = "disp2", "parent";
 163
 164                         rgb {
 165                                 status = "disabled";
 166                         };
 167                 };
 168
 169                 hdmi {
 170                         compatible = "nvidia,tegra30-hdmi";
 171                         reg = <0x54280000 0x00040000>;
 172                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 173                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 174                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 175                         clock-names = "hdmi", "parent";
 176                         status = "disabled";
 177                 };
 178
 179                 tvo {
 180                         compatible = "nvidia,tegra30-tvo";
 181                         reg = <0x542c0000 0x00040000>;
 182                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 184                         status = "disabled";
 185                 };
 186
 187                 dsi {
 188                         compatible = "nvidia,tegra30-dsi";
 189                         reg = <0x54300000 0x00040000>;
 190                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 191                         status = "disabled";
 192                 };
 193         };
 194
 195         timer@50004600 {
 196                 compatible = "arm,cortex-a9-twd-timer";
 197                 reg = <0x50040600 0x20>;
 198                 interrupts = <GIC_PPI 13
 199                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 200                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 201         };
 202
 203         intc: interrupt-controller {
 204                 compatible = "arm,cortex-a9-gic";
 205                 reg = <0x50041000 0x1000
 206                        0x50040100 0x0100>;
 207                 interrupt-controller;
 208                 #interrupt-cells = <3>;
 209         };
 210
 211         cache-controller {
 212                 compatible = "arm,pl310-cache";
 213                 reg = <0x50043000 0x1000>;
 214                 arm,data-latency = <6 6 2>;
 215                 arm,tag-latency = <5 5 2>;
 216                 cache-unified;
 217                 cache-level = <2>;
 218         };
 219
 220         timer@60005000 {
 221                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 222                 reg = <0x60005000 0x400>;
 223                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 224                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 230         };
 231
 232         tegra_car: clock {
 233                 compatible = "nvidia,tegra30-car";
 234                 reg = <0x60006000 0x1000>;
 235                 #clock-cells = <1>;
 236         };
 237
 238         apbdma: dma {
 239                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 240                 reg = <0x6000a000 0x1400>;
 241                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 245                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 274         };
 275
 276         ahb: ahb {
 277                 compatible = "nvidia,tegra30-ahb";
 278                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 279         };
 280
 281         gpio: gpio {
 282                 compatible = "nvidia,tegra30-gpio";
 283                 reg = <0x6000d000 0x1000>;
 284                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 292                 #gpio-cells = <2>;
 293                 gpio-controller;
 294                 #interrupt-cells = <2>;
 295                 interrupt-controller;
 296         };
 297
 298         pinmux: pinmux {
 299                 compatible = "nvidia,tegra30-pinmux";
 300                 reg = <0x70000868 0xd4    /* Pad control registers */
 301                        0x70003000 0x3e4>; /* Mux registers */
 302         };
 303
 304         /*
 305          * There are two serial driver i.e. 8250 based simple serial
 306          * driver and APB DMA based serial driver for higher baudrate
 307          * and performace. To enable the 8250 based driver, the compatible
 308          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 309          * the APB DMA based serial driver, the comptible is
 310          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 311          */
 312         uarta: serial@70006000 {
 313                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 314                 reg = <0x70006000 0x40>;
 315                 reg-shift = <2>;
 316                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 317                 nvidia,dma-request-selector = <&apbdma 8>;
 318                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 319                 status = "disabled";
 320         };
 321
 322         uartb: serial@70006040 {
 323                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 324                 reg = <0x70006040 0x40>;
 325                 reg-shift = <2>;
 326                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 327                 nvidia,dma-request-selector = <&apbdma 9>;
 328                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 329                 status = "disabled";
 330         };
 331
 332         uartc: serial@70006200 {
 333                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 334                 reg = <0x70006200 0x100>;
 335                 reg-shift = <2>;
 336                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 337                 nvidia,dma-request-selector = <&apbdma 10>;
 338                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 339                 status = "disabled";
 340         };
 341
 342         uartd: serial@70006300 {
 343                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 344                 reg = <0x70006300 0x100>;
 345                 reg-shift = <2>;
 346                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 347                 nvidia,dma-request-selector = <&apbdma 19>;
 348                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 349                 status = "disabled";
 350         };
 351
 352         uarte: serial@70006400 {
 353                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 354                 reg = <0x70006400 0x100>;
 355                 reg-shift = <2>;
 356                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 357                 nvidia,dma-request-selector = <&apbdma 20>;
 358                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 359                 status = "disabled";
 360         };
 361
 362         pwm: pwm {
 363                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 364                 reg = <0x7000a000 0x100>;
 365                 #pwm-cells = <2>;
 366                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 367                 status = "disabled";
 368         };
 369
 370         rtc {
 371                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 372                 reg = <0x7000e000 0x100>;
 373                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 375         };
 376
 377         i2c@7000c000 {
 378                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 379                 reg = <0x7000c000 0x100>;
 380                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 384                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 385                 clock-names = "div-clk", "fast-clk";
 386                 status = "disabled";
 387         };
 388
 389         i2c@7000c400 {
 390                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 391                 reg = <0x7000c400 0x100>;
 392                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 396                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 397                 clock-names = "div-clk", "fast-clk";
 398                 status = "disabled";
 399         };
 400
 401         i2c@7000c500 {
 402                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 403                 reg = <0x7000c500 0x100>;
 404                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 408                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 409                 clock-names = "div-clk", "fast-clk";
 410                 status = "disabled";
 411         };
 412
 413         i2c@7000c700 {
 414                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 415                 reg = <0x7000c700 0x100>;
 416                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 420                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 421                 clock-names = "div-clk", "fast-clk";
 422                 status = "disabled";
 423         };
 424
 425         i2c@7000d000 {
 426                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 427                 reg = <0x7000d000 0x100>;
 428                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 432                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 433                 clock-names = "div-clk", "fast-clk";
 434                 status = "disabled";
 435         };
 436
 437         spi@7000d400 {
 438                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 439                 reg = <0x7000d400 0x200>;
 440                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 441                 nvidia,dma-request-selector = <&apbdma 15>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 445                 status = "disabled";
 446         };
 447
 448         spi@7000d600 {
 449                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 450                 reg = <0x7000d600 0x200>;
 451                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 452                 nvidia,dma-request-selector = <&apbdma 16>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 456                 status = "disabled";
 457         };
 458
 459         spi@7000d800 {
 460                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 461                 reg = <0x7000d800 0x200>;
 462                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 463                 nvidia,dma-request-selector = <&apbdma 17>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 467                 status = "disabled";
 468         };
 469
 470         spi@7000da00 {
 471                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 472                 reg = <0x7000da00 0x200>;
 473                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 474                 nvidia,dma-request-selector = <&apbdma 18>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 478                 status = "disabled";
 479         };
 480
 481         spi@7000dc00 {
 482                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 483                 reg = <0x7000dc00 0x200>;
 484                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 485                 nvidia,dma-request-selector = <&apbdma 27>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 489                 status = "disabled";
 490         };
 491
 492         spi@7000de00 {
 493                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 494                 reg = <0x7000de00 0x200>;
 495                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 496                 nvidia,dma-request-selector = <&apbdma 28>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 500                 status = "disabled";
 501         };
 502
 503         kbc {
 504                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 505                 reg = <0x7000e200 0x100>;
 506                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 508                 status = "disabled";
 509         };
 510
 511         pmc {
 512                 compatible = "nvidia,tegra30-pmc";
 513                 reg = <0x7000e400 0x400>;
 514                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 515                 clock-names = "pclk", "clk32k_in";
 516         };
 517
 518         memory-controller {
 519                 compatible = "nvidia,tegra30-mc";
 520                 reg = <0x7000f000 0x010
 521                        0x7000f03c 0x1b4
 522                        0x7000f200 0x028
 523                        0x7000f284 0x17c>;
 524                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 525         };
 526
 527         iommu {
 528                 compatible = "nvidia,tegra30-smmu";
 529                 reg = <0x7000f010 0x02c
 530                        0x7000f1f0 0x010
 531                        0x7000f228 0x05c>;
 532                 nvidia,#asids = <4>;            /* # of ASIDs */
 533                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 534                 nvidia,ahb = <&ahb>;
 535         };
 536
 537         ahub {
 538                 compatible = "nvidia,tegra30-ahub";
 539                 reg = <0x70080000 0x200
 540                        0x70080200 0x100>;
 541                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 542                 nvidia,dma-request-selector = <&apbdma 1>;
 543                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 544                          <&tegra_car TEGRA30_CLK_APBIF>,
 545                          <&tegra_car TEGRA30_CLK_I2S0>,
 546                          <&tegra_car TEGRA30_CLK_I2S1>,
 547                          <&tegra_car TEGRA30_CLK_I2S2>,
 548                          <&tegra_car TEGRA30_CLK_I2S3>,
 549                          <&tegra_car TEGRA30_CLK_I2S4>,
 550                          <&tegra_car TEGRA30_CLK_DAM0>,
 551                          <&tegra_car TEGRA30_CLK_DAM1>,
 552                          <&tegra_car TEGRA30_CLK_DAM2>,
 553                          <&tegra_car TEGRA30_CLK_SPDIF_IN>;
 554                 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 555                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 556                               "spdif_in";
 557                 ranges;
 558                 #address-cells = <1>;
 559                 #size-cells = <1>;
 560
 561                 tegra_i2s0: i2s@70080300 {
 562                         compatible = "nvidia,tegra30-i2s";
 563                         reg = <0x70080300 0x100>;
 564                         nvidia,ahub-cif-ids = <4 4>;
 565                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 566                         status = "disabled";
 567                 };
 568
 569                 tegra_i2s1: i2s@70080400 {
 570                         compatible = "nvidia,tegra30-i2s";
 571                         reg = <0x70080400 0x100>;
 572                         nvidia,ahub-cif-ids = <5 5>;
 573                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 574                         status = "disabled";
 575                 };
 576
 577                 tegra_i2s2: i2s@70080500 {
 578                         compatible = "nvidia,tegra30-i2s";
 579                         reg = <0x70080500 0x100>;
 580                         nvidia,ahub-cif-ids = <6 6>;
 581                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 582                         status = "disabled";
 583                 };
 584
 585                 tegra_i2s3: i2s@70080600 {
 586                         compatible = "nvidia,tegra30-i2s";
 587                         reg = <0x70080600 0x100>;
 588                         nvidia,ahub-cif-ids = <7 7>;
 589                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 590                         status = "disabled";
 591                 };
 592
 593                 tegra_i2s4: i2s@70080700 {
 594                         compatible = "nvidia,tegra30-i2s";
 595                         reg = <0x70080700 0x100>;
 596                         nvidia,ahub-cif-ids = <8 8>;
 597                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 598                         status = "disabled";
 599                 };
 600         };
 601
 602         sdhci@78000000 {
 603                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 604                 reg = <0x78000000 0x200>;
 605                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 607                 status = "disabled";
 608         };
 609
 610         sdhci@78000200 {
 611                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 612                 reg = <0x78000200 0x200>;
 613                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 615                 status = "disabled";
 616         };
 617
 618         sdhci@78000400 {
 619                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 620                 reg = <0x78000400 0x200>;
 621                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 622                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 623                 status = "disabled";
 624         };
 625
 626         sdhci@78000600 {
 627                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 628                 reg = <0x78000600 0x200>;
 629                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 630                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 631                 status = "disabled";
 632         };
 633
 634         usb@7d000000 {
 635                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 636                 reg = <0x7d000000 0x4000>;
 637                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 638                 phy_type = "utmi";
 639                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 640                 nvidia,needs-double-reset;
 641                 nvidia,phy = <&phy1>;
 642                 status = "disabled";
 643         };
 644
 645         phy1: usb-phy@7d000000 {
 646                 compatible = "nvidia,tegra30-usb-phy";
 647                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 648                 phy_type = "utmi";
 649                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 650                          <&tegra_car TEGRA30_CLK_PLL_U>,
 651                          <&tegra_car TEGRA30_CLK_USBD>;
 652                 clock-names = "reg", "pll_u", "utmi-pads";
 653                 nvidia,hssync-start-delay = <9>;
 654                 nvidia,idle-wait-delay = <17>;
 655                 nvidia,elastic-limit = <16>;
 656                 nvidia,term-range-adj = <6>;
 657                 nvidia,xcvr-setup = <51>;
 658                 nvidia.xcvr-setup-use-fuses;
 659                 nvidia,xcvr-lsfslew = <1>;
 660                 nvidia,xcvr-lsrslew = <1>;
 661                 nvidia,xcvr-hsslew = <32>;
 662                 nvidia,hssquelch-level = <2>;
 663                 nvidia,hsdiscon-level = <5>;
 664                 status = "disabled";
 665         };
 666
 667         usb@7d004000 {
 668                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 669                 reg = <0x7d004000 0x4000>;
 670                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 671                 phy_type = "ulpi";
 672                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 673                 nvidia,phy = <&phy2>;
 674                 status = "disabled";
 675         };
 676
 677         phy2: usb-phy@7d004000 {
 678                 compatible = "nvidia,tegra30-usb-phy";
 679                 reg = <0x7d004000 0x4000>;
 680                 phy_type = "ulpi";
 681                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 682                          <&tegra_car TEGRA30_CLK_PLL_U>,
 683                          <&tegra_car TEGRA30_CLK_CDEV2>;
 684                 clock-names = "reg", "pll_u", "ulpi-link";
 685                 status = "disabled";
 686         };
 687
 688         usb@7d008000 {
 689                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 690                 reg = <0x7d008000 0x4000>;
 691                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 692                 phy_type = "utmi";
 693                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 694                 nvidia,phy = <&phy3>;
 695                 status = "disabled";
 696         };
 697
 698         phy3: usb-phy@7d008000 {
 699                 compatible = "nvidia,tegra30-usb-phy";
 700                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 701                 phy_type = "utmi";
 702                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 703                          <&tegra_car TEGRA30_CLK_PLL_U>,
 704                          <&tegra_car TEGRA30_CLK_USBD>;
 705                 clock-names = "reg", "pll_u", "utmi-pads";
 706                 nvidia,hssync-start-delay = <0>;
 707                 nvidia,idle-wait-delay = <17>;
 708                 nvidia,elastic-limit = <16>;
 709                 nvidia,term-range-adj = <6>;
 710                 nvidia,xcvr-setup = <51>;
 711                 nvidia.xcvr-setup-use-fuses;
 712                 nvidia,xcvr-lsfslew = <2>;
 713                 nvidia,xcvr-lsrslew = <2>;
 714                 nvidia,xcvr-hsslew = <32>;
 715                 nvidia,hssquelch-level = <2>;
 716                 nvidia,hsdiscon-level = <5>;
 717                 status = "disabled";
 718         };
 719
 720         cpus {
 721                 #address-cells = <1>;
 722                 #size-cells = <0>;
 723
 724                 cpu@0 {
 725                         device_type = "cpu";
 726                         compatible = "arm,cortex-a9";
 727                         reg = <0>;
 728                 };
 729
 730                 cpu@1 {
 731                         device_type = "cpu";
 732                         compatible = "arm,cortex-a9";
 733                         reg = <1>;
 734                 };
 735
 736                 cpu@2 {
 737                         device_type = "cpu";
 738                         compatible = "arm,cortex-a9";
 739                         reg = <2>;
 740                 };
 741
 742                 cpu@3 {
 743                         device_type = "cpu";
 744                         compatible = "arm,cortex-a9";
 745                         reg = <3>;
 746                 };
 747         };
 748
 749         pmu {
 750                 compatible = "arm,cortex-a9-pmu";
 751                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 752                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 753                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 754                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 755         };
 756 };