arch/mips/pci/pci.c

   1 /*
   2  * This program is free software; you can redistribute  it and/or modify it
   3  * under  the terms of  the GNU General  Public License as published by the
   4  * Free Software Foundation;  either version 2 of the  License, or (at your
   5  * option) any later version.
   6  *
   7  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
   8  * Copyright (C) 2011 Wind River Systems,
   9  *   written by Ralf Baechle (ralf@linux-mips.org)
  10  */
  11 #include <linux/bug.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mm.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/export.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/of_address.h>
  20
  21 #include <asm/cpu-info.h>
  22
  23 /*
  24  * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
  25  * assignments.
  26  */
  27
  28 /*
  29  * The PCI controller list.
  30  */
  31
  32 static struct pci_controller *hose_head, **hose_tail = &hose_head;
  33
  34 unsigned long PCIBIOS_MIN_IO;
  35 unsigned long PCIBIOS_MIN_MEM;
  36
  37 static int pci_initialized;
  38
  39 /*
  40  * We need to avoid collisions with `mirrored' VGA ports
  41  * and other strange ISA hardware, so we always want the
  42  * addresses to be allocated in the 0x000-0x0ff region
  43  * modulo 0x400.
  44  *
  45  * Why? Because some silly external IO cards only decode
  46  * the low 10 bits of the IO address. The 0x00-0xff region
  47  * is reserved for motherboard devices that decode all 16
  48  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  49  * but we want to try to avoid allocating at 0x2900-0x2bff
  50  * which might have be mirrored at 0x0100-0x03ff..
  51  */
  52 resource_size_t
  53 pcibios_align_resource(void *data, const struct resource *res,
  54                        resource_size_t size, resource_size_t align)
  55 {
  56         struct pci_dev *dev = data;
  57         struct pci_controller *hose = dev->sysdata;
  58         resource_size_t start = res->start;
  59
  60         if (res->flags & IORESOURCE_IO) {
  61                 /* Make sure we start at our min on all hoses */
  62                 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
  63                         start = PCIBIOS_MIN_IO + hose->io_resource->start;
  64
  65                 /*
  66                  * Put everything into 0x00-0xff region modulo 0x400
  67                  */
  68                 if (start & 0x300)
  69                         start = (start + 0x3ff) & ~0x3ff;
  70         } else if (res->flags & IORESOURCE_MEM) {
  71                 /* Make sure we start at our min on all hoses */
  72                 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
  73                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
  74         }
  75
  76         return start;
  77 }
  78
  79 static void pcibios_scanbus(struct pci_controller *hose)
  80 {
  81         static int next_busno;
  82         static int need_domain_info;
  83         LIST_HEAD(resources);
  84         struct pci_bus *bus;
  85
  86         if (!hose->iommu)
  87                 PCI_DMA_BUS_IS_PHYS = 1;
  88
  89         if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
  90                 next_busno = (*hose->get_busno)();
  91
  92         pci_add_resource_offset(&resources,
  93                                 hose->mem_resource, hose->mem_offset);
  94         pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
  95         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
  96                                 &resources);
  97         if (!bus)
  98                 pci_free_resource_list(&resources);
  99
 100         hose->bus = bus;
 101
 102         need_domain_info = need_domain_info || hose->index;
 103         hose->need_domain_info = need_domain_info;
 104         if (bus) {
 105                 next_busno = bus->busn_res.end + 1;
 106                 /* Don't allow 8-bit bus number overflow inside the hose -
 107                    reserve some space for bridges. */
 108                 if (next_busno > 224) {
 109                         next_busno = 0;
 110                         need_domain_info = 1;
 111                 }
 112
 113                 if (!pci_has_flag(PCI_PROBE_ONLY)) {
 114                         pci_bus_size_bridges(bus);
 115                         pci_bus_assign_resources(bus);
 116                 }
 117         }
 118 }
 119
 120 #ifdef CONFIG_OF
 121 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
 122 {
 123         const __be32 *ranges;
 124         int rlen;
 125         int pna = of_n_addr_cells(node);
 126         int np = pna + 5;
 127
 128         pr_info("PCI host bridge %s ranges:\n", node->full_name);
 129         ranges = of_get_property(node, "ranges", &rlen);
 130         if (ranges == NULL)
 131                 return;
 132         hose->of_node = node;
 133
 134         while ((rlen -= np * 4) >= 0) {
 135                 u32 pci_space;
 136                 struct resource *res = NULL;
 137                 u64 addr, size;
 138
 139                 pci_space = be32_to_cpup(&ranges[0]);
 140                 addr = of_translate_address(node, ranges + 3);
 141                 size = of_read_number(ranges + pna + 3, 2);
 142                 ranges += np;
 143                 switch ((pci_space >> 24) & 0x3) {
 144                 case 1:         /* PCI IO space */
 145                         pr_info("  IO 0x%016llx..0x%016llx\n",
 146                                         addr, addr + size - 1);
 147                         hose->io_map_base =
 148                                 (unsigned long)ioremap(addr, size);
 149                         res = hose->io_resource;
 150                         res->flags = IORESOURCE_IO;
 151                         break;
 152                 case 2:         /* PCI Memory space */
 153                 case 3:         /* PCI 64 bits Memory space */
 154                         pr_info(" MEM 0x%016llx..0x%016llx\n",
 155                                         addr, addr + size - 1);
 156                         res = hose->mem_resource;
 157                         res->flags = IORESOURCE_MEM;
 158                         break;
 159                 }
 160                 if (res != NULL) {
 161                         res->start = addr;
 162                         res->name = node->full_name;
 163                         res->end = res->start + size - 1;
 164                         res->parent = NULL;
 165                         res->sibling = NULL;
 166                         res->child = NULL;
 167                 }
 168         }
 169 }
 170
 171 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
 172 {
 173         struct pci_controller *hose = bus->sysdata;
 174
 175         return of_node_get(hose->of_node);
 176 }
 177 #endif
 178
 179 static DEFINE_MUTEX(pci_scan_mutex);
 180
 181 void register_pci_controller(struct pci_controller *hose)
 182 {
 183         struct resource *parent;
 184
 185         parent = hose->mem_resource->parent;
 186         if (!parent)
 187                 parent = &iomem_resource;
 188
 189         if (request_resource(parent, hose->mem_resource) < 0)
 190                 goto out;
 191
 192         parent = hose->io_resource->parent;
 193         if (!parent)
 194                 parent = &ioport_resource;
 195
 196         if (request_resource(parent, hose->io_resource) < 0) {
 197                 release_resource(hose->mem_resource);
 198                 goto out;
 199         }
 200
 201         *hose_tail = hose;
 202         hose_tail = &hose->next;
 203
 204         /*
 205          * Do not panic here but later - this might happen before console init.
 206          */
 207         if (!hose->io_map_base) {
 208                 printk(KERN_WARNING
 209                        "registering PCI controller with io_map_base unset\n");
 210         }
 211
 212         /*
 213          * Scan the bus if it is register after the PCI subsystem
 214          * initialization.
 215          */
 216         if (pci_initialized) {
 217                 mutex_lock(&pci_scan_mutex);
 218                 pcibios_scanbus(hose);
 219                 mutex_unlock(&pci_scan_mutex);
 220         }
 221
 222         return;
 223
 224 out:
 225         printk(KERN_WARNING
 226                "Skipping PCI bus scan due to resource conflict\n");
 227 }
 228
 229 static void __init pcibios_set_cache_line_size(void)
 230 {
 231         struct cpuinfo_mips *c = &current_cpu_data;
 232         unsigned int lsize;
 233
 234         /*
 235          * Set PCI cacheline size to that of the highest level in the
 236          * cache hierarchy.
 237          */
 238         lsize = c->dcache.linesz;
 239         lsize = c->scache.linesz ? : lsize;
 240         lsize = c->tcache.linesz ? : lsize;
 241
 242         BUG_ON(!lsize);
 243
 244         pci_dfl_cache_line_size = lsize >> 2;
 245
 246         pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
 247 }
 248
 249 static int __init pcibios_init(void)
 250 {
 251         struct pci_controller *hose;
 252
 253         pcibios_set_cache_line_size();
 254
 255         /* Scan all of the recorded PCI controllers.  */
 256         for (hose = hose_head; hose; hose = hose->next)
 257                 pcibios_scanbus(hose);
 258
 259         pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
 260
 261         pci_initialized = 1;
 262
 263         return 0;
 264 }
 265
 266 subsys_initcall(pcibios_init);
 267
 268 static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 269 {
 270         u16 cmd, old_cmd;
 271         int idx;
 272         struct resource *r;
 273
 274         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 275         old_cmd = cmd;
 276         for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
 277                 /* Only set up the requested stuff */
 278                 if (!(mask & (1<<idx)))
 279                         continue;
 280
 281                 r = &dev->resource[idx];
 282                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 283                         continue;
 284                 if ((idx == PCI_ROM_RESOURCE) &&
 285                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 286                         continue;
 287                 if (!r->start && r->end) {
 288                         printk(KERN_ERR "PCI: Device %s not available "
 289                                "because of resource collisions\n",
 290                                pci_name(dev));
 291                         return -EINVAL;
 292                 }
 293                 if (r->flags & IORESOURCE_IO)
 294                         cmd |= PCI_COMMAND_IO;
 295                 if (r->flags & IORESOURCE_MEM)
 296                         cmd |= PCI_COMMAND_MEMORY;
 297         }
 298         if (cmd != old_cmd) {
 299                 printk("PCI: Enabling device %s (%04x -> %04x)\n",
 300                        pci_name(dev), old_cmd, cmd);
 301                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 302         }
 303         return 0;
 304 }
 305
 306 unsigned int pcibios_assign_all_busses(void)
 307 {
 308         return 1;
 309 }
 310
 311 int pcibios_enable_device(struct pci_dev *dev, int mask)
 312 {
 313         int err;
 314
 315         if ((err = pcibios_enable_resources(dev, mask)) < 0)
 316                 return err;
 317
 318         return pcibios_plat_dev_init(dev);
 319 }
 320
 321 void pcibios_fixup_bus(struct pci_bus *bus)
 322 {
 323         struct pci_dev *dev = bus->self;
 324
 325         if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
 326             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 327                 pci_read_bridge_bases(bus);
 328         }
 329 }
 330
 331 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 332 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 333
 334 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 335                         enum pci_mmap_state mmap_state, int write_combine)
 336 {
 337         unsigned long prot;
 338
 339         /*
 340          * I/O space can be accessed via normal processor loads and stores on
 341          * this platform but for now we elect not to do this and portable
 342          * drivers should not do this anyway.
 343          */
 344         if (mmap_state == pci_mmap_io)
 345                 return -EINVAL;
 346
 347         /*
 348          * Ignore write-combine; for now only return uncached mappings.
 349          */
 350         prot = pgprot_val(vma->vm_page_prot);
 351         prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
 352         vma->vm_page_prot = __pgprot(prot);
 353
 354         return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 355                 vma->vm_end - vma->vm_start, vma->vm_page_prot);
 356 }
 357
 358 char * (*pcibios_plat_setup)(char *str) __initdata;
 359
 360 char *__init pcibios_setup(char *str)
 361 {
 362         if (pcibios_plat_setup)
 363                 return pcibios_plat_setup(str);
 364         return str;
 365 }