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hpsa: fix bad -ENOMEM return value in hpsa_big_passthru_ioctl
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_mbx.c
bloba9aae500e791b2ade17ad472a462aaa89e88d351
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include "qla_target.h"
9
10 #include <linux/delay.h>
11 #include <linux/gfp.h>
12
13
14 /*
15 * qla2x00_mailbox_command
16 * Issue mailbox command and waits for completion.
17 *
18 * Input:
19 * ha = adapter block pointer.
20 * mcp = driver internal mbx struct pointer.
21 *
22 * Output:
23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
24 *
25 * Returns:
26 * 0 : QLA_SUCCESS = cmd performed success
27 * 1 : QLA_FUNCTION_FAILED (error encountered)
28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
29 *
30 * Context:
31 * Kernel context.
32 */
33 static int
34 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
35 {
36 int rval;
37 unsigned long flags = 0;
38 device_reg_t __iomem *reg;
39 uint8_t abort_active;
40 uint8_t io_lock_on;
41 uint16_t command = 0;
42 uint16_t *iptr;
43 uint16_t __iomem *optr;
44 uint32_t cnt;
45 uint32_t mboxes;
46 unsigned long wait_time;
47 struct qla_hw_data *ha = vha->hw;
48 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
49
50 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
51
52 if (ha->pdev->error_state > pci_channel_io_frozen) {
53 ql_log(ql_log_warn, vha, 0x1001,
54 "error_state is greater than pci_channel_io_frozen, "
55 "exiting.\n");
56 return QLA_FUNCTION_TIMEOUT;
57 }
58
59 if (vha->device_flags & DFLG_DEV_FAILED) {
60 ql_log(ql_log_warn, vha, 0x1002,
61 "Device in failed state, exiting.\n");
62 return QLA_FUNCTION_TIMEOUT;
63 }
64
65 reg = ha->iobase;
66 io_lock_on = base_vha->flags.init_done;
67
68 rval = QLA_SUCCESS;
69 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
70
71
72 if (ha->flags.pci_channel_io_perm_failure) {
73 ql_log(ql_log_warn, vha, 0x1003,
74 "Perm failure on EEH timeout MBX, exiting.\n");
75 return QLA_FUNCTION_TIMEOUT;
76 }
77
78 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
79 /* Setting Link-Down error */
80 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
81 ql_log(ql_log_warn, vha, 0x1004,
82 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
83 return QLA_FUNCTION_TIMEOUT;
84 }
85
86 /*
87 * Wait for active mailbox commands to finish by waiting at most tov
88 * seconds. This is to serialize actual issuing of mailbox cmds during
89 * non ISP abort time.
90 */
91 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
92 /* Timeout occurred. Return error. */
93 ql_log(ql_log_warn, vha, 0x1005,
94 "Cmd access timeout, cmd=0x%x, Exiting.\n",
95 mcp->mb[0]);
96 return QLA_FUNCTION_TIMEOUT;
97 }
98
99 ha->flags.mbox_busy = 1;
100 /* Save mailbox command for debug */
101 ha->mcp = mcp;
102
103 ql_dbg(ql_dbg_mbx, vha, 0x1006,
104 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
105
106 spin_lock_irqsave(&ha->hardware_lock, flags);
107
108 /* Load mailbox registers. */
109 if (IS_P3P_TYPE(ha))
110 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
111 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
112 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
113 else
114 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
115
116 iptr = mcp->mb;
117 command = mcp->mb[0];
118 mboxes = mcp->out_mb;
119
120 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
121 "Mailbox registers (OUT):\n");
122 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
123 if (IS_QLA2200(ha) && cnt == 8)
124 optr =
125 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
126 if (mboxes & BIT_0) {
127 ql_dbg(ql_dbg_mbx, vha, 0x1112,
128 "mbox[%d]<-0x%04x\n", cnt, *iptr);
129 WRT_REG_WORD(optr, *iptr);
130 }
131
132 mboxes >>= 1;
133 optr++;
134 iptr++;
135 }
136
137 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
138 "I/O Address = %p.\n", optr);
139
140 /* Issue set host interrupt command to send cmd out. */
141 ha->flags.mbox_int = 0;
142 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
143
144 /* Unlock mbx registers and wait for interrupt */
145 ql_dbg(ql_dbg_mbx, vha, 0x100f,
146 "Going to unlock irq & waiting for interrupts. "
147 "jiffies=%lx.\n", jiffies);
148
149 /* Wait for mbx cmd completion until timeout */
150
151 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
152 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
153
154 if (IS_P3P_TYPE(ha)) {
155 if (RD_REG_DWORD(&reg->isp82.hint) &
156 HINT_MBX_INT_PENDING) {
157 spin_unlock_irqrestore(&ha->hardware_lock,
158 flags);
159 ha->flags.mbox_busy = 0;
160 ql_dbg(ql_dbg_mbx, vha, 0x1010,
161 "Pending mailbox timeout, exiting.\n");
162 rval = QLA_FUNCTION_TIMEOUT;
163 goto premature_exit;
164 }
165 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
166 } else if (IS_FWI2_CAPABLE(ha))
167 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
168 else
169 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
170 spin_unlock_irqrestore(&ha->hardware_lock, flags);
171
172 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
173 mcp->tov * HZ)) {
174 ql_dbg(ql_dbg_mbx, vha, 0x117a,
175 "cmd=%x Timeout.\n", command);
176 spin_lock_irqsave(&ha->hardware_lock, flags);
177 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
178 spin_unlock_irqrestore(&ha->hardware_lock, flags);
179 }
180 } else {
181 ql_dbg(ql_dbg_mbx, vha, 0x1011,
182 "Cmd=%x Polling Mode.\n", command);
183
184 if (IS_P3P_TYPE(ha)) {
185 if (RD_REG_DWORD(&reg->isp82.hint) &
186 HINT_MBX_INT_PENDING) {
187 spin_unlock_irqrestore(&ha->hardware_lock,
188 flags);
189 ha->flags.mbox_busy = 0;
190 ql_dbg(ql_dbg_mbx, vha, 0x1012,
191 "Pending mailbox timeout, exiting.\n");
192 rval = QLA_FUNCTION_TIMEOUT;
193 goto premature_exit;
194 }
195 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
196 } else if (IS_FWI2_CAPABLE(ha))
197 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
198 else
199 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
200 spin_unlock_irqrestore(&ha->hardware_lock, flags);
201
202 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
203 while (!ha->flags.mbox_int) {
204 if (time_after(jiffies, wait_time))
205 break;
206
207 /* Check for pending interrupts. */
208 qla2x00_poll(ha->rsp_q_map[0]);
209
210 if (!ha->flags.mbox_int &&
211 !(IS_QLA2200(ha) &&
212 command == MBC_LOAD_RISC_RAM_EXTENDED))
213 msleep(10);
214 } /* while */
215 ql_dbg(ql_dbg_mbx, vha, 0x1013,
216 "Waited %d sec.\n",
217 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
218 }
219
220 /* Check whether we timed out */
221 if (ha->flags.mbox_int) {
222 uint16_t *iptr2;
223
224 ql_dbg(ql_dbg_mbx, vha, 0x1014,
225 "Cmd=%x completed.\n", command);
226
227 /* Got interrupt. Clear the flag. */
228 ha->flags.mbox_int = 0;
229 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
230
231 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
232 ha->flags.mbox_busy = 0;
233 /* Setting Link-Down error */
234 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
235 ha->mcp = NULL;
236 rval = QLA_FUNCTION_FAILED;
237 ql_log(ql_log_warn, vha, 0x1015,
238 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
239 goto premature_exit;
240 }
241
242 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
243 rval = QLA_FUNCTION_FAILED;
244
245 /* Load return mailbox registers. */
246 iptr2 = mcp->mb;
247 iptr = (uint16_t *)&ha->mailbox_out[0];
248 mboxes = mcp->in_mb;
249
250 ql_dbg(ql_dbg_mbx, vha, 0x1113,
251 "Mailbox registers (IN):\n");
252 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
253 if (mboxes & BIT_0) {
254 *iptr2 = *iptr;
255 ql_dbg(ql_dbg_mbx, vha, 0x1114,
256 "mbox[%d]->0x%04x\n", cnt, *iptr2);
257 }
258
259 mboxes >>= 1;
260 iptr2++;
261 iptr++;
262 }
263 } else {
264
265 uint16_t mb0;
266 uint32_t ictrl;
267
268 if (IS_FWI2_CAPABLE(ha)) {
269 mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
270 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
271 } else {
272 mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
273 ictrl = RD_REG_WORD(&reg->isp.ictrl);
274 }
275 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
276 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
277 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
278 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
279
280 /*
281 * Attempt to capture a firmware dump for further analysis
282 * of the current firmware state. We do not need to do this
283 * if we are intentionally generating a dump.
284 */
285 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
286 ha->isp_ops->fw_dump(vha, 0);
287
288 rval = QLA_FUNCTION_TIMEOUT;
289 }
290
291 ha->flags.mbox_busy = 0;
292
293 /* Clean up */
294 ha->mcp = NULL;
295
296 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
297 ql_dbg(ql_dbg_mbx, vha, 0x101a,
298 "Checking for additional resp interrupt.\n");
299
300 /* polling mode for non isp_abort commands. */
301 qla2x00_poll(ha->rsp_q_map[0]);
302 }
303
304 if (rval == QLA_FUNCTION_TIMEOUT &&
305 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
306 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
307 ha->flags.eeh_busy) {
308 /* not in dpc. schedule it for dpc to take over. */
309 ql_dbg(ql_dbg_mbx, vha, 0x101b,
310 "Timeout, schedule isp_abort_needed.\n");
311
312 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
313 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
314 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
315 if (IS_QLA82XX(ha)) {
316 ql_dbg(ql_dbg_mbx, vha, 0x112a,
317 "disabling pause transmit on port "
318 "0 & 1.\n");
319 qla82xx_wr_32(ha,
320 QLA82XX_CRB_NIU + 0x98,
321 CRB_NIU_XG_PAUSE_CTL_P0|
322 CRB_NIU_XG_PAUSE_CTL_P1);
323 }
324 ql_log(ql_log_info, base_vha, 0x101c,
325 "Mailbox cmd timeout occurred, cmd=0x%x, "
326 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
327 "abort.\n", command, mcp->mb[0],
328 ha->flags.eeh_busy);
329 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
330 qla2xxx_wake_dpc(vha);
331 }
332 } else if (!abort_active) {
333 /* call abort directly since we are in the DPC thread */
334 ql_dbg(ql_dbg_mbx, vha, 0x101d,
335 "Timeout, calling abort_isp.\n");
336
337 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
338 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
339 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
340 if (IS_QLA82XX(ha)) {
341 ql_dbg(ql_dbg_mbx, vha, 0x112b,
342 "disabling pause transmit on port "
343 "0 & 1.\n");
344 qla82xx_wr_32(ha,
345 QLA82XX_CRB_NIU + 0x98,
346 CRB_NIU_XG_PAUSE_CTL_P0|
347 CRB_NIU_XG_PAUSE_CTL_P1);
348 }
349 ql_log(ql_log_info, base_vha, 0x101e,
350 "Mailbox cmd timeout occurred, cmd=0x%x, "
351 "mb[0]=0x%x. Scheduling ISP abort ",
352 command, mcp->mb[0]);
353 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
354 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
355 /* Allow next mbx cmd to come in. */
356 complete(&ha->mbx_cmd_comp);
357 if (ha->isp_ops->abort_isp(vha)) {
358 /* Failed. retry later. */
359 set_bit(ISP_ABORT_NEEDED,
360 &vha->dpc_flags);
361 }
362 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
363 ql_dbg(ql_dbg_mbx, vha, 0x101f,
364 "Finished abort_isp.\n");
365 goto mbx_done;
366 }
367 }
368 }
369
370 premature_exit:
371 /* Allow next mbx cmd to come in. */
372 complete(&ha->mbx_cmd_comp);
373
374 mbx_done:
375 if (rval) {
376 ql_log(ql_log_warn, base_vha, 0x1020,
377 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
378 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
379 } else {
380 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
381 }
382
383 return rval;
384 }
385
386 int
387 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
388 uint32_t risc_code_size)
389 {
390 int rval;
391 struct qla_hw_data *ha = vha->hw;
392 mbx_cmd_t mc;
393 mbx_cmd_t *mcp = &mc;
394
395 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
396 "Entered %s.\n", __func__);
397
398 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
399 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
400 mcp->mb[8] = MSW(risc_addr);
401 mcp->out_mb = MBX_8|MBX_0;
402 } else {
403 mcp->mb[0] = MBC_LOAD_RISC_RAM;
404 mcp->out_mb = MBX_0;
405 }
406 mcp->mb[1] = LSW(risc_addr);
407 mcp->mb[2] = MSW(req_dma);
408 mcp->mb[3] = LSW(req_dma);
409 mcp->mb[6] = MSW(MSD(req_dma));
410 mcp->mb[7] = LSW(MSD(req_dma));
411 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
412 if (IS_FWI2_CAPABLE(ha)) {
413 mcp->mb[4] = MSW(risc_code_size);
414 mcp->mb[5] = LSW(risc_code_size);
415 mcp->out_mb |= MBX_5|MBX_4;
416 } else {
417 mcp->mb[4] = LSW(risc_code_size);
418 mcp->out_mb |= MBX_4;
419 }
420
421 mcp->in_mb = MBX_0;
422 mcp->tov = MBX_TOV_SECONDS;
423 mcp->flags = 0;
424 rval = qla2x00_mailbox_command(vha, mcp);
425
426 if (rval != QLA_SUCCESS) {
427 ql_dbg(ql_dbg_mbx, vha, 0x1023,
428 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
429 } else {
430 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
431 "Done %s.\n", __func__);
432 }
433
434 return rval;
435 }
436
437 #define EXTENDED_BB_CREDITS BIT_0
438 /*
439 * qla2x00_execute_fw
440 * Start adapter firmware.
441 *
442 * Input:
443 * ha = adapter block pointer.
444 * TARGET_QUEUE_LOCK must be released.
445 * ADAPTER_STATE_LOCK must be released.
446 *
447 * Returns:
448 * qla2x00 local function return status code.
449 *
450 * Context:
451 * Kernel context.
452 */
453 int
454 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
455 {
456 int rval;
457 struct qla_hw_data *ha = vha->hw;
458 mbx_cmd_t mc;
459 mbx_cmd_t *mcp = &mc;
460
461 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
462 "Entered %s.\n", __func__);
463
464 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
465 mcp->out_mb = MBX_0;
466 mcp->in_mb = MBX_0;
467 if (IS_FWI2_CAPABLE(ha)) {
468 mcp->mb[1] = MSW(risc_addr);
469 mcp->mb[2] = LSW(risc_addr);
470 mcp->mb[3] = 0;
471 if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
472 struct nvram_81xx *nv = ha->nvram;
473 mcp->mb[4] = (nv->enhanced_features &
474 EXTENDED_BB_CREDITS);
475 } else
476 mcp->mb[4] = 0;
477 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
478 mcp->in_mb |= MBX_1;
479 } else {
480 mcp->mb[1] = LSW(risc_addr);
481 mcp->out_mb |= MBX_1;
482 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
483 mcp->mb[2] = 0;
484 mcp->out_mb |= MBX_2;
485 }
486 }
487
488 mcp->tov = MBX_TOV_SECONDS;
489 mcp->flags = 0;
490 rval = qla2x00_mailbox_command(vha, mcp);
491
492 if (rval != QLA_SUCCESS) {
493 ql_dbg(ql_dbg_mbx, vha, 0x1026,
494 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
495 } else {
496 if (IS_FWI2_CAPABLE(ha)) {
497 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
498 "Done exchanges=%x.\n", mcp->mb[1]);
499 } else {
500 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
501 "Done %s.\n", __func__);
502 }
503 }
504
505 return rval;
506 }
507
508 /*
509 * qla2x00_get_fw_version
510 * Get firmware version.
511 *
512 * Input:
513 * ha: adapter state pointer.
514 * major: pointer for major number.
515 * minor: pointer for minor number.
516 * subminor: pointer for subminor number.
517 *
518 * Returns:
519 * qla2x00 local function return status code.
520 *
521 * Context:
522 * Kernel context.
523 */
524 int
525 qla2x00_get_fw_version(scsi_qla_host_t *vha)
526 {
527 int rval;
528 mbx_cmd_t mc;
529 mbx_cmd_t *mcp = &mc;
530 struct qla_hw_data *ha = vha->hw;
531
532 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
533 "Entered %s.\n", __func__);
534
535 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
536 mcp->out_mb = MBX_0;
537 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
538 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
539 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
540 if (IS_FWI2_CAPABLE(ha))
541 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
542 mcp->flags = 0;
543 mcp->tov = MBX_TOV_SECONDS;
544 rval = qla2x00_mailbox_command(vha, mcp);
545 if (rval != QLA_SUCCESS)
546 goto failed;
547
548 /* Return mailbox data. */
549 ha->fw_major_version = mcp->mb[1];
550 ha->fw_minor_version = mcp->mb[2];
551 ha->fw_subminor_version = mcp->mb[3];
552 ha->fw_attributes = mcp->mb[6];
553 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
554 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
555 else
556 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
557 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
558 ha->mpi_version[0] = mcp->mb[10] & 0xff;
559 ha->mpi_version[1] = mcp->mb[11] >> 8;
560 ha->mpi_version[2] = mcp->mb[11] & 0xff;
561 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
562 ha->phy_version[0] = mcp->mb[8] & 0xff;
563 ha->phy_version[1] = mcp->mb[9] >> 8;
564 ha->phy_version[2] = mcp->mb[9] & 0xff;
565 }
566 if (IS_FWI2_CAPABLE(ha)) {
567 ha->fw_attributes_h = mcp->mb[15];
568 ha->fw_attributes_ext[0] = mcp->mb[16];
569 ha->fw_attributes_ext[1] = mcp->mb[17];
570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
571 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
572 __func__, mcp->mb[15], mcp->mb[6]);
573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
574 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
575 __func__, mcp->mb[17], mcp->mb[16]);
576 }
577
578 failed:
579 if (rval != QLA_SUCCESS) {
580 /*EMPTY*/
581 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
582 } else {
583 /*EMPTY*/
584 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
585 "Done %s.\n", __func__);
586 }
587 return rval;
588 }
589
590 /*
591 * qla2x00_get_fw_options
592 * Set firmware options.
593 *
594 * Input:
595 * ha = adapter block pointer.
596 * fwopt = pointer for firmware options.
597 *
598 * Returns:
599 * qla2x00 local function return status code.
600 *
601 * Context:
602 * Kernel context.
603 */
604 int
605 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
606 {
607 int rval;
608 mbx_cmd_t mc;
609 mbx_cmd_t *mcp = &mc;
610
611 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
612 "Entered %s.\n", __func__);
613
614 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
615 mcp->out_mb = MBX_0;
616 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
617 mcp->tov = MBX_TOV_SECONDS;
618 mcp->flags = 0;
619 rval = qla2x00_mailbox_command(vha, mcp);
620
621 if (rval != QLA_SUCCESS) {
622 /*EMPTY*/
623 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
624 } else {
625 fwopts[0] = mcp->mb[0];
626 fwopts[1] = mcp->mb[1];
627 fwopts[2] = mcp->mb[2];
628 fwopts[3] = mcp->mb[3];
629
630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
631 "Done %s.\n", __func__);
632 }
633
634 return rval;
635 }
636
637
638 /*
639 * qla2x00_set_fw_options
640 * Set firmware options.
641 *
642 * Input:
643 * ha = adapter block pointer.
644 * fwopt = pointer for firmware options.
645 *
646 * Returns:
647 * qla2x00 local function return status code.
648 *
649 * Context:
650 * Kernel context.
651 */
652 int
653 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
654 {
655 int rval;
656 mbx_cmd_t mc;
657 mbx_cmd_t *mcp = &mc;
658
659 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
660 "Entered %s.\n", __func__);
661
662 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
663 mcp->mb[1] = fwopts[1];
664 mcp->mb[2] = fwopts[2];
665 mcp->mb[3] = fwopts[3];
666 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
667 mcp->in_mb = MBX_0;
668 if (IS_FWI2_CAPABLE(vha->hw)) {
669 mcp->in_mb |= MBX_1;
670 } else {
671 mcp->mb[10] = fwopts[10];
672 mcp->mb[11] = fwopts[11];
673 mcp->mb[12] = 0; /* Undocumented, but used */
674 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
675 }
676 mcp->tov = MBX_TOV_SECONDS;
677 mcp->flags = 0;
678 rval = qla2x00_mailbox_command(vha, mcp);
679
680 fwopts[0] = mcp->mb[0];
681
682 if (rval != QLA_SUCCESS) {
683 /*EMPTY*/
684 ql_dbg(ql_dbg_mbx, vha, 0x1030,
685 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
686 } else {
687 /*EMPTY*/
688 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
689 "Done %s.\n", __func__);
690 }
691
692 return rval;
693 }
694
695 /*
696 * qla2x00_mbx_reg_test
697 * Mailbox register wrap test.
698 *
699 * Input:
700 * ha = adapter block pointer.
701 * TARGET_QUEUE_LOCK must be released.
702 * ADAPTER_STATE_LOCK must be released.
703 *
704 * Returns:
705 * qla2x00 local function return status code.
706 *
707 * Context:
708 * Kernel context.
709 */
710 int
711 qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
712 {
713 int rval;
714 mbx_cmd_t mc;
715 mbx_cmd_t *mcp = &mc;
716
717 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
718 "Entered %s.\n", __func__);
719
720 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
721 mcp->mb[1] = 0xAAAA;
722 mcp->mb[2] = 0x5555;
723 mcp->mb[3] = 0xAA55;
724 mcp->mb[4] = 0x55AA;
725 mcp->mb[5] = 0xA5A5;
726 mcp->mb[6] = 0x5A5A;
727 mcp->mb[7] = 0x2525;
728 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
729 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
730 mcp->tov = MBX_TOV_SECONDS;
731 mcp->flags = 0;
732 rval = qla2x00_mailbox_command(vha, mcp);
733
734 if (rval == QLA_SUCCESS) {
735 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
736 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
737 rval = QLA_FUNCTION_FAILED;
738 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
739 mcp->mb[7] != 0x2525)
740 rval = QLA_FUNCTION_FAILED;
741 }
742
743 if (rval != QLA_SUCCESS) {
744 /*EMPTY*/
745 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
746 } else {
747 /*EMPTY*/
748 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
749 "Done %s.\n", __func__);
750 }
751
752 return rval;
753 }
754
755 /*
756 * qla2x00_verify_checksum
757 * Verify firmware checksum.
758 *
759 * Input:
760 * ha = adapter block pointer.
761 * TARGET_QUEUE_LOCK must be released.
762 * ADAPTER_STATE_LOCK must be released.
763 *
764 * Returns:
765 * qla2x00 local function return status code.
766 *
767 * Context:
768 * Kernel context.
769 */
770 int
771 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
772 {
773 int rval;
774 mbx_cmd_t mc;
775 mbx_cmd_t *mcp = &mc;
776
777 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
778 "Entered %s.\n", __func__);
779
780 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
781 mcp->out_mb = MBX_0;
782 mcp->in_mb = MBX_0;
783 if (IS_FWI2_CAPABLE(vha->hw)) {
784 mcp->mb[1] = MSW(risc_addr);
785 mcp->mb[2] = LSW(risc_addr);
786 mcp->out_mb |= MBX_2|MBX_1;
787 mcp->in_mb |= MBX_2|MBX_1;
788 } else {
789 mcp->mb[1] = LSW(risc_addr);
790 mcp->out_mb |= MBX_1;
791 mcp->in_mb |= MBX_1;
792 }
793
794 mcp->tov = MBX_TOV_SECONDS;
795 mcp->flags = 0;
796 rval = qla2x00_mailbox_command(vha, mcp);
797
798 if (rval != QLA_SUCCESS) {
799 ql_dbg(ql_dbg_mbx, vha, 0x1036,
800 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
801 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
802 } else {
803 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
804 "Done %s.\n", __func__);
805 }
806
807 return rval;
808 }
809
810 /*
811 * qla2x00_issue_iocb
812 * Issue IOCB using mailbox command
813 *
814 * Input:
815 * ha = adapter state pointer.
816 * buffer = buffer pointer.
817 * phys_addr = physical address of buffer.
818 * size = size of buffer.
819 * TARGET_QUEUE_LOCK must be released.
820 * ADAPTER_STATE_LOCK must be released.
821 *
822 * Returns:
823 * qla2x00 local function return status code.
824 *
825 * Context:
826 * Kernel context.
827 */
828 int
829 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
830 dma_addr_t phys_addr, size_t size, uint32_t tov)
831 {
832 int rval;
833 mbx_cmd_t mc;
834 mbx_cmd_t *mcp = &mc;
835
836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
837 "Entered %s.\n", __func__);
838
839 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
840 mcp->mb[1] = 0;
841 mcp->mb[2] = MSW(phys_addr);
842 mcp->mb[3] = LSW(phys_addr);
843 mcp->mb[6] = MSW(MSD(phys_addr));
844 mcp->mb[7] = LSW(MSD(phys_addr));
845 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
846 mcp->in_mb = MBX_2|MBX_0;
847 mcp->tov = tov;
848 mcp->flags = 0;
849 rval = qla2x00_mailbox_command(vha, mcp);
850
851 if (rval != QLA_SUCCESS) {
852 /*EMPTY*/
853 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
854 } else {
855 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
856
857 /* Mask reserved bits. */
858 sts_entry->entry_status &=
859 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
860 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
861 "Done %s.\n", __func__);
862 }
863
864 return rval;
865 }
866
867 int
868 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
869 size_t size)
870 {
871 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
872 MBX_TOV_SECONDS);
873 }
874
875 /*
876 * qla2x00_abort_command
877 * Abort command aborts a specified IOCB.
878 *
879 * Input:
880 * ha = adapter block pointer.
881 * sp = SB structure pointer.
882 *
883 * Returns:
884 * qla2x00 local function return status code.
885 *
886 * Context:
887 * Kernel context.
888 */
889 int
890 qla2x00_abort_command(srb_t *sp)
891 {
892 unsigned long flags = 0;
893 int rval;
894 uint32_t handle = 0;
895 mbx_cmd_t mc;
896 mbx_cmd_t *mcp = &mc;
897 fc_port_t *fcport = sp->fcport;
898 scsi_qla_host_t *vha = fcport->vha;
899 struct qla_hw_data *ha = vha->hw;
900 struct req_que *req = vha->req;
901 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
902
903 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
904 "Entered %s.\n", __func__);
905
906 spin_lock_irqsave(&ha->hardware_lock, flags);
907 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
908 if (req->outstanding_cmds[handle] == sp)
909 break;
910 }
911 spin_unlock_irqrestore(&ha->hardware_lock, flags);
912
913 if (handle == req->num_outstanding_cmds) {
914 /* command not found */
915 return QLA_FUNCTION_FAILED;
916 }
917
918 mcp->mb[0] = MBC_ABORT_COMMAND;
919 if (HAS_EXTENDED_IDS(ha))
920 mcp->mb[1] = fcport->loop_id;
921 else
922 mcp->mb[1] = fcport->loop_id << 8;
923 mcp->mb[2] = (uint16_t)handle;
924 mcp->mb[3] = (uint16_t)(handle >> 16);
925 mcp->mb[6] = (uint16_t)cmd->device->lun;
926 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
927 mcp->in_mb = MBX_0;
928 mcp->tov = MBX_TOV_SECONDS;
929 mcp->flags = 0;
930 rval = qla2x00_mailbox_command(vha, mcp);
931
932 if (rval != QLA_SUCCESS) {
933 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
934 } else {
935 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
936 "Done %s.\n", __func__);
937 }
938
939 return rval;
940 }
941
942 int
943 qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
944 {
945 int rval, rval2;
946 mbx_cmd_t mc;
947 mbx_cmd_t *mcp = &mc;
948 scsi_qla_host_t *vha;
949 struct req_que *req;
950 struct rsp_que *rsp;
951
952 l = l;
953 vha = fcport->vha;
954
955 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
956 "Entered %s.\n", __func__);
957
958 req = vha->hw->req_q_map[0];
959 rsp = req->rsp;
960 mcp->mb[0] = MBC_ABORT_TARGET;
961 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
962 if (HAS_EXTENDED_IDS(vha->hw)) {
963 mcp->mb[1] = fcport->loop_id;
964 mcp->mb[10] = 0;
965 mcp->out_mb |= MBX_10;
966 } else {
967 mcp->mb[1] = fcport->loop_id << 8;
968 }
969 mcp->mb[2] = vha->hw->loop_reset_delay;
970 mcp->mb[9] = vha->vp_idx;
971
972 mcp->in_mb = MBX_0;
973 mcp->tov = MBX_TOV_SECONDS;
974 mcp->flags = 0;
975 rval = qla2x00_mailbox_command(vha, mcp);
976 if (rval != QLA_SUCCESS) {
977 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
978 "Failed=%x.\n", rval);
979 }
980
981 /* Issue marker IOCB. */
982 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
983 MK_SYNC_ID);
984 if (rval2 != QLA_SUCCESS) {
985 ql_dbg(ql_dbg_mbx, vha, 0x1040,
986 "Failed to issue marker IOCB (%x).\n", rval2);
987 } else {
988 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
989 "Done %s.\n", __func__);
990 }
991
992 return rval;
993 }
994
995 int
996 qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
997 {
998 int rval, rval2;
999 mbx_cmd_t mc;
1000 mbx_cmd_t *mcp = &mc;
1001 scsi_qla_host_t *vha;
1002 struct req_que *req;
1003 struct rsp_que *rsp;
1004
1005 vha = fcport->vha;
1006
1007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1008 "Entered %s.\n", __func__);
1009
1010 req = vha->hw->req_q_map[0];
1011 rsp = req->rsp;
1012 mcp->mb[0] = MBC_LUN_RESET;
1013 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
1014 if (HAS_EXTENDED_IDS(vha->hw))
1015 mcp->mb[1] = fcport->loop_id;
1016 else
1017 mcp->mb[1] = fcport->loop_id << 8;
1018 mcp->mb[2] = l;
1019 mcp->mb[3] = 0;
1020 mcp->mb[9] = vha->vp_idx;
1021
1022 mcp->in_mb = MBX_0;
1023 mcp->tov = MBX_TOV_SECONDS;
1024 mcp->flags = 0;
1025 rval = qla2x00_mailbox_command(vha, mcp);
1026 if (rval != QLA_SUCCESS) {
1027 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
1028 }
1029
1030 /* Issue marker IOCB. */
1031 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1032 MK_SYNC_ID_LUN);
1033 if (rval2 != QLA_SUCCESS) {
1034 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1035 "Failed to issue marker IOCB (%x).\n", rval2);
1036 } else {
1037 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1038 "Done %s.\n", __func__);
1039 }
1040
1041 return rval;
1042 }
1043
1044 /*
1045 * qla2x00_get_adapter_id
1046 * Get adapter ID and topology.
1047 *
1048 * Input:
1049 * ha = adapter block pointer.
1050 * id = pointer for loop ID.
1051 * al_pa = pointer for AL_PA.
1052 * area = pointer for area.
1053 * domain = pointer for domain.
1054 * top = pointer for topology.
1055 * TARGET_QUEUE_LOCK must be released.
1056 * ADAPTER_STATE_LOCK must be released.
1057 *
1058 * Returns:
1059 * qla2x00 local function return status code.
1060 *
1061 * Context:
1062 * Kernel context.
1063 */
1064 int
1065 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1066 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1067 {
1068 int rval;
1069 mbx_cmd_t mc;
1070 mbx_cmd_t *mcp = &mc;
1071
1072 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1073 "Entered %s.\n", __func__);
1074
1075 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
1076 mcp->mb[9] = vha->vp_idx;
1077 mcp->out_mb = MBX_9|MBX_0;
1078 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1079 if (IS_CNA_CAPABLE(vha->hw))
1080 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1081 mcp->tov = MBX_TOV_SECONDS;
1082 mcp->flags = 0;
1083 rval = qla2x00_mailbox_command(vha, mcp);
1084 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1085 rval = QLA_COMMAND_ERROR;
1086 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1087 rval = QLA_INVALID_COMMAND;
1088
1089 /* Return data. */
1090 *id = mcp->mb[1];
1091 *al_pa = LSB(mcp->mb[2]);
1092 *area = MSB(mcp->mb[2]);
1093 *domain = LSB(mcp->mb[3]);
1094 *top = mcp->mb[6];
1095 *sw_cap = mcp->mb[7];
1096
1097 if (rval != QLA_SUCCESS) {
1098 /*EMPTY*/
1099 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1100 } else {
1101 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1102 "Done %s.\n", __func__);
1103
1104 if (IS_CNA_CAPABLE(vha->hw)) {
1105 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1106 vha->fcoe_fcf_idx = mcp->mb[10];
1107 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1108 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1109 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1110 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1111 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1112 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1113 }
1114 }
1115
1116 return rval;
1117 }
1118
1119 /*
1120 * qla2x00_get_retry_cnt
1121 * Get current firmware login retry count and delay.
1122 *
1123 * Input:
1124 * ha = adapter block pointer.
1125 * retry_cnt = pointer to login retry count.
1126 * tov = pointer to login timeout value.
1127 *
1128 * Returns:
1129 * qla2x00 local function return status code.
1130 *
1131 * Context:
1132 * Kernel context.
1133 */
1134 int
1135 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1136 uint16_t *r_a_tov)
1137 {
1138 int rval;
1139 uint16_t ratov;
1140 mbx_cmd_t mc;
1141 mbx_cmd_t *mcp = &mc;
1142
1143 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1144 "Entered %s.\n", __func__);
1145
1146 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1147 mcp->out_mb = MBX_0;
1148 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1149 mcp->tov = MBX_TOV_SECONDS;
1150 mcp->flags = 0;
1151 rval = qla2x00_mailbox_command(vha, mcp);
1152
1153 if (rval != QLA_SUCCESS) {
1154 /*EMPTY*/
1155 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1156 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1157 } else {
1158 /* Convert returned data and check our values. */
1159 *r_a_tov = mcp->mb[3] / 2;
1160 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1161 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1162 /* Update to the larger values */
1163 *retry_cnt = (uint8_t)mcp->mb[1];
1164 *tov = ratov;
1165 }
1166
1167 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
1168 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1169 }
1170
1171 return rval;
1172 }
1173
1174 /*
1175 * qla2x00_init_firmware
1176 * Initialize adapter firmware.
1177 *
1178 * Input:
1179 * ha = adapter block pointer.
1180 * dptr = Initialization control block pointer.
1181 * size = size of initialization control block.
1182 * TARGET_QUEUE_LOCK must be released.
1183 * ADAPTER_STATE_LOCK must be released.
1184 *
1185 * Returns:
1186 * qla2x00 local function return status code.
1187 *
1188 * Context:
1189 * Kernel context.
1190 */
1191 int
1192 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1193 {
1194 int rval;
1195 mbx_cmd_t mc;
1196 mbx_cmd_t *mcp = &mc;
1197 struct qla_hw_data *ha = vha->hw;
1198
1199 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1200 "Entered %s.\n", __func__);
1201
1202 if (IS_P3P_TYPE(ha) && ql2xdbwr)
1203 qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
1204 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1205
1206 if (ha->flags.npiv_supported)
1207 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1208 else
1209 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1210
1211 mcp->mb[1] = 0;
1212 mcp->mb[2] = MSW(ha->init_cb_dma);
1213 mcp->mb[3] = LSW(ha->init_cb_dma);
1214 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1215 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1216 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1217 if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
1218 mcp->mb[1] = BIT_0;
1219 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1220 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1221 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1222 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1223 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1224 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1225 }
1226 /* 1 and 2 should normally be captured. */
1227 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1228 if (IS_QLA83XX(ha))
1229 /* mb3 is additional info about the installed SFP. */
1230 mcp->in_mb |= MBX_3;
1231 mcp->buf_size = size;
1232 mcp->flags = MBX_DMA_OUT;
1233 mcp->tov = MBX_TOV_SECONDS;
1234 rval = qla2x00_mailbox_command(vha, mcp);
1235
1236 if (rval != QLA_SUCCESS) {
1237 /*EMPTY*/
1238 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1239 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1240 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1241 } else {
1242 /*EMPTY*/
1243 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1244 "Done %s.\n", __func__);
1245 }
1246
1247 return rval;
1248 }
1249
1250 /*
1251 * qla2x00_get_node_name_list
1252 * Issue get node name list mailbox command, kmalloc()
1253 * and return the resulting list. Caller must kfree() it!
1254 *
1255 * Input:
1256 * ha = adapter state pointer.
1257 * out_data = resulting list
1258 * out_len = length of the resulting list
1259 *
1260 * Returns:
1261 * qla2x00 local function return status code.
1262 *
1263 * Context:
1264 * Kernel context.
1265 */
1266 int
1267 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
1268 {
1269 struct qla_hw_data *ha = vha->hw;
1270 struct qla_port_24xx_data *list = NULL;
1271 void *pmap;
1272 mbx_cmd_t mc;
1273 dma_addr_t pmap_dma;
1274 ulong dma_size;
1275 int rval, left;
1276
1277 left = 1;
1278 while (left > 0) {
1279 dma_size = left * sizeof(*list);
1280 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
1281 &pmap_dma, GFP_KERNEL);
1282 if (!pmap) {
1283 ql_log(ql_log_warn, vha, 0x113f,
1284 "%s(%ld): DMA Alloc failed of %ld\n",
1285 __func__, vha->host_no, dma_size);
1286 rval = QLA_MEMORY_ALLOC_FAILED;
1287 goto out;
1288 }
1289
1290 mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
1291 mc.mb[1] = BIT_1 | BIT_3;
1292 mc.mb[2] = MSW(pmap_dma);
1293 mc.mb[3] = LSW(pmap_dma);
1294 mc.mb[6] = MSW(MSD(pmap_dma));
1295 mc.mb[7] = LSW(MSD(pmap_dma));
1296 mc.mb[8] = dma_size;
1297 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
1298 mc.in_mb = MBX_0|MBX_1;
1299 mc.tov = 30;
1300 mc.flags = MBX_DMA_IN;
1301
1302 rval = qla2x00_mailbox_command(vha, &mc);
1303 if (rval != QLA_SUCCESS) {
1304 if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
1305 (mc.mb[1] == 0xA)) {
1306 left += le16_to_cpu(mc.mb[2]) /
1307 sizeof(struct qla_port_24xx_data);
1308 goto restart;
1309 }
1310 goto out_free;
1311 }
1312
1313 left = 0;
1314
1315 list = kzalloc(dma_size, GFP_KERNEL);
1316 if (!list) {
1317 ql_log(ql_log_warn, vha, 0x1140,
1318 "%s(%ld): failed to allocate node names list "
1319 "structure.\n", __func__, vha->host_no);
1320 rval = QLA_MEMORY_ALLOC_FAILED;
1321 goto out_free;
1322 }
1323
1324 memcpy(list, pmap, dma_size);
1325 restart:
1326 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1327 }
1328
1329 *out_data = list;
1330 *out_len = dma_size;
1331
1332 out:
1333 return rval;
1334
1335 out_free:
1336 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1337 return rval;
1338 }
1339
1340 /*
1341 * qla2x00_get_port_database
1342 * Issue normal/enhanced get port database mailbox command
1343 * and copy device name as necessary.
1344 *
1345 * Input:
1346 * ha = adapter state pointer.
1347 * dev = structure pointer.
1348 * opt = enhanced cmd option byte.
1349 *
1350 * Returns:
1351 * qla2x00 local function return status code.
1352 *
1353 * Context:
1354 * Kernel context.
1355 */
1356 int
1357 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1358 {
1359 int rval;
1360 mbx_cmd_t mc;
1361 mbx_cmd_t *mcp = &mc;
1362 port_database_t *pd;
1363 struct port_database_24xx *pd24;
1364 dma_addr_t pd_dma;
1365 struct qla_hw_data *ha = vha->hw;
1366
1367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1368 "Entered %s.\n", __func__);
1369
1370 pd24 = NULL;
1371 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1372 if (pd == NULL) {
1373 ql_log(ql_log_warn, vha, 0x1050,
1374 "Failed to allocate port database structure.\n");
1375 return QLA_MEMORY_ALLOC_FAILED;
1376 }
1377 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1378
1379 mcp->mb[0] = MBC_GET_PORT_DATABASE;
1380 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1381 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1382 mcp->mb[2] = MSW(pd_dma);
1383 mcp->mb[3] = LSW(pd_dma);
1384 mcp->mb[6] = MSW(MSD(pd_dma));
1385 mcp->mb[7] = LSW(MSD(pd_dma));
1386 mcp->mb[9] = vha->vp_idx;
1387 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1388 mcp->in_mb = MBX_0;
1389 if (IS_FWI2_CAPABLE(ha)) {
1390 mcp->mb[1] = fcport->loop_id;
1391 mcp->mb[10] = opt;
1392 mcp->out_mb |= MBX_10|MBX_1;
1393 mcp->in_mb |= MBX_1;
1394 } else if (HAS_EXTENDED_IDS(ha)) {
1395 mcp->mb[1] = fcport->loop_id;
1396 mcp->mb[10] = opt;
1397 mcp->out_mb |= MBX_10|MBX_1;
1398 } else {
1399 mcp->mb[1] = fcport->loop_id << 8 | opt;
1400 mcp->out_mb |= MBX_1;
1401 }
1402 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1403 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1404 mcp->flags = MBX_DMA_IN;
1405 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1406 rval = qla2x00_mailbox_command(vha, mcp);
1407 if (rval != QLA_SUCCESS)
1408 goto gpd_error_out;
1409
1410 if (IS_FWI2_CAPABLE(ha)) {
1411 uint64_t zero = 0;
1412 pd24 = (struct port_database_24xx *) pd;
1413
1414 /* Check for logged in state. */
1415 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1416 pd24->last_login_state != PDS_PRLI_COMPLETE) {
1417 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1418 "Unable to verify login-state (%x/%x) for "
1419 "loop_id %x.\n", pd24->current_login_state,
1420 pd24->last_login_state, fcport->loop_id);
1421 rval = QLA_FUNCTION_FAILED;
1422 goto gpd_error_out;
1423 }
1424
1425 if (fcport->loop_id == FC_NO_LOOP_ID ||
1426 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1427 memcmp(fcport->port_name, pd24->port_name, 8))) {
1428 /* We lost the device mid way. */
1429 rval = QLA_NOT_LOGGED_IN;
1430 goto gpd_error_out;
1431 }
1432
1433 /* Names are little-endian. */
1434 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1435 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1436
1437 /* Get port_id of device. */
1438 fcport->d_id.b.domain = pd24->port_id[0];
1439 fcport->d_id.b.area = pd24->port_id[1];
1440 fcport->d_id.b.al_pa = pd24->port_id[2];
1441 fcport->d_id.b.rsvd_1 = 0;
1442
1443 /* If not target must be initiator or unknown type. */
1444 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1445 fcport->port_type = FCT_INITIATOR;
1446 else
1447 fcport->port_type = FCT_TARGET;
1448
1449 /* Passback COS information. */
1450 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1451 FC_COS_CLASS2 : FC_COS_CLASS3;
1452
1453 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1454 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1455 } else {
1456 uint64_t zero = 0;
1457
1458 /* Check for logged in state. */
1459 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1460 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
1461 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1462 "Unable to verify login-state (%x/%x) - "
1463 "portid=%02x%02x%02x.\n", pd->master_state,
1464 pd->slave_state, fcport->d_id.b.domain,
1465 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1466 rval = QLA_FUNCTION_FAILED;
1467 goto gpd_error_out;
1468 }
1469
1470 if (fcport->loop_id == FC_NO_LOOP_ID ||
1471 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1472 memcmp(fcport->port_name, pd->port_name, 8))) {
1473 /* We lost the device mid way. */
1474 rval = QLA_NOT_LOGGED_IN;
1475 goto gpd_error_out;
1476 }
1477
1478 /* Names are little-endian. */
1479 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1480 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1481
1482 /* Get port_id of device. */
1483 fcport->d_id.b.domain = pd->port_id[0];
1484 fcport->d_id.b.area = pd->port_id[3];
1485 fcport->d_id.b.al_pa = pd->port_id[2];
1486 fcport->d_id.b.rsvd_1 = 0;
1487
1488 /* If not target must be initiator or unknown type. */
1489 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1490 fcport->port_type = FCT_INITIATOR;
1491 else
1492 fcport->port_type = FCT_TARGET;
1493
1494 /* Passback COS information. */
1495 fcport->supported_classes = (pd->options & BIT_4) ?
1496 FC_COS_CLASS2: FC_COS_CLASS3;
1497 }
1498
1499 gpd_error_out:
1500 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1501
1502 if (rval != QLA_SUCCESS) {
1503 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1504 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1505 mcp->mb[0], mcp->mb[1]);
1506 } else {
1507 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1508 "Done %s.\n", __func__);
1509 }
1510
1511 return rval;
1512 }
1513
1514 /*
1515 * qla2x00_get_firmware_state
1516 * Get adapter firmware state.
1517 *
1518 * Input:
1519 * ha = adapter block pointer.
1520 * dptr = pointer for firmware state.
1521 * TARGET_QUEUE_LOCK must be released.
1522 * ADAPTER_STATE_LOCK must be released.
1523 *
1524 * Returns:
1525 * qla2x00 local function return status code.
1526 *
1527 * Context:
1528 * Kernel context.
1529 */
1530 int
1531 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1532 {
1533 int rval;
1534 mbx_cmd_t mc;
1535 mbx_cmd_t *mcp = &mc;
1536
1537 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1538 "Entered %s.\n", __func__);
1539
1540 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1541 mcp->out_mb = MBX_0;
1542 if (IS_FWI2_CAPABLE(vha->hw))
1543 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1544 else
1545 mcp->in_mb = MBX_1|MBX_0;
1546 mcp->tov = MBX_TOV_SECONDS;
1547 mcp->flags = 0;
1548 rval = qla2x00_mailbox_command(vha, mcp);
1549
1550 /* Return firmware states. */
1551 states[0] = mcp->mb[1];
1552 if (IS_FWI2_CAPABLE(vha->hw)) {
1553 states[1] = mcp->mb[2];
1554 states[2] = mcp->mb[3];
1555 states[3] = mcp->mb[4];
1556 states[4] = mcp->mb[5];
1557 }
1558
1559 if (rval != QLA_SUCCESS) {
1560 /*EMPTY*/
1561 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1562 } else {
1563 /*EMPTY*/
1564 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1565 "Done %s.\n", __func__);
1566 }
1567
1568 return rval;
1569 }
1570
1571 /*
1572 * qla2x00_get_port_name
1573 * Issue get port name mailbox command.
1574 * Returned name is in big endian format.
1575 *
1576 * Input:
1577 * ha = adapter block pointer.
1578 * loop_id = loop ID of device.
1579 * name = pointer for name.
1580 * TARGET_QUEUE_LOCK must be released.
1581 * ADAPTER_STATE_LOCK must be released.
1582 *
1583 * Returns:
1584 * qla2x00 local function return status code.
1585 *
1586 * Context:
1587 * Kernel context.
1588 */
1589 int
1590 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1591 uint8_t opt)
1592 {
1593 int rval;
1594 mbx_cmd_t mc;
1595 mbx_cmd_t *mcp = &mc;
1596
1597 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1598 "Entered %s.\n", __func__);
1599
1600 mcp->mb[0] = MBC_GET_PORT_NAME;
1601 mcp->mb[9] = vha->vp_idx;
1602 mcp->out_mb = MBX_9|MBX_1|MBX_0;
1603 if (HAS_EXTENDED_IDS(vha->hw)) {
1604 mcp->mb[1] = loop_id;
1605 mcp->mb[10] = opt;
1606 mcp->out_mb |= MBX_10;
1607 } else {
1608 mcp->mb[1] = loop_id << 8 | opt;
1609 }
1610
1611 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1612 mcp->tov = MBX_TOV_SECONDS;
1613 mcp->flags = 0;
1614 rval = qla2x00_mailbox_command(vha, mcp);
1615
1616 if (rval != QLA_SUCCESS) {
1617 /*EMPTY*/
1618 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1619 } else {
1620 if (name != NULL) {
1621 /* This function returns name in big endian. */
1622 name[0] = MSB(mcp->mb[2]);
1623 name[1] = LSB(mcp->mb[2]);
1624 name[2] = MSB(mcp->mb[3]);
1625 name[3] = LSB(mcp->mb[3]);
1626 name[4] = MSB(mcp->mb[6]);
1627 name[5] = LSB(mcp->mb[6]);
1628 name[6] = MSB(mcp->mb[7]);
1629 name[7] = LSB(mcp->mb[7]);
1630 }
1631
1632 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1633 "Done %s.\n", __func__);
1634 }
1635
1636 return rval;
1637 }
1638
1639 /*
1640 * qla24xx_link_initialization
1641 * Issue link initialization mailbox command.
1642 *
1643 * Input:
1644 * ha = adapter block pointer.
1645 * TARGET_QUEUE_LOCK must be released.
1646 * ADAPTER_STATE_LOCK must be released.
1647 *
1648 * Returns:
1649 * qla2x00 local function return status code.
1650 *
1651 * Context:
1652 * Kernel context.
1653 */
1654 int
1655 qla24xx_link_initialize(scsi_qla_host_t *vha)
1656 {
1657 int rval;
1658 mbx_cmd_t mc;
1659 mbx_cmd_t *mcp = &mc;
1660
1661 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
1662 "Entered %s.\n", __func__);
1663
1664 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
1665 return QLA_FUNCTION_FAILED;
1666
1667 mcp->mb[0] = MBC_LINK_INITIALIZATION;
1668 mcp->mb[1] = BIT_4;
1669 if (vha->hw->operating_mode == LOOP)
1670 mcp->mb[1] |= BIT_6;
1671 else
1672 mcp->mb[1] |= BIT_5;
1673 mcp->mb[2] = 0;
1674 mcp->mb[3] = 0;
1675 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1676 mcp->in_mb = MBX_0;
1677 mcp->tov = MBX_TOV_SECONDS;
1678 mcp->flags = 0;
1679 rval = qla2x00_mailbox_command(vha, mcp);
1680
1681 if (rval != QLA_SUCCESS) {
1682 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
1683 } else {
1684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
1685 "Done %s.\n", __func__);
1686 }
1687
1688 return rval;
1689 }
1690
1691 /*
1692 * qla2x00_lip_reset
1693 * Issue LIP reset mailbox command.
1694 *
1695 * Input:
1696 * ha = adapter block pointer.
1697 * TARGET_QUEUE_LOCK must be released.
1698 * ADAPTER_STATE_LOCK must be released.
1699 *
1700 * Returns:
1701 * qla2x00 local function return status code.
1702 *
1703 * Context:
1704 * Kernel context.
1705 */
1706 int
1707 qla2x00_lip_reset(scsi_qla_host_t *vha)
1708 {
1709 int rval;
1710 mbx_cmd_t mc;
1711 mbx_cmd_t *mcp = &mc;
1712
1713 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
1714 "Entered %s.\n", __func__);
1715
1716 if (IS_CNA_CAPABLE(vha->hw)) {
1717 /* Logout across all FCFs. */
1718 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1719 mcp->mb[1] = BIT_1;
1720 mcp->mb[2] = 0;
1721 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1722 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1723 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1724 mcp->mb[1] = BIT_6;
1725 mcp->mb[2] = 0;
1726 mcp->mb[3] = vha->hw->loop_reset_delay;
1727 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1728 } else {
1729 mcp->mb[0] = MBC_LIP_RESET;
1730 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1731 if (HAS_EXTENDED_IDS(vha->hw)) {
1732 mcp->mb[1] = 0x00ff;
1733 mcp->mb[10] = 0;
1734 mcp->out_mb |= MBX_10;
1735 } else {
1736 mcp->mb[1] = 0xff00;
1737 }
1738 mcp->mb[2] = vha->hw->loop_reset_delay;
1739 mcp->mb[3] = 0;
1740 }
1741 mcp->in_mb = MBX_0;
1742 mcp->tov = MBX_TOV_SECONDS;
1743 mcp->flags = 0;
1744 rval = qla2x00_mailbox_command(vha, mcp);
1745
1746 if (rval != QLA_SUCCESS) {
1747 /*EMPTY*/
1748 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1749 } else {
1750 /*EMPTY*/
1751 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
1752 "Done %s.\n", __func__);
1753 }
1754
1755 return rval;
1756 }
1757
1758 /*
1759 * qla2x00_send_sns
1760 * Send SNS command.
1761 *
1762 * Input:
1763 * ha = adapter block pointer.
1764 * sns = pointer for command.
1765 * cmd_size = command size.
1766 * buf_size = response/command size.
1767 * TARGET_QUEUE_LOCK must be released.
1768 * ADAPTER_STATE_LOCK must be released.
1769 *
1770 * Returns:
1771 * qla2x00 local function return status code.
1772 *
1773 * Context:
1774 * Kernel context.
1775 */
1776 int
1777 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1778 uint16_t cmd_size, size_t buf_size)
1779 {
1780 int rval;
1781 mbx_cmd_t mc;
1782 mbx_cmd_t *mcp = &mc;
1783
1784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
1785 "Entered %s.\n", __func__);
1786
1787 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
1788 "Retry cnt=%d ratov=%d total tov=%d.\n",
1789 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1790
1791 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1792 mcp->mb[1] = cmd_size;
1793 mcp->mb[2] = MSW(sns_phys_address);
1794 mcp->mb[3] = LSW(sns_phys_address);
1795 mcp->mb[6] = MSW(MSD(sns_phys_address));
1796 mcp->mb[7] = LSW(MSD(sns_phys_address));
1797 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1798 mcp->in_mb = MBX_0|MBX_1;
1799 mcp->buf_size = buf_size;
1800 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
1801 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
1802 rval = qla2x00_mailbox_command(vha, mcp);
1803
1804 if (rval != QLA_SUCCESS) {
1805 /*EMPTY*/
1806 ql_dbg(ql_dbg_mbx, vha, 0x105f,
1807 "Failed=%x mb[0]=%x mb[1]=%x.\n",
1808 rval, mcp->mb[0], mcp->mb[1]);
1809 } else {
1810 /*EMPTY*/
1811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
1812 "Done %s.\n", __func__);
1813 }
1814
1815 return rval;
1816 }
1817
1818 int
1819 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1820 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1821 {
1822 int rval;
1823
1824 struct logio_entry_24xx *lg;
1825 dma_addr_t lg_dma;
1826 uint32_t iop[2];
1827 struct qla_hw_data *ha = vha->hw;
1828 struct req_que *req;
1829 struct rsp_que *rsp;
1830
1831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
1832 "Entered %s.\n", __func__);
1833
1834 if (ha->flags.cpu_affinity_enabled)
1835 req = ha->req_q_map[0];
1836 else
1837 req = vha->req;
1838 rsp = req->rsp;
1839
1840 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1841 if (lg == NULL) {
1842 ql_log(ql_log_warn, vha, 0x1062,
1843 "Failed to allocate login IOCB.\n");
1844 return QLA_MEMORY_ALLOC_FAILED;
1845 }
1846 memset(lg, 0, sizeof(struct logio_entry_24xx));
1847
1848 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1849 lg->entry_count = 1;
1850 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1851 lg->nport_handle = cpu_to_le16(loop_id);
1852 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1853 if (opt & BIT_0)
1854 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
1855 if (opt & BIT_1)
1856 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1857 lg->port_id[0] = al_pa;
1858 lg->port_id[1] = area;
1859 lg->port_id[2] = domain;
1860 lg->vp_index = vha->vp_idx;
1861 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
1862 (ha->r_a_tov / 10 * 2) + 2);
1863 if (rval != QLA_SUCCESS) {
1864 ql_dbg(ql_dbg_mbx, vha, 0x1063,
1865 "Failed to issue login IOCB (%x).\n", rval);
1866 } else if (lg->entry_status != 0) {
1867 ql_dbg(ql_dbg_mbx, vha, 0x1064,
1868 "Failed to complete IOCB -- error status (%x).\n",
1869 lg->entry_status);
1870 rval = QLA_FUNCTION_FAILED;
1871 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1872 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1873 iop[1] = le32_to_cpu(lg->io_parameter[1]);
1874
1875 ql_dbg(ql_dbg_mbx, vha, 0x1065,
1876 "Failed to complete IOCB -- completion status (%x) "
1877 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1878 iop[0], iop[1]);
1879
1880 switch (iop[0]) {
1881 case LSC_SCODE_PORTID_USED:
1882 mb[0] = MBS_PORT_ID_USED;
1883 mb[1] = LSW(iop[1]);
1884 break;
1885 case LSC_SCODE_NPORT_USED:
1886 mb[0] = MBS_LOOP_ID_USED;
1887 break;
1888 case LSC_SCODE_NOLINK:
1889 case LSC_SCODE_NOIOCB:
1890 case LSC_SCODE_NOXCB:
1891 case LSC_SCODE_CMD_FAILED:
1892 case LSC_SCODE_NOFABRIC:
1893 case LSC_SCODE_FW_NOT_READY:
1894 case LSC_SCODE_NOT_LOGGED_IN:
1895 case LSC_SCODE_NOPCB:
1896 case LSC_SCODE_ELS_REJECT:
1897 case LSC_SCODE_CMD_PARAM_ERR:
1898 case LSC_SCODE_NONPORT:
1899 case LSC_SCODE_LOGGED_IN:
1900 case LSC_SCODE_NOFLOGI_ACC:
1901 default:
1902 mb[0] = MBS_COMMAND_ERROR;
1903 break;
1904 }
1905 } else {
1906 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
1907 "Done %s.\n", __func__);
1908
1909 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1910
1911 mb[0] = MBS_COMMAND_COMPLETE;
1912 mb[1] = 0;
1913 if (iop[0] & BIT_4) {
1914 if (iop[0] & BIT_8)
1915 mb[1] |= BIT_1;
1916 } else
1917 mb[1] = BIT_0;
1918
1919 /* Passback COS information. */
1920 mb[10] = 0;
1921 if (lg->io_parameter[7] || lg->io_parameter[8])
1922 mb[10] |= BIT_0; /* Class 2. */
1923 if (lg->io_parameter[9] || lg->io_parameter[10])
1924 mb[10] |= BIT_1; /* Class 3. */
1925 if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
1926 mb[10] |= BIT_7; /* Confirmed Completion
1927 * Allowed
1928 */
1929 }
1930
1931 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1932
1933 return rval;
1934 }
1935
1936 /*
1937 * qla2x00_login_fabric
1938 * Issue login fabric port mailbox command.
1939 *
1940 * Input:
1941 * ha = adapter block pointer.
1942 * loop_id = device loop ID.
1943 * domain = device domain.
1944 * area = device area.
1945 * al_pa = device AL_PA.
1946 * status = pointer for return status.
1947 * opt = command options.
1948 * TARGET_QUEUE_LOCK must be released.
1949 * ADAPTER_STATE_LOCK must be released.
1950 *
1951 * Returns:
1952 * qla2x00 local function return status code.
1953 *
1954 * Context:
1955 * Kernel context.
1956 */
1957 int
1958 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1959 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1960 {
1961 int rval;
1962 mbx_cmd_t mc;
1963 mbx_cmd_t *mcp = &mc;
1964 struct qla_hw_data *ha = vha->hw;
1965
1966 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
1967 "Entered %s.\n", __func__);
1968
1969 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
1970 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1971 if (HAS_EXTENDED_IDS(ha)) {
1972 mcp->mb[1] = loop_id;
1973 mcp->mb[10] = opt;
1974 mcp->out_mb |= MBX_10;
1975 } else {
1976 mcp->mb[1] = (loop_id << 8) | opt;
1977 }
1978 mcp->mb[2] = domain;
1979 mcp->mb[3] = area << 8 | al_pa;
1980
1981 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
1982 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1983 mcp->flags = 0;
1984 rval = qla2x00_mailbox_command(vha, mcp);
1985
1986 /* Return mailbox statuses. */
1987 if (mb != NULL) {
1988 mb[0] = mcp->mb[0];
1989 mb[1] = mcp->mb[1];
1990 mb[2] = mcp->mb[2];
1991 mb[6] = mcp->mb[6];
1992 mb[7] = mcp->mb[7];
1993 /* COS retrieved from Get-Port-Database mailbox command. */
1994 mb[10] = 0;
1995 }
1996
1997 if (rval != QLA_SUCCESS) {
1998 /* RLU tmp code: need to change main mailbox_command function to
1999 * return ok even when the mailbox completion value is not
2000 * SUCCESS. The caller needs to be responsible to interpret
2001 * the return values of this mailbox command if we're not
2002 * to change too much of the existing code.
2003 */
2004 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2005 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2006 mcp->mb[0] == 0x4006)
2007 rval = QLA_SUCCESS;
2008
2009 /*EMPTY*/
2010 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2011 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2012 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
2013 } else {
2014 /*EMPTY*/
2015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2016 "Done %s.\n", __func__);
2017 }
2018
2019 return rval;
2020 }
2021
2022 /*
2023 * qla2x00_login_local_device
2024 * Issue login loop port mailbox command.
2025 *
2026 * Input:
2027 * ha = adapter block pointer.
2028 * loop_id = device loop ID.
2029 * opt = command options.
2030 *
2031 * Returns:
2032 * Return status code.
2033 *
2034 * Context:
2035 * Kernel context.
2036 *
2037 */
2038 int
2039 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
2040 uint16_t *mb_ret, uint8_t opt)
2041 {
2042 int rval;
2043 mbx_cmd_t mc;
2044 mbx_cmd_t *mcp = &mc;
2045 struct qla_hw_data *ha = vha->hw;
2046
2047 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2048 "Entered %s.\n", __func__);
2049
2050 if (IS_FWI2_CAPABLE(ha))
2051 return qla24xx_login_fabric(vha, fcport->loop_id,
2052 fcport->d_id.b.domain, fcport->d_id.b.area,
2053 fcport->d_id.b.al_pa, mb_ret, opt);
2054
2055 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2056 if (HAS_EXTENDED_IDS(ha))
2057 mcp->mb[1] = fcport->loop_id;
2058 else
2059 mcp->mb[1] = fcport->loop_id << 8;
2060 mcp->mb[2] = opt;
2061 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2062 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2063 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2064 mcp->flags = 0;
2065 rval = qla2x00_mailbox_command(vha, mcp);
2066
2067 /* Return mailbox statuses. */
2068 if (mb_ret != NULL) {
2069 mb_ret[0] = mcp->mb[0];
2070 mb_ret[1] = mcp->mb[1];
2071 mb_ret[6] = mcp->mb[6];
2072 mb_ret[7] = mcp->mb[7];
2073 }
2074
2075 if (rval != QLA_SUCCESS) {
2076 /* AV tmp code: need to change main mailbox_command function to
2077 * return ok even when the mailbox completion value is not
2078 * SUCCESS. The caller needs to be responsible to interpret
2079 * the return values of this mailbox command if we're not
2080 * to change too much of the existing code.
2081 */
2082 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2083 rval = QLA_SUCCESS;
2084
2085 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2086 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2087 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
2088 } else {
2089 /*EMPTY*/
2090 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2091 "Done %s.\n", __func__);
2092 }
2093
2094 return (rval);
2095 }
2096
2097 int
2098 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2099 uint8_t area, uint8_t al_pa)
2100 {
2101 int rval;
2102 struct logio_entry_24xx *lg;
2103 dma_addr_t lg_dma;
2104 struct qla_hw_data *ha = vha->hw;
2105 struct req_que *req;
2106 struct rsp_que *rsp;
2107
2108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2109 "Entered %s.\n", __func__);
2110
2111 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2112 if (lg == NULL) {
2113 ql_log(ql_log_warn, vha, 0x106e,
2114 "Failed to allocate logout IOCB.\n");
2115 return QLA_MEMORY_ALLOC_FAILED;
2116 }
2117 memset(lg, 0, sizeof(struct logio_entry_24xx));
2118
2119 if (ql2xmaxqueues > 1)
2120 req = ha->req_q_map[0];
2121 else
2122 req = vha->req;
2123 rsp = req->rsp;
2124 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2125 lg->entry_count = 1;
2126 lg->handle = MAKE_HANDLE(req->id, lg->handle);
2127 lg->nport_handle = cpu_to_le16(loop_id);
2128 lg->control_flags =
2129 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2130 LCF_FREE_NPORT);
2131 lg->port_id[0] = al_pa;
2132 lg->port_id[1] = area;
2133 lg->port_id[2] = domain;
2134 lg->vp_index = vha->vp_idx;
2135 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2136 (ha->r_a_tov / 10 * 2) + 2);
2137 if (rval != QLA_SUCCESS) {
2138 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2139 "Failed to issue logout IOCB (%x).\n", rval);
2140 } else if (lg->entry_status != 0) {
2141 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2142 "Failed to complete IOCB -- error status (%x).\n",
2143 lg->entry_status);
2144 rval = QLA_FUNCTION_FAILED;
2145 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
2146 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2147 "Failed to complete IOCB -- completion status (%x) "
2148 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2149 le32_to_cpu(lg->io_parameter[0]),
2150 le32_to_cpu(lg->io_parameter[1]));
2151 } else {
2152 /*EMPTY*/
2153 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2154 "Done %s.\n", __func__);
2155 }
2156
2157 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2158
2159 return rval;
2160 }
2161
2162 /*
2163 * qla2x00_fabric_logout
2164 * Issue logout fabric port mailbox command.
2165 *
2166 * Input:
2167 * ha = adapter block pointer.
2168 * loop_id = device loop ID.
2169 * TARGET_QUEUE_LOCK must be released.
2170 * ADAPTER_STATE_LOCK must be released.
2171 *
2172 * Returns:
2173 * qla2x00 local function return status code.
2174 *
2175 * Context:
2176 * Kernel context.
2177 */
2178 int
2179 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2180 uint8_t area, uint8_t al_pa)
2181 {
2182 int rval;
2183 mbx_cmd_t mc;
2184 mbx_cmd_t *mcp = &mc;
2185
2186 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2187 "Entered %s.\n", __func__);
2188
2189 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2190 mcp->out_mb = MBX_1|MBX_0;
2191 if (HAS_EXTENDED_IDS(vha->hw)) {
2192 mcp->mb[1] = loop_id;
2193 mcp->mb[10] = 0;
2194 mcp->out_mb |= MBX_10;
2195 } else {
2196 mcp->mb[1] = loop_id << 8;
2197 }
2198
2199 mcp->in_mb = MBX_1|MBX_0;
2200 mcp->tov = MBX_TOV_SECONDS;
2201 mcp->flags = 0;
2202 rval = qla2x00_mailbox_command(vha, mcp);
2203
2204 if (rval != QLA_SUCCESS) {
2205 /*EMPTY*/
2206 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2207 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
2208 } else {
2209 /*EMPTY*/
2210 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2211 "Done %s.\n", __func__);
2212 }
2213
2214 return rval;
2215 }
2216
2217 /*
2218 * qla2x00_full_login_lip
2219 * Issue full login LIP mailbox command.
2220 *
2221 * Input:
2222 * ha = adapter block pointer.
2223 * TARGET_QUEUE_LOCK must be released.
2224 * ADAPTER_STATE_LOCK must be released.
2225 *
2226 * Returns:
2227 * qla2x00 local function return status code.
2228 *
2229 * Context:
2230 * Kernel context.
2231 */
2232 int
2233 qla2x00_full_login_lip(scsi_qla_host_t *vha)
2234 {
2235 int rval;
2236 mbx_cmd_t mc;
2237 mbx_cmd_t *mcp = &mc;
2238
2239 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2240 "Entered %s.\n", __func__);
2241
2242 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2243 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
2244 mcp->mb[2] = 0;
2245 mcp->mb[3] = 0;
2246 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2247 mcp->in_mb = MBX_0;
2248 mcp->tov = MBX_TOV_SECONDS;
2249 mcp->flags = 0;
2250 rval = qla2x00_mailbox_command(vha, mcp);
2251
2252 if (rval != QLA_SUCCESS) {
2253 /*EMPTY*/
2254 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
2255 } else {
2256 /*EMPTY*/
2257 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2258 "Done %s.\n", __func__);
2259 }
2260
2261 return rval;
2262 }
2263
2264 /*
2265 * qla2x00_get_id_list
2266 *
2267 * Input:
2268 * ha = adapter block pointer.
2269 *
2270 * Returns:
2271 * qla2x00 local function return status code.
2272 *
2273 * Context:
2274 * Kernel context.
2275 */
2276 int
2277 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
2278 uint16_t *entries)
2279 {
2280 int rval;
2281 mbx_cmd_t mc;
2282 mbx_cmd_t *mcp = &mc;
2283
2284 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2285 "Entered %s.\n", __func__);
2286
2287 if (id_list == NULL)
2288 return QLA_FUNCTION_FAILED;
2289
2290 mcp->mb[0] = MBC_GET_ID_LIST;
2291 mcp->out_mb = MBX_0;
2292 if (IS_FWI2_CAPABLE(vha->hw)) {
2293 mcp->mb[2] = MSW(id_list_dma);
2294 mcp->mb[3] = LSW(id_list_dma);
2295 mcp->mb[6] = MSW(MSD(id_list_dma));
2296 mcp->mb[7] = LSW(MSD(id_list_dma));
2297 mcp->mb[8] = 0;
2298 mcp->mb[9] = vha->vp_idx;
2299 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
2300 } else {
2301 mcp->mb[1] = MSW(id_list_dma);
2302 mcp->mb[2] = LSW(id_list_dma);
2303 mcp->mb[3] = MSW(MSD(id_list_dma));
2304 mcp->mb[6] = LSW(MSD(id_list_dma));
2305 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2306 }
2307 mcp->in_mb = MBX_1|MBX_0;
2308 mcp->tov = MBX_TOV_SECONDS;
2309 mcp->flags = 0;
2310 rval = qla2x00_mailbox_command(vha, mcp);
2311
2312 if (rval != QLA_SUCCESS) {
2313 /*EMPTY*/
2314 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
2315 } else {
2316 *entries = mcp->mb[1];
2317 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2318 "Done %s.\n", __func__);
2319 }
2320
2321 return rval;
2322 }
2323
2324 /*
2325 * qla2x00_get_resource_cnts
2326 * Get current firmware resource counts.
2327 *
2328 * Input:
2329 * ha = adapter block pointer.
2330 *
2331 * Returns:
2332 * qla2x00 local function return status code.
2333 *
2334 * Context:
2335 * Kernel context.
2336 */
2337 int
2338 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
2339 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
2340 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
2341 {
2342 int rval;
2343 mbx_cmd_t mc;
2344 mbx_cmd_t *mcp = &mc;
2345
2346 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2347 "Entered %s.\n", __func__);
2348
2349 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2350 mcp->out_mb = MBX_0;
2351 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2352 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
2353 mcp->in_mb |= MBX_12;
2354 mcp->tov = MBX_TOV_SECONDS;
2355 mcp->flags = 0;
2356 rval = qla2x00_mailbox_command(vha, mcp);
2357
2358 if (rval != QLA_SUCCESS) {
2359 /*EMPTY*/
2360 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2361 "Failed mb[0]=%x.\n", mcp->mb[0]);
2362 } else {
2363 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
2364 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2365 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2366 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2367 mcp->mb[11], mcp->mb[12]);
2368
2369 if (cur_xchg_cnt)
2370 *cur_xchg_cnt = mcp->mb[3];
2371 if (orig_xchg_cnt)
2372 *orig_xchg_cnt = mcp->mb[6];
2373 if (cur_iocb_cnt)
2374 *cur_iocb_cnt = mcp->mb[7];
2375 if (orig_iocb_cnt)
2376 *orig_iocb_cnt = mcp->mb[10];
2377 if (vha->hw->flags.npiv_supported && max_npiv_vports)
2378 *max_npiv_vports = mcp->mb[11];
2379 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
2380 *max_fcfs = mcp->mb[12];
2381 }
2382
2383 return (rval);
2384 }
2385
2386 /*
2387 * qla2x00_get_fcal_position_map
2388 * Get FCAL (LILP) position map using mailbox command
2389 *
2390 * Input:
2391 * ha = adapter state pointer.
2392 * pos_map = buffer pointer (can be NULL).
2393 *
2394 * Returns:
2395 * qla2x00 local function return status code.
2396 *
2397 * Context:
2398 * Kernel context.
2399 */
2400 int
2401 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
2402 {
2403 int rval;
2404 mbx_cmd_t mc;
2405 mbx_cmd_t *mcp = &mc;
2406 char *pmap;
2407 dma_addr_t pmap_dma;
2408 struct qla_hw_data *ha = vha->hw;
2409
2410 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2411 "Entered %s.\n", __func__);
2412
2413 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
2414 if (pmap == NULL) {
2415 ql_log(ql_log_warn, vha, 0x1080,
2416 "Memory alloc failed.\n");
2417 return QLA_MEMORY_ALLOC_FAILED;
2418 }
2419 memset(pmap, 0, FCAL_MAP_SIZE);
2420
2421 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2422 mcp->mb[2] = MSW(pmap_dma);
2423 mcp->mb[3] = LSW(pmap_dma);
2424 mcp->mb[6] = MSW(MSD(pmap_dma));
2425 mcp->mb[7] = LSW(MSD(pmap_dma));
2426 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2427 mcp->in_mb = MBX_1|MBX_0;
2428 mcp->buf_size = FCAL_MAP_SIZE;
2429 mcp->flags = MBX_DMA_IN;
2430 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2431 rval = qla2x00_mailbox_command(vha, mcp);
2432
2433 if (rval == QLA_SUCCESS) {
2434 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
2435 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2436 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2437 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2438 pmap, pmap[0] + 1);
2439
2440 if (pos_map)
2441 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2442 }
2443 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2444
2445 if (rval != QLA_SUCCESS) {
2446 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
2447 } else {
2448 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2449 "Done %s.\n", __func__);
2450 }
2451
2452 return rval;
2453 }
2454
2455 /*
2456 * qla2x00_get_link_status
2457 *
2458 * Input:
2459 * ha = adapter block pointer.
2460 * loop_id = device loop ID.
2461 * ret_buf = pointer to link status return buffer.
2462 *
2463 * Returns:
2464 * 0 = success.
2465 * BIT_0 = mem alloc error.
2466 * BIT_1 = mailbox error.
2467 */
2468 int
2469 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
2470 struct link_statistics *stats, dma_addr_t stats_dma)
2471 {
2472 int rval;
2473 mbx_cmd_t mc;
2474 mbx_cmd_t *mcp = &mc;
2475 uint32_t *siter, *diter, dwords;
2476 struct qla_hw_data *ha = vha->hw;
2477
2478 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2479 "Entered %s.\n", __func__);
2480
2481 mcp->mb[0] = MBC_GET_LINK_STATUS;
2482 mcp->mb[2] = MSW(stats_dma);
2483 mcp->mb[3] = LSW(stats_dma);
2484 mcp->mb[6] = MSW(MSD(stats_dma));
2485 mcp->mb[7] = LSW(MSD(stats_dma));
2486 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2487 mcp->in_mb = MBX_0;
2488 if (IS_FWI2_CAPABLE(ha)) {
2489 mcp->mb[1] = loop_id;
2490 mcp->mb[4] = 0;
2491 mcp->mb[10] = 0;
2492 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2493 mcp->in_mb |= MBX_1;
2494 } else if (HAS_EXTENDED_IDS(ha)) {
2495 mcp->mb[1] = loop_id;
2496 mcp->mb[10] = 0;
2497 mcp->out_mb |= MBX_10|MBX_1;
2498 } else {
2499 mcp->mb[1] = loop_id << 8;
2500 mcp->out_mb |= MBX_1;
2501 }
2502 mcp->tov = MBX_TOV_SECONDS;
2503 mcp->flags = IOCTL_CMD;
2504 rval = qla2x00_mailbox_command(vha, mcp);
2505
2506 if (rval == QLA_SUCCESS) {
2507 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2508 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2509 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2510 rval = QLA_FUNCTION_FAILED;
2511 } else {
2512 /* Copy over data -- firmware data is LE. */
2513 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2514 "Done %s.\n", __func__);
2515 dwords = offsetof(struct link_statistics, unused1) / 4;
2516 siter = diter = &stats->link_fail_cnt;
2517 while (dwords--)
2518 *diter++ = le32_to_cpu(*siter++);
2519 }
2520 } else {
2521 /* Failed. */
2522 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
2523 }
2524
2525 return rval;
2526 }
2527
2528 int
2529 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
2530 dma_addr_t stats_dma)
2531 {
2532 int rval;
2533 mbx_cmd_t mc;
2534 mbx_cmd_t *mcp = &mc;
2535 uint32_t *siter, *diter, dwords;
2536
2537 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2538 "Entered %s.\n", __func__);
2539
2540 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
2541 mcp->mb[2] = MSW(stats_dma);
2542 mcp->mb[3] = LSW(stats_dma);
2543 mcp->mb[6] = MSW(MSD(stats_dma));
2544 mcp->mb[7] = LSW(MSD(stats_dma));
2545 mcp->mb[8] = sizeof(struct link_statistics) / 4;
2546 mcp->mb[9] = vha->vp_idx;
2547 mcp->mb[10] = 0;
2548 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2549 mcp->in_mb = MBX_2|MBX_1|MBX_0;
2550 mcp->tov = MBX_TOV_SECONDS;
2551 mcp->flags = IOCTL_CMD;
2552 rval = qla2x00_mailbox_command(vha, mcp);
2553
2554 if (rval == QLA_SUCCESS) {
2555 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2556 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2557 "Failed mb[0]=%x.\n", mcp->mb[0]);
2558 rval = QLA_FUNCTION_FAILED;
2559 } else {
2560 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2561 "Done %s.\n", __func__);
2562 /* Copy over data -- firmware data is LE. */
2563 dwords = sizeof(struct link_statistics) / 4;
2564 siter = diter = &stats->link_fail_cnt;
2565 while (dwords--)
2566 *diter++ = le32_to_cpu(*siter++);
2567 }
2568 } else {
2569 /* Failed. */
2570 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
2571 }
2572
2573 return rval;
2574 }
2575
2576 int
2577 qla24xx_abort_command(srb_t *sp)
2578 {
2579 int rval;
2580 unsigned long flags = 0;
2581
2582 struct abort_entry_24xx *abt;
2583 dma_addr_t abt_dma;
2584 uint32_t handle;
2585 fc_port_t *fcport = sp->fcport;
2586 struct scsi_qla_host *vha = fcport->vha;
2587 struct qla_hw_data *ha = vha->hw;
2588 struct req_que *req = vha->req;
2589
2590 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2591 "Entered %s.\n", __func__);
2592
2593 spin_lock_irqsave(&ha->hardware_lock, flags);
2594 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
2595 if (req->outstanding_cmds[handle] == sp)
2596 break;
2597 }
2598 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2599 if (handle == req->num_outstanding_cmds) {
2600 /* Command not found. */
2601 return QLA_FUNCTION_FAILED;
2602 }
2603
2604 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2605 if (abt == NULL) {
2606 ql_log(ql_log_warn, vha, 0x108d,
2607 "Failed to allocate abort IOCB.\n");
2608 return QLA_MEMORY_ALLOC_FAILED;
2609 }
2610 memset(abt, 0, sizeof(struct abort_entry_24xx));
2611
2612 abt->entry_type = ABORT_IOCB_TYPE;
2613 abt->entry_count = 1;
2614 abt->handle = MAKE_HANDLE(req->id, abt->handle);
2615 abt->nport_handle = cpu_to_le16(fcport->loop_id);
2616 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
2617 abt->port_id[0] = fcport->d_id.b.al_pa;
2618 abt->port_id[1] = fcport->d_id.b.area;
2619 abt->port_id[2] = fcport->d_id.b.domain;
2620 abt->vp_index = fcport->vha->vp_idx;
2621
2622 abt->req_que_no = cpu_to_le16(req->id);
2623
2624 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
2625 if (rval != QLA_SUCCESS) {
2626 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2627 "Failed to issue IOCB (%x).\n", rval);
2628 } else if (abt->entry_status != 0) {
2629 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2630 "Failed to complete IOCB -- error status (%x).\n",
2631 abt->entry_status);
2632 rval = QLA_FUNCTION_FAILED;
2633 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
2634 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2635 "Failed to complete IOCB -- completion status (%x).\n",
2636 le16_to_cpu(abt->nport_handle));
2637 rval = QLA_FUNCTION_FAILED;
2638 } else {
2639 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2640 "Done %s.\n", __func__);
2641 }
2642
2643 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2644
2645 return rval;
2646 }
2647
2648 struct tsk_mgmt_cmd {
2649 union {
2650 struct tsk_mgmt_entry tsk;
2651 struct sts_entry_24xx sts;
2652 } p;
2653 };
2654
2655 static int
2656 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
2657 unsigned int l, int tag)
2658 {
2659 int rval, rval2;
2660 struct tsk_mgmt_cmd *tsk;
2661 struct sts_entry_24xx *sts;
2662 dma_addr_t tsk_dma;
2663 scsi_qla_host_t *vha;
2664 struct qla_hw_data *ha;
2665 struct req_que *req;
2666 struct rsp_que *rsp;
2667
2668 vha = fcport->vha;
2669 ha = vha->hw;
2670 req = vha->req;
2671
2672 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
2673 "Entered %s.\n", __func__);
2674
2675 if (ha->flags.cpu_affinity_enabled)
2676 rsp = ha->rsp_q_map[tag + 1];
2677 else
2678 rsp = req->rsp;
2679 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
2680 if (tsk == NULL) {
2681 ql_log(ql_log_warn, vha, 0x1093,
2682 "Failed to allocate task management IOCB.\n");
2683 return QLA_MEMORY_ALLOC_FAILED;
2684 }
2685 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
2686
2687 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
2688 tsk->p.tsk.entry_count = 1;
2689 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
2690 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
2691 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
2692 tsk->p.tsk.control_flags = cpu_to_le32(type);
2693 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
2694 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
2695 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
2696 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
2697 if (type == TCF_LUN_RESET) {
2698 int_to_scsilun(l, &tsk->p.tsk.lun);
2699 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
2700 sizeof(tsk->p.tsk.lun));
2701 }
2702
2703 sts = &tsk->p.sts;
2704 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
2705 if (rval != QLA_SUCCESS) {
2706 ql_dbg(ql_dbg_mbx, vha, 0x1094,
2707 "Failed to issue %s reset IOCB (%x).\n", name, rval);
2708 } else if (sts->entry_status != 0) {
2709 ql_dbg(ql_dbg_mbx, vha, 0x1095,
2710 "Failed to complete IOCB -- error status (%x).\n",
2711 sts->entry_status);
2712 rval = QLA_FUNCTION_FAILED;
2713 } else if (sts->comp_status !=
2714 __constant_cpu_to_le16(CS_COMPLETE)) {
2715 ql_dbg(ql_dbg_mbx, vha, 0x1096,
2716 "Failed to complete IOCB -- completion status (%x).\n",
2717 le16_to_cpu(sts->comp_status));
2718 rval = QLA_FUNCTION_FAILED;
2719 } else if (le16_to_cpu(sts->scsi_status) &
2720 SS_RESPONSE_INFO_LEN_VALID) {
2721 if (le32_to_cpu(sts->rsp_data_len) < 4) {
2722 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
2723 "Ignoring inconsistent data length -- not enough "
2724 "response info (%d).\n",
2725 le32_to_cpu(sts->rsp_data_len));
2726 } else if (sts->data[3]) {
2727 ql_dbg(ql_dbg_mbx, vha, 0x1098,
2728 "Failed to complete IOCB -- response (%x).\n",
2729 sts->data[3]);
2730 rval = QLA_FUNCTION_FAILED;
2731 }
2732 }
2733
2734 /* Issue marker IOCB. */
2735 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
2736 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
2737 if (rval2 != QLA_SUCCESS) {
2738 ql_dbg(ql_dbg_mbx, vha, 0x1099,
2739 "Failed to issue marker IOCB (%x).\n", rval2);
2740 } else {
2741 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
2742 "Done %s.\n", __func__);
2743 }
2744
2745 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
2746
2747 return rval;
2748 }
2749
2750 int
2751 qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
2752 {
2753 struct qla_hw_data *ha = fcport->vha->hw;
2754
2755 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2756 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
2757
2758 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
2759 }
2760
2761 int
2762 qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
2763 {
2764 struct qla_hw_data *ha = fcport->vha->hw;
2765
2766 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2767 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
2768
2769 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
2770 }
2771
2772 int
2773 qla2x00_system_error(scsi_qla_host_t *vha)
2774 {
2775 int rval;
2776 mbx_cmd_t mc;
2777 mbx_cmd_t *mcp = &mc;
2778 struct qla_hw_data *ha = vha->hw;
2779
2780 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
2781 return QLA_FUNCTION_FAILED;
2782
2783 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
2784 "Entered %s.\n", __func__);
2785
2786 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
2787 mcp->out_mb = MBX_0;
2788 mcp->in_mb = MBX_0;
2789 mcp->tov = 5;
2790 mcp->flags = 0;
2791 rval = qla2x00_mailbox_command(vha, mcp);
2792
2793 if (rval != QLA_SUCCESS) {
2794 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
2795 } else {
2796 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
2797 "Done %s.\n", __func__);
2798 }
2799
2800 return rval;
2801 }
2802
2803 /**
2804 * qla2x00_set_serdes_params() -
2805 * @ha: HA context
2806 *
2807 * Returns
2808 */
2809 int
2810 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
2811 uint16_t sw_em_2g, uint16_t sw_em_4g)
2812 {
2813 int rval;
2814 mbx_cmd_t mc;
2815 mbx_cmd_t *mcp = &mc;
2816
2817 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
2818 "Entered %s.\n", __func__);
2819
2820 mcp->mb[0] = MBC_SERDES_PARAMS;
2821 mcp->mb[1] = BIT_0;
2822 mcp->mb[2] = sw_em_1g | BIT_15;
2823 mcp->mb[3] = sw_em_2g | BIT_15;
2824 mcp->mb[4] = sw_em_4g | BIT_15;
2825 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2826 mcp->in_mb = MBX_0;
2827 mcp->tov = MBX_TOV_SECONDS;
2828 mcp->flags = 0;
2829 rval = qla2x00_mailbox_command(vha, mcp);
2830
2831 if (rval != QLA_SUCCESS) {
2832 /*EMPTY*/
2833 ql_dbg(ql_dbg_mbx, vha, 0x109f,
2834 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2835 } else {
2836 /*EMPTY*/
2837 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
2838 "Done %s.\n", __func__);
2839 }
2840
2841 return rval;
2842 }
2843
2844 int
2845 qla2x00_stop_firmware(scsi_qla_host_t *vha)
2846 {
2847 int rval;
2848 mbx_cmd_t mc;
2849 mbx_cmd_t *mcp = &mc;
2850
2851 if (!IS_FWI2_CAPABLE(vha->hw))
2852 return QLA_FUNCTION_FAILED;
2853
2854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
2855 "Entered %s.\n", __func__);
2856
2857 mcp->mb[0] = MBC_STOP_FIRMWARE;
2858 mcp->mb[1] = 0;
2859 mcp->out_mb = MBX_1|MBX_0;
2860 mcp->in_mb = MBX_0;
2861 mcp->tov = 5;
2862 mcp->flags = 0;
2863 rval = qla2x00_mailbox_command(vha, mcp);
2864
2865 if (rval != QLA_SUCCESS) {
2866 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
2867 if (mcp->mb[0] == MBS_INVALID_COMMAND)
2868 rval = QLA_INVALID_COMMAND;
2869 } else {
2870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
2871 "Done %s.\n", __func__);
2872 }
2873
2874 return rval;
2875 }
2876
2877 int
2878 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
2879 uint16_t buffers)
2880 {
2881 int rval;
2882 mbx_cmd_t mc;
2883 mbx_cmd_t *mcp = &mc;
2884
2885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
2886 "Entered %s.\n", __func__);
2887
2888 if (!IS_FWI2_CAPABLE(vha->hw))
2889 return QLA_FUNCTION_FAILED;
2890
2891 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2892 return QLA_FUNCTION_FAILED;
2893
2894 mcp->mb[0] = MBC_TRACE_CONTROL;
2895 mcp->mb[1] = TC_EFT_ENABLE;
2896 mcp->mb[2] = LSW(eft_dma);
2897 mcp->mb[3] = MSW(eft_dma);
2898 mcp->mb[4] = LSW(MSD(eft_dma));
2899 mcp->mb[5] = MSW(MSD(eft_dma));
2900 mcp->mb[6] = buffers;
2901 mcp->mb[7] = TC_AEN_DISABLE;
2902 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2903 mcp->in_mb = MBX_1|MBX_0;
2904 mcp->tov = MBX_TOV_SECONDS;
2905 mcp->flags = 0;
2906 rval = qla2x00_mailbox_command(vha, mcp);
2907 if (rval != QLA_SUCCESS) {
2908 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
2909 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2910 rval, mcp->mb[0], mcp->mb[1]);
2911 } else {
2912 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
2913 "Done %s.\n", __func__);
2914 }
2915
2916 return rval;
2917 }
2918
2919 int
2920 qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
2921 {
2922 int rval;
2923 mbx_cmd_t mc;
2924 mbx_cmd_t *mcp = &mc;
2925
2926 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
2927 "Entered %s.\n", __func__);
2928
2929 if (!IS_FWI2_CAPABLE(vha->hw))
2930 return QLA_FUNCTION_FAILED;
2931
2932 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2933 return QLA_FUNCTION_FAILED;
2934
2935 mcp->mb[0] = MBC_TRACE_CONTROL;
2936 mcp->mb[1] = TC_EFT_DISABLE;
2937 mcp->out_mb = MBX_1|MBX_0;
2938 mcp->in_mb = MBX_1|MBX_0;
2939 mcp->tov = MBX_TOV_SECONDS;
2940 mcp->flags = 0;
2941 rval = qla2x00_mailbox_command(vha, mcp);
2942 if (rval != QLA_SUCCESS) {
2943 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
2944 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2945 rval, mcp->mb[0], mcp->mb[1]);
2946 } else {
2947 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
2948 "Done %s.\n", __func__);
2949 }
2950
2951 return rval;
2952 }
2953
2954 int
2955 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
2956 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
2957 {
2958 int rval;
2959 mbx_cmd_t mc;
2960 mbx_cmd_t *mcp = &mc;
2961
2962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
2963 "Entered %s.\n", __func__);
2964
2965 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
2966 !IS_QLA83XX(vha->hw))
2967 return QLA_FUNCTION_FAILED;
2968
2969 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2970 return QLA_FUNCTION_FAILED;
2971
2972 mcp->mb[0] = MBC_TRACE_CONTROL;
2973 mcp->mb[1] = TC_FCE_ENABLE;
2974 mcp->mb[2] = LSW(fce_dma);
2975 mcp->mb[3] = MSW(fce_dma);
2976 mcp->mb[4] = LSW(MSD(fce_dma));
2977 mcp->mb[5] = MSW(MSD(fce_dma));
2978 mcp->mb[6] = buffers;
2979 mcp->mb[7] = TC_AEN_DISABLE;
2980 mcp->mb[8] = 0;
2981 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
2982 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
2983 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
2984 MBX_1|MBX_0;
2985 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2986 mcp->tov = MBX_TOV_SECONDS;
2987 mcp->flags = 0;
2988 rval = qla2x00_mailbox_command(vha, mcp);
2989 if (rval != QLA_SUCCESS) {
2990 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
2991 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2992 rval, mcp->mb[0], mcp->mb[1]);
2993 } else {
2994 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
2995 "Done %s.\n", __func__);
2996
2997 if (mb)
2998 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
2999 if (dwords)
3000 *dwords = buffers;
3001 }
3002
3003 return rval;
3004 }
3005
3006 int
3007 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
3008 {
3009 int rval;
3010 mbx_cmd_t mc;
3011 mbx_cmd_t *mcp = &mc;
3012
3013 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3014 "Entered %s.\n", __func__);
3015
3016 if (!IS_FWI2_CAPABLE(vha->hw))
3017 return QLA_FUNCTION_FAILED;
3018
3019 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3020 return QLA_FUNCTION_FAILED;
3021
3022 mcp->mb[0] = MBC_TRACE_CONTROL;
3023 mcp->mb[1] = TC_FCE_DISABLE;
3024 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3025 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3026 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3027 MBX_1|MBX_0;
3028 mcp->tov = MBX_TOV_SECONDS;
3029 mcp->flags = 0;
3030 rval = qla2x00_mailbox_command(vha, mcp);
3031 if (rval != QLA_SUCCESS) {
3032 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3033 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3034 rval, mcp->mb[0], mcp->mb[1]);
3035 } else {
3036 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3037 "Done %s.\n", __func__);
3038
3039 if (wr)
3040 *wr = (uint64_t) mcp->mb[5] << 48 |
3041 (uint64_t) mcp->mb[4] << 32 |
3042 (uint64_t) mcp->mb[3] << 16 |
3043 (uint64_t) mcp->mb[2];
3044 if (rd)
3045 *rd = (uint64_t) mcp->mb[9] << 48 |
3046 (uint64_t) mcp->mb[8] << 32 |
3047 (uint64_t) mcp->mb[7] << 16 |
3048 (uint64_t) mcp->mb[6];
3049 }
3050
3051 return rval;
3052 }
3053
3054 int
3055 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3056 uint16_t *port_speed, uint16_t *mb)
3057 {
3058 int rval;
3059 mbx_cmd_t mc;
3060 mbx_cmd_t *mcp = &mc;
3061
3062 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3063 "Entered %s.\n", __func__);
3064
3065 if (!IS_IIDMA_CAPABLE(vha->hw))
3066 return QLA_FUNCTION_FAILED;
3067
3068 mcp->mb[0] = MBC_PORT_PARAMS;
3069 mcp->mb[1] = loop_id;
3070 mcp->mb[2] = mcp->mb[3] = 0;
3071 mcp->mb[9] = vha->vp_idx;
3072 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3073 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3074 mcp->tov = MBX_TOV_SECONDS;
3075 mcp->flags = 0;
3076 rval = qla2x00_mailbox_command(vha, mcp);
3077
3078 /* Return mailbox statuses. */
3079 if (mb != NULL) {
3080 mb[0] = mcp->mb[0];
3081 mb[1] = mcp->mb[1];
3082 mb[3] = mcp->mb[3];
3083 }
3084
3085 if (rval != QLA_SUCCESS) {
3086 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
3087 } else {
3088 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3089 "Done %s.\n", __func__);
3090 if (port_speed)
3091 *port_speed = mcp->mb[3];
3092 }
3093
3094 return rval;
3095 }
3096
3097 int
3098 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3099 uint16_t port_speed, uint16_t *mb)
3100 {
3101 int rval;
3102 mbx_cmd_t mc;
3103 mbx_cmd_t *mcp = &mc;
3104
3105 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3106 "Entered %s.\n", __func__);
3107
3108 if (!IS_IIDMA_CAPABLE(vha->hw))
3109 return QLA_FUNCTION_FAILED;
3110
3111 mcp->mb[0] = MBC_PORT_PARAMS;
3112 mcp->mb[1] = loop_id;
3113 mcp->mb[2] = BIT_0;
3114 if (IS_CNA_CAPABLE(vha->hw))
3115 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3116 else
3117 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3118 mcp->mb[9] = vha->vp_idx;
3119 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3120 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3121 mcp->tov = MBX_TOV_SECONDS;
3122 mcp->flags = 0;
3123 rval = qla2x00_mailbox_command(vha, mcp);
3124
3125 /* Return mailbox statuses. */
3126 if (mb != NULL) {
3127 mb[0] = mcp->mb[0];
3128 mb[1] = mcp->mb[1];
3129 mb[3] = mcp->mb[3];
3130 }
3131
3132 if (rval != QLA_SUCCESS) {
3133 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3134 "Failed=%x.\n", rval);
3135 } else {
3136 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3137 "Done %s.\n", __func__);
3138 }
3139
3140 return rval;
3141 }
3142
3143 void
3144 qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
3145 struct vp_rpt_id_entry_24xx *rptid_entry)
3146 {
3147 uint8_t vp_idx;
3148 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
3149 struct qla_hw_data *ha = vha->hw;
3150 scsi_qla_host_t *vp;
3151 unsigned long flags;
3152 int found;
3153
3154 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3155 "Entered %s.\n", __func__);
3156
3157 if (rptid_entry->entry_status != 0)
3158 return;
3159
3160 if (rptid_entry->format == 0) {
3161 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
3162 "Format 0 : Number of VPs setup %d, number of "
3163 "VPs acquired %d.\n",
3164 MSB(le16_to_cpu(rptid_entry->vp_count)),
3165 LSB(le16_to_cpu(rptid_entry->vp_count)));
3166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
3167 "Primary port id %02x%02x%02x.\n",
3168 rptid_entry->port_id[2], rptid_entry->port_id[1],
3169 rptid_entry->port_id[0]);
3170 } else if (rptid_entry->format == 1) {
3171 vp_idx = LSB(stat);
3172 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
3173 "Format 1: VP[%d] enabled - status %d - with "
3174 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
3175 rptid_entry->port_id[2], rptid_entry->port_id[1],
3176 rptid_entry->port_id[0]);
3177
3178 vp = vha;
3179 if (vp_idx == 0 && (MSB(stat) != 1))
3180 goto reg_needed;
3181
3182 if (MSB(stat) != 0 && MSB(stat) != 2) {
3183 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3184 "Could not acquire ID for VP[%d].\n", vp_idx);
3185 return;
3186 }
3187
3188 found = 0;
3189 spin_lock_irqsave(&ha->vport_slock, flags);
3190 list_for_each_entry(vp, &ha->vp_list, list) {
3191 if (vp_idx == vp->vp_idx) {
3192 found = 1;
3193 break;
3194 }
3195 }
3196 spin_unlock_irqrestore(&ha->vport_slock, flags);
3197
3198 if (!found)
3199 return;
3200
3201 vp->d_id.b.domain = rptid_entry->port_id[2];
3202 vp->d_id.b.area = rptid_entry->port_id[1];
3203 vp->d_id.b.al_pa = rptid_entry->port_id[0];
3204
3205 /*
3206 * Cannot configure here as we are still sitting on the
3207 * response queue. Handle it in dpc context.
3208 */
3209 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3210
3211 reg_needed:
3212 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3213 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3214 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
3215 qla2xxx_wake_dpc(vha);
3216 }
3217 }
3218
3219 /*
3220 * qla24xx_modify_vp_config
3221 * Change VP configuration for vha
3222 *
3223 * Input:
3224 * vha = adapter block pointer.
3225 *
3226 * Returns:
3227 * qla2xxx local function return status code.
3228 *
3229 * Context:
3230 * Kernel context.
3231 */
3232 int
3233 qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3234 {
3235 int rval;
3236 struct vp_config_entry_24xx *vpmod;
3237 dma_addr_t vpmod_dma;
3238 struct qla_hw_data *ha = vha->hw;
3239 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3240
3241 /* This can be called by the parent */
3242
3243 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3244 "Entered %s.\n", __func__);
3245
3246 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
3247 if (!vpmod) {
3248 ql_log(ql_log_warn, vha, 0x10bc,
3249 "Failed to allocate modify VP IOCB.\n");
3250 return QLA_MEMORY_ALLOC_FAILED;
3251 }
3252
3253 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3254 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3255 vpmod->entry_count = 1;
3256 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3257 vpmod->vp_count = 1;
3258 vpmod->vp_index1 = vha->vp_idx;
3259 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
3260
3261 qlt_modify_vp_config(vha, vpmod);
3262
3263 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3264 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3265 vpmod->entry_count = 1;
3266
3267 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
3268 if (rval != QLA_SUCCESS) {
3269 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3270 "Failed to issue VP config IOCB (%x).\n", rval);
3271 } else if (vpmod->comp_status != 0) {
3272 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3273 "Failed to complete IOCB -- error status (%x).\n",
3274 vpmod->comp_status);
3275 rval = QLA_FUNCTION_FAILED;
3276 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
3277 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3278 "Failed to complete IOCB -- completion status (%x).\n",
3279 le16_to_cpu(vpmod->comp_status));
3280 rval = QLA_FUNCTION_FAILED;
3281 } else {
3282 /* EMPTY */
3283 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3284 "Done %s.\n", __func__);
3285 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3286 }
3287 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
3288
3289 return rval;
3290 }
3291
3292 /*
3293 * qla24xx_control_vp
3294 * Enable a virtual port for given host
3295 *
3296 * Input:
3297 * ha = adapter block pointer.
3298 * vhba = virtual adapter (unused)
3299 * index = index number for enabled VP
3300 *
3301 * Returns:
3302 * qla2xxx local function return status code.
3303 *
3304 * Context:
3305 * Kernel context.
3306 */
3307 int
3308 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3309 {
3310 int rval;
3311 int map, pos;
3312 struct vp_ctrl_entry_24xx *vce;
3313 dma_addr_t vce_dma;
3314 struct qla_hw_data *ha = vha->hw;
3315 int vp_index = vha->vp_idx;
3316 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3317
3318 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
3319 "Entered %s enabling index %d.\n", __func__, vp_index);
3320
3321 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
3322 return QLA_PARAMETER_ERROR;
3323
3324 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3325 if (!vce) {
3326 ql_log(ql_log_warn, vha, 0x10c2,
3327 "Failed to allocate VP control IOCB.\n");
3328 return QLA_MEMORY_ALLOC_FAILED;
3329 }
3330 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3331
3332 vce->entry_type = VP_CTRL_IOCB_TYPE;
3333 vce->entry_count = 1;
3334 vce->command = cpu_to_le16(cmd);
3335 vce->vp_count = __constant_cpu_to_le16(1);
3336
3337 /* index map in firmware starts with 1; decrement index
3338 * this is ok as we never use index 0
3339 */
3340 map = (vp_index - 1) / 8;
3341 pos = (vp_index - 1) & 7;
3342 mutex_lock(&ha->vport_lock);
3343 vce->vp_idx_map[map] |= 1 << pos;
3344 mutex_unlock(&ha->vport_lock);
3345
3346 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
3347 if (rval != QLA_SUCCESS) {
3348 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3349 "Failed to issue VP control IOCB (%x).\n", rval);
3350 } else if (vce->entry_status != 0) {
3351 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3352 "Failed to complete IOCB -- error status (%x).\n",
3353 vce->entry_status);
3354 rval = QLA_FUNCTION_FAILED;
3355 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
3356 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3357 "Failed to complet IOCB -- completion status (%x).\n",
3358 le16_to_cpu(vce->comp_status));
3359 rval = QLA_FUNCTION_FAILED;
3360 } else {
3361 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3362 "Done %s.\n", __func__);
3363 }
3364
3365 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3366
3367 return rval;
3368 }
3369
3370 /*
3371 * qla2x00_send_change_request
3372 * Receive or disable RSCN request from fabric controller
3373 *
3374 * Input:
3375 * ha = adapter block pointer
3376 * format = registration format:
3377 * 0 - Reserved
3378 * 1 - Fabric detected registration
3379 * 2 - N_port detected registration
3380 * 3 - Full registration
3381 * FF - clear registration
3382 * vp_idx = Virtual port index
3383 *
3384 * Returns:
3385 * qla2x00 local function return status code.
3386 *
3387 * Context:
3388 * Kernel Context
3389 */
3390
3391 int
3392 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
3393 uint16_t vp_idx)
3394 {
3395 int rval;
3396 mbx_cmd_t mc;
3397 mbx_cmd_t *mcp = &mc;
3398
3399 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3400 "Entered %s.\n", __func__);
3401
3402 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3403 mcp->mb[1] = format;
3404 mcp->mb[9] = vp_idx;
3405 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3406 mcp->in_mb = MBX_0|MBX_1;
3407 mcp->tov = MBX_TOV_SECONDS;
3408 mcp->flags = 0;
3409 rval = qla2x00_mailbox_command(vha, mcp);
3410
3411 if (rval == QLA_SUCCESS) {
3412 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3413 rval = BIT_1;
3414 }
3415 } else
3416 rval = BIT_1;
3417
3418 return rval;
3419 }
3420
3421 int
3422 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
3423 uint32_t size)
3424 {
3425 int rval;
3426 mbx_cmd_t mc;
3427 mbx_cmd_t *mcp = &mc;
3428
3429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3430 "Entered %s.\n", __func__);
3431
3432 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
3433 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3434 mcp->mb[8] = MSW(addr);
3435 mcp->out_mb = MBX_8|MBX_0;
3436 } else {
3437 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3438 mcp->out_mb = MBX_0;
3439 }
3440 mcp->mb[1] = LSW(addr);
3441 mcp->mb[2] = MSW(req_dma);
3442 mcp->mb[3] = LSW(req_dma);
3443 mcp->mb[6] = MSW(MSD(req_dma));
3444 mcp->mb[7] = LSW(MSD(req_dma));
3445 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
3446 if (IS_FWI2_CAPABLE(vha->hw)) {
3447 mcp->mb[4] = MSW(size);
3448 mcp->mb[5] = LSW(size);
3449 mcp->out_mb |= MBX_5|MBX_4;
3450 } else {
3451 mcp->mb[4] = LSW(size);
3452 mcp->out_mb |= MBX_4;
3453 }
3454
3455 mcp->in_mb = MBX_0;
3456 mcp->tov = MBX_TOV_SECONDS;
3457 mcp->flags = 0;
3458 rval = qla2x00_mailbox_command(vha, mcp);
3459
3460 if (rval != QLA_SUCCESS) {
3461 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3462 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3463 } else {
3464 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3465 "Done %s.\n", __func__);
3466 }
3467
3468 return rval;
3469 }
3470 /* 84XX Support **************************************************************/
3471
3472 struct cs84xx_mgmt_cmd {
3473 union {
3474 struct verify_chip_entry_84xx req;
3475 struct verify_chip_rsp_84xx rsp;
3476 } p;
3477 };
3478
3479 int
3480 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
3481 {
3482 int rval, retry;
3483 struct cs84xx_mgmt_cmd *mn;
3484 dma_addr_t mn_dma;
3485 uint16_t options;
3486 unsigned long flags;
3487 struct qla_hw_data *ha = vha->hw;
3488
3489 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
3490 "Entered %s.\n", __func__);
3491
3492 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
3493 if (mn == NULL) {
3494 return QLA_MEMORY_ALLOC_FAILED;
3495 }
3496
3497 /* Force Update? */
3498 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
3499 /* Diagnostic firmware? */
3500 /* options |= MENLO_DIAG_FW; */
3501 /* We update the firmware with only one data sequence. */
3502 options |= VCO_END_OF_DATA;
3503
3504 do {
3505 retry = 0;
3506 memset(mn, 0, sizeof(*mn));
3507 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
3508 mn->p.req.entry_count = 1;
3509 mn->p.req.options = cpu_to_le16(options);
3510
3511 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
3512 "Dump of Verify Request.\n");
3513 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
3514 (uint8_t *)mn, sizeof(*mn));
3515
3516 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
3517 if (rval != QLA_SUCCESS) {
3518 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
3519 "Failed to issue verify IOCB (%x).\n", rval);
3520 goto verify_done;
3521 }
3522
3523 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
3524 "Dump of Verify Response.\n");
3525 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
3526 (uint8_t *)mn, sizeof(*mn));
3527
3528 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
3529 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
3530 le16_to_cpu(mn->p.rsp.failure_code) : 0;
3531 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
3532 "cs=%x fc=%x.\n", status[0], status[1]);
3533
3534 if (status[0] != CS_COMPLETE) {
3535 rval = QLA_FUNCTION_FAILED;
3536 if (!(options & VCO_DONT_UPDATE_FW)) {
3537 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
3538 "Firmware update failed. Retrying "
3539 "without update firmware.\n");
3540 options |= VCO_DONT_UPDATE_FW;
3541 options &= ~VCO_FORCE_UPDATE;
3542 retry = 1;
3543 }
3544 } else {
3545 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
3546 "Firmware updated to %x.\n",
3547 le32_to_cpu(mn->p.rsp.fw_ver));
3548
3549 /* NOTE: we only update OP firmware. */
3550 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
3551 ha->cs84xx->op_fw_version =
3552 le32_to_cpu(mn->p.rsp.fw_ver);
3553 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
3554 flags);
3555 }
3556 } while (retry);
3557
3558 verify_done:
3559 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
3560
3561 if (rval != QLA_SUCCESS) {
3562 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
3563 "Failed=%x.\n", rval);
3564 } else {
3565 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
3566 "Done %s.\n", __func__);
3567 }
3568
3569 return rval;
3570 }
3571
3572 int
3573 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
3574 {
3575 int rval;
3576 unsigned long flags;
3577 mbx_cmd_t mc;
3578 mbx_cmd_t *mcp = &mc;
3579 struct qla_hw_data *ha = vha->hw;
3580
3581 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
3582 "Entered %s.\n", __func__);
3583
3584 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3585 mcp->mb[1] = req->options;
3586 mcp->mb[2] = MSW(LSD(req->dma));
3587 mcp->mb[3] = LSW(LSD(req->dma));
3588 mcp->mb[6] = MSW(MSD(req->dma));
3589 mcp->mb[7] = LSW(MSD(req->dma));
3590 mcp->mb[5] = req->length;
3591 if (req->rsp)
3592 mcp->mb[10] = req->rsp->id;
3593 mcp->mb[12] = req->qos;
3594 mcp->mb[11] = req->vp_idx;
3595 mcp->mb[13] = req->rid;
3596 if (IS_QLA83XX(ha))
3597 mcp->mb[15] = 0;
3598
3599 mcp->mb[4] = req->id;
3600 /* que in ptr index */
3601 mcp->mb[8] = 0;
3602 /* que out ptr index */
3603 mcp->mb[9] = 0;
3604 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
3605 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3606 mcp->in_mb = MBX_0;
3607 mcp->flags = MBX_DMA_OUT;
3608 mcp->tov = MBX_TOV_SECONDS * 2;
3609
3610 if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
3611 mcp->in_mb |= MBX_1;
3612 if (IS_QLA83XX(ha)) {
3613 mcp->out_mb |= MBX_15;
3614 /* debug q create issue in SR-IOV */
3615 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3616 }
3617
3618 spin_lock_irqsave(&ha->hardware_lock, flags);
3619 if (!(req->options & BIT_0)) {
3620 WRT_REG_DWORD(req->req_q_in, 0);
3621 if (!IS_QLA83XX(ha))
3622 WRT_REG_DWORD(req->req_q_out, 0);
3623 }
3624 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3625
3626 rval = qla2x00_mailbox_command(vha, mcp);
3627 if (rval != QLA_SUCCESS) {
3628 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
3629 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3630 } else {
3631 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
3632 "Done %s.\n", __func__);
3633 }
3634
3635 return rval;
3636 }
3637
3638 int
3639 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
3640 {
3641 int rval;
3642 unsigned long flags;
3643 mbx_cmd_t mc;
3644 mbx_cmd_t *mcp = &mc;
3645 struct qla_hw_data *ha = vha->hw;
3646
3647 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
3648 "Entered %s.\n", __func__);
3649
3650 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3651 mcp->mb[1] = rsp->options;
3652 mcp->mb[2] = MSW(LSD(rsp->dma));
3653 mcp->mb[3] = LSW(LSD(rsp->dma));
3654 mcp->mb[6] = MSW(MSD(rsp->dma));
3655 mcp->mb[7] = LSW(MSD(rsp->dma));
3656 mcp->mb[5] = rsp->length;
3657 mcp->mb[14] = rsp->msix->entry;
3658 mcp->mb[13] = rsp->rid;
3659 if (IS_QLA83XX(ha))
3660 mcp->mb[15] = 0;
3661
3662 mcp->mb[4] = rsp->id;
3663 /* que in ptr index */
3664 mcp->mb[8] = 0;
3665 /* que out ptr index */
3666 mcp->mb[9] = 0;
3667 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
3668 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3669 mcp->in_mb = MBX_0;
3670 mcp->flags = MBX_DMA_OUT;
3671 mcp->tov = MBX_TOV_SECONDS * 2;
3672
3673 if (IS_QLA81XX(ha)) {
3674 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
3675 mcp->in_mb |= MBX_1;
3676 } else if (IS_QLA83XX(ha)) {
3677 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
3678 mcp->in_mb |= MBX_1;
3679 /* debug q create issue in SR-IOV */
3680 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3681 }
3682
3683 spin_lock_irqsave(&ha->hardware_lock, flags);
3684 if (!(rsp->options & BIT_0)) {
3685 WRT_REG_DWORD(rsp->rsp_q_out, 0);
3686 if (!IS_QLA83XX(ha))
3687 WRT_REG_DWORD(rsp->rsp_q_in, 0);
3688 }
3689
3690 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3691
3692 rval = qla2x00_mailbox_command(vha, mcp);
3693 if (rval != QLA_SUCCESS) {
3694 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
3695 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3696 } else {
3697 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
3698 "Done %s.\n", __func__);
3699 }
3700
3701 return rval;
3702 }
3703
3704 int
3705 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
3706 {
3707 int rval;
3708 mbx_cmd_t mc;
3709 mbx_cmd_t *mcp = &mc;
3710
3711 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
3712 "Entered %s.\n", __func__);
3713
3714 mcp->mb[0] = MBC_IDC_ACK;
3715 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3716 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3717 mcp->in_mb = MBX_0;
3718 mcp->tov = MBX_TOV_SECONDS;
3719 mcp->flags = 0;
3720 rval = qla2x00_mailbox_command(vha, mcp);
3721
3722 if (rval != QLA_SUCCESS) {
3723 ql_dbg(ql_dbg_mbx, vha, 0x10da,
3724 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3725 } else {
3726 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
3727 "Done %s.\n", __func__);
3728 }
3729
3730 return rval;
3731 }
3732
3733 int
3734 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3735 {
3736 int rval;
3737 mbx_cmd_t mc;
3738 mbx_cmd_t *mcp = &mc;
3739
3740 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
3741 "Entered %s.\n", __func__);
3742
3743 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
3744 return QLA_FUNCTION_FAILED;
3745
3746 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3747 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
3748 mcp->out_mb = MBX_1|MBX_0;
3749 mcp->in_mb = MBX_1|MBX_0;
3750 mcp->tov = MBX_TOV_SECONDS;
3751 mcp->flags = 0;
3752 rval = qla2x00_mailbox_command(vha, mcp);
3753
3754 if (rval != QLA_SUCCESS) {
3755 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
3756 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3757 rval, mcp->mb[0], mcp->mb[1]);
3758 } else {
3759 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
3760 "Done %s.\n", __func__);
3761 *sector_size = mcp->mb[1];
3762 }
3763
3764 return rval;
3765 }
3766
3767 int
3768 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3769 {
3770 int rval;
3771 mbx_cmd_t mc;
3772 mbx_cmd_t *mcp = &mc;
3773
3774 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
3775 return QLA_FUNCTION_FAILED;
3776
3777 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
3778 "Entered %s.\n", __func__);
3779
3780 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3781 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
3782 FAC_OPT_CMD_WRITE_PROTECT;
3783 mcp->out_mb = MBX_1|MBX_0;
3784 mcp->in_mb = MBX_1|MBX_0;
3785 mcp->tov = MBX_TOV_SECONDS;
3786 mcp->flags = 0;
3787 rval = qla2x00_mailbox_command(vha, mcp);
3788
3789 if (rval != QLA_SUCCESS) {
3790 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
3791 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3792 rval, mcp->mb[0], mcp->mb[1]);
3793 } else {
3794 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
3795 "Done %s.\n", __func__);
3796 }
3797
3798 return rval;
3799 }
3800
3801 int
3802 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
3803 {
3804 int rval;
3805 mbx_cmd_t mc;
3806 mbx_cmd_t *mcp = &mc;
3807
3808 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
3809 return QLA_FUNCTION_FAILED;
3810
3811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
3812 "Entered %s.\n", __func__);
3813
3814 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3815 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
3816 mcp->mb[2] = LSW(start);
3817 mcp->mb[3] = MSW(start);
3818 mcp->mb[4] = LSW(finish);
3819 mcp->mb[5] = MSW(finish);
3820 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3821 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3822 mcp->tov = MBX_TOV_SECONDS;
3823 mcp->flags = 0;
3824 rval = qla2x00_mailbox_command(vha, mcp);
3825
3826 if (rval != QLA_SUCCESS) {
3827 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
3828 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3829 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
3830 } else {
3831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
3832 "Done %s.\n", __func__);
3833 }
3834
3835 return rval;
3836 }
3837
3838 int
3839 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
3840 {
3841 int rval = 0;
3842 mbx_cmd_t mc;
3843 mbx_cmd_t *mcp = &mc;
3844
3845 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
3846 "Entered %s.\n", __func__);
3847
3848 mcp->mb[0] = MBC_RESTART_MPI_FW;
3849 mcp->out_mb = MBX_0;
3850 mcp->in_mb = MBX_0|MBX_1;
3851 mcp->tov = MBX_TOV_SECONDS;
3852 mcp->flags = 0;
3853 rval = qla2x00_mailbox_command(vha, mcp);
3854
3855 if (rval != QLA_SUCCESS) {
3856 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
3857 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3858 rval, mcp->mb[0], mcp->mb[1]);
3859 } else {
3860 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
3861 "Done %s.\n", __func__);
3862 }
3863
3864 return rval;
3865 }
3866
3867 int
3868 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
3869 {
3870 int rval;
3871 mbx_cmd_t mc;
3872 mbx_cmd_t *mcp = &mc;
3873 int i;
3874 int len;
3875 uint16_t *str;
3876 struct qla_hw_data *ha = vha->hw;
3877
3878 if (!IS_P3P_TYPE(ha))
3879 return QLA_FUNCTION_FAILED;
3880
3881 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
3882 "Entered %s.\n", __func__);
3883
3884 str = (void *)version;
3885 len = strlen(version);
3886
3887 mcp->mb[0] = MBC_SET_RNID_PARAMS;
3888 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
3889 mcp->out_mb = MBX_1|MBX_0;
3890 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
3891 mcp->mb[i] = cpu_to_le16p(str);
3892 mcp->out_mb |= 1<<i;
3893 }
3894 for (; i < 16; i++) {
3895 mcp->mb[i] = 0;
3896 mcp->out_mb |= 1<<i;
3897 }
3898 mcp->in_mb = MBX_1|MBX_0;
3899 mcp->tov = MBX_TOV_SECONDS;
3900 mcp->flags = 0;
3901 rval = qla2x00_mailbox_command(vha, mcp);
3902
3903 if (rval != QLA_SUCCESS) {
3904 ql_dbg(ql_dbg_mbx, vha, 0x117c,
3905 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
3906 } else {
3907 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
3908 "Done %s.\n", __func__);
3909 }
3910
3911 return rval;
3912 }
3913
3914 int
3915 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
3916 {
3917 int rval;
3918 mbx_cmd_t mc;
3919 mbx_cmd_t *mcp = &mc;
3920 int len;
3921 uint16_t dwlen;
3922 uint8_t *str;
3923 dma_addr_t str_dma;
3924 struct qla_hw_data *ha = vha->hw;
3925
3926 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
3927 IS_P3P_TYPE(ha))
3928 return QLA_FUNCTION_FAILED;
3929
3930 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
3931 "Entered %s.\n", __func__);
3932
3933 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
3934 if (!str) {
3935 ql_log(ql_log_warn, vha, 0x117f,
3936 "Failed to allocate driver version param.\n");
3937 return QLA_MEMORY_ALLOC_FAILED;
3938 }
3939
3940 memcpy(str, "\x7\x3\x11\x0", 4);
3941 dwlen = str[0];
3942 len = dwlen * 4 - 4;
3943 memset(str + 4, 0, len);
3944 if (len > strlen(version))
3945 len = strlen(version);
3946 memcpy(str + 4, version, len);
3947
3948 mcp->mb[0] = MBC_SET_RNID_PARAMS;
3949 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
3950 mcp->mb[2] = MSW(LSD(str_dma));
3951 mcp->mb[3] = LSW(LSD(str_dma));
3952 mcp->mb[6] = MSW(MSD(str_dma));
3953 mcp->mb[7] = LSW(MSD(str_dma));
3954 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
3955 mcp->in_mb = MBX_1|MBX_0;
3956 mcp->tov = MBX_TOV_SECONDS;
3957 mcp->flags = 0;
3958 rval = qla2x00_mailbox_command(vha, mcp);
3959
3960 if (rval != QLA_SUCCESS) {
3961 ql_dbg(ql_dbg_mbx, vha, 0x1180,
3962 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
3963 } else {
3964 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
3965 "Done %s.\n", __func__);
3966 }
3967
3968 dma_pool_free(ha->s_dma_pool, str, str_dma);
3969
3970 return rval;
3971 }
3972
3973 static int
3974 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
3975 {
3976 int rval;
3977 mbx_cmd_t mc;
3978 mbx_cmd_t *mcp = &mc;
3979
3980 if (!IS_FWI2_CAPABLE(vha->hw))
3981 return QLA_FUNCTION_FAILED;
3982
3983 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
3984 "Entered %s.\n", __func__);
3985
3986 mcp->mb[0] = MBC_GET_RNID_PARAMS;
3987 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
3988 mcp->out_mb = MBX_1|MBX_0;
3989 mcp->in_mb = MBX_1|MBX_0;
3990 mcp->tov = MBX_TOV_SECONDS;
3991 mcp->flags = 0;
3992 rval = qla2x00_mailbox_command(vha, mcp);
3993 *temp = mcp->mb[1];
3994
3995 if (rval != QLA_SUCCESS) {
3996 ql_dbg(ql_dbg_mbx, vha, 0x115a,
3997 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
3998 } else {
3999 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4000 "Done %s.\n", __func__);
4001 }
4002
4003 return rval;
4004 }
4005
4006 int
4007 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4008 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4009 {
4010 int rval;
4011 mbx_cmd_t mc;
4012 mbx_cmd_t *mcp = &mc;
4013 struct qla_hw_data *ha = vha->hw;
4014
4015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4016 "Entered %s.\n", __func__);
4017
4018 if (!IS_FWI2_CAPABLE(ha))
4019 return QLA_FUNCTION_FAILED;
4020
4021 if (len == 1)
4022 opt |= BIT_0;
4023
4024 mcp->mb[0] = MBC_READ_SFP;
4025 mcp->mb[1] = dev;
4026 mcp->mb[2] = MSW(sfp_dma);
4027 mcp->mb[3] = LSW(sfp_dma);
4028 mcp->mb[6] = MSW(MSD(sfp_dma));
4029 mcp->mb[7] = LSW(MSD(sfp_dma));
4030 mcp->mb[8] = len;
4031 mcp->mb[9] = off;
4032 mcp->mb[10] = opt;
4033 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4034 mcp->in_mb = MBX_1|MBX_0;
4035 mcp->tov = MBX_TOV_SECONDS;
4036 mcp->flags = 0;
4037 rval = qla2x00_mailbox_command(vha, mcp);
4038
4039 if (opt & BIT_0)
4040 *sfp = mcp->mb[1];
4041
4042 if (rval != QLA_SUCCESS) {
4043 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4044 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4045 } else {
4046 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4047 "Done %s.\n", __func__);
4048 }
4049
4050 return rval;
4051 }
4052
4053 int
4054 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4055 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4056 {
4057 int rval;
4058 mbx_cmd_t mc;
4059 mbx_cmd_t *mcp = &mc;
4060 struct qla_hw_data *ha = vha->hw;
4061
4062 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4063 "Entered %s.\n", __func__);
4064
4065 if (!IS_FWI2_CAPABLE(ha))
4066 return QLA_FUNCTION_FAILED;
4067
4068 if (len == 1)
4069 opt |= BIT_0;
4070
4071 if (opt & BIT_0)
4072 len = *sfp;
4073
4074 mcp->mb[0] = MBC_WRITE_SFP;
4075 mcp->mb[1] = dev;
4076 mcp->mb[2] = MSW(sfp_dma);
4077 mcp->mb[3] = LSW(sfp_dma);
4078 mcp->mb[6] = MSW(MSD(sfp_dma));
4079 mcp->mb[7] = LSW(MSD(sfp_dma));
4080 mcp->mb[8] = len;
4081 mcp->mb[9] = off;
4082 mcp->mb[10] = opt;
4083 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4084 mcp->in_mb = MBX_1|MBX_0;
4085 mcp->tov = MBX_TOV_SECONDS;
4086 mcp->flags = 0;
4087 rval = qla2x00_mailbox_command(vha, mcp);
4088
4089 if (rval != QLA_SUCCESS) {
4090 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4091 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4092 } else {
4093 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4094 "Done %s.\n", __func__);
4095 }
4096
4097 return rval;
4098 }
4099
4100 int
4101 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4102 uint16_t size_in_bytes, uint16_t *actual_size)
4103 {
4104 int rval;
4105 mbx_cmd_t mc;
4106 mbx_cmd_t *mcp = &mc;
4107
4108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4109 "Entered %s.\n", __func__);
4110
4111 if (!IS_CNA_CAPABLE(vha->hw))
4112 return QLA_FUNCTION_FAILED;
4113
4114 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4115 mcp->mb[2] = MSW(stats_dma);
4116 mcp->mb[3] = LSW(stats_dma);
4117 mcp->mb[6] = MSW(MSD(stats_dma));
4118 mcp->mb[7] = LSW(MSD(stats_dma));
4119 mcp->mb[8] = size_in_bytes >> 2;
4120 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4121 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4122 mcp->tov = MBX_TOV_SECONDS;
4123 mcp->flags = 0;
4124 rval = qla2x00_mailbox_command(vha, mcp);
4125
4126 if (rval != QLA_SUCCESS) {
4127 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4128 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4129 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4130 } else {
4131 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4132 "Done %s.\n", __func__);
4133
4134
4135 *actual_size = mcp->mb[2] << 2;
4136 }
4137
4138 return rval;
4139 }
4140
4141 int
4142 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4143 uint16_t size)
4144 {
4145 int rval;
4146 mbx_cmd_t mc;
4147 mbx_cmd_t *mcp = &mc;
4148
4149 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4150 "Entered %s.\n", __func__);
4151
4152 if (!IS_CNA_CAPABLE(vha->hw))
4153 return QLA_FUNCTION_FAILED;
4154
4155 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4156 mcp->mb[1] = 0;
4157 mcp->mb[2] = MSW(tlv_dma);
4158 mcp->mb[3] = LSW(tlv_dma);
4159 mcp->mb[6] = MSW(MSD(tlv_dma));
4160 mcp->mb[7] = LSW(MSD(tlv_dma));
4161 mcp->mb[8] = size;
4162 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4163 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4164 mcp->tov = MBX_TOV_SECONDS;
4165 mcp->flags = 0;
4166 rval = qla2x00_mailbox_command(vha, mcp);
4167
4168 if (rval != QLA_SUCCESS) {
4169 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4170 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4171 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4172 } else {
4173 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4174 "Done %s.\n", __func__);
4175 }
4176
4177 return rval;
4178 }
4179
4180 int
4181 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4182 {
4183 int rval;
4184 mbx_cmd_t mc;
4185 mbx_cmd_t *mcp = &mc;
4186
4187 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4188 "Entered %s.\n", __func__);
4189
4190 if (!IS_FWI2_CAPABLE(vha->hw))
4191 return QLA_FUNCTION_FAILED;
4192
4193 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4194 mcp->mb[1] = LSW(risc_addr);
4195 mcp->mb[8] = MSW(risc_addr);
4196 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4197 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4198 mcp->tov = 30;
4199 mcp->flags = 0;
4200 rval = qla2x00_mailbox_command(vha, mcp);
4201 if (rval != QLA_SUCCESS) {
4202 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4203 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4204 } else {
4205 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4206 "Done %s.\n", __func__);
4207 *data = mcp->mb[3] << 16 | mcp->mb[2];
4208 }
4209
4210 return rval;
4211 }
4212
4213 int
4214 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4215 uint16_t *mresp)
4216 {
4217 int rval;
4218 mbx_cmd_t mc;
4219 mbx_cmd_t *mcp = &mc;
4220
4221 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4222 "Entered %s.\n", __func__);
4223
4224 memset(mcp->mb, 0 , sizeof(mcp->mb));
4225 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4226 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4227
4228 /* transfer count */
4229 mcp->mb[10] = LSW(mreq->transfer_size);
4230 mcp->mb[11] = MSW(mreq->transfer_size);
4231
4232 /* send data address */
4233 mcp->mb[14] = LSW(mreq->send_dma);
4234 mcp->mb[15] = MSW(mreq->send_dma);
4235 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4236 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4237
4238 /* receive data address */
4239 mcp->mb[16] = LSW(mreq->rcv_dma);
4240 mcp->mb[17] = MSW(mreq->rcv_dma);
4241 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4242 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4243
4244 /* Iteration count */
4245 mcp->mb[18] = LSW(mreq->iteration_count);
4246 mcp->mb[19] = MSW(mreq->iteration_count);
4247
4248 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4249 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4250 if (IS_CNA_CAPABLE(vha->hw))
4251 mcp->out_mb |= MBX_2;
4252 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4253
4254 mcp->buf_size = mreq->transfer_size;
4255 mcp->tov = MBX_TOV_SECONDS;
4256 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4257
4258 rval = qla2x00_mailbox_command(vha, mcp);
4259
4260 if (rval != QLA_SUCCESS) {
4261 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4262 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4263 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4264 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
4265 } else {
4266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4267 "Done %s.\n", __func__);
4268 }
4269
4270 /* Copy mailbox information */
4271 memcpy( mresp, mcp->mb, 64);
4272 return rval;
4273 }
4274
4275 int
4276 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4277 uint16_t *mresp)
4278 {
4279 int rval;
4280 mbx_cmd_t mc;
4281 mbx_cmd_t *mcp = &mc;
4282 struct qla_hw_data *ha = vha->hw;
4283
4284 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4285 "Entered %s.\n", __func__);
4286
4287 memset(mcp->mb, 0 , sizeof(mcp->mb));
4288 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
4289 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
4290 if (IS_CNA_CAPABLE(ha)) {
4291 mcp->mb[1] |= BIT_15;
4292 mcp->mb[2] = vha->fcoe_fcf_idx;
4293 }
4294 mcp->mb[16] = LSW(mreq->rcv_dma);
4295 mcp->mb[17] = MSW(mreq->rcv_dma);
4296 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4297 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4298
4299 mcp->mb[10] = LSW(mreq->transfer_size);
4300
4301 mcp->mb[14] = LSW(mreq->send_dma);
4302 mcp->mb[15] = MSW(mreq->send_dma);
4303 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4304 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4305
4306 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4307 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4308 if (IS_CNA_CAPABLE(ha))
4309 mcp->out_mb |= MBX_2;
4310
4311 mcp->in_mb = MBX_0;
4312 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4313 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4314 mcp->in_mb |= MBX_1;
4315 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4316 mcp->in_mb |= MBX_3;
4317
4318 mcp->tov = MBX_TOV_SECONDS;
4319 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4320 mcp->buf_size = mreq->transfer_size;
4321
4322 rval = qla2x00_mailbox_command(vha, mcp);
4323
4324 if (rval != QLA_SUCCESS) {
4325 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4326 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4327 rval, mcp->mb[0], mcp->mb[1]);
4328 } else {
4329 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4330 "Done %s.\n", __func__);
4331 }
4332
4333 /* Copy mailbox information */
4334 memcpy(mresp, mcp->mb, 64);
4335 return rval;
4336 }
4337
4338 int
4339 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
4340 {
4341 int rval;
4342 mbx_cmd_t mc;
4343 mbx_cmd_t *mcp = &mc;
4344
4345 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
4346 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
4347
4348 mcp->mb[0] = MBC_ISP84XX_RESET;
4349 mcp->mb[1] = enable_diagnostic;
4350 mcp->out_mb = MBX_1|MBX_0;
4351 mcp->in_mb = MBX_1|MBX_0;
4352 mcp->tov = MBX_TOV_SECONDS;
4353 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4354 rval = qla2x00_mailbox_command(vha, mcp);
4355
4356 if (rval != QLA_SUCCESS)
4357 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
4358 else
4359 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4360 "Done %s.\n", __func__);
4361
4362 return rval;
4363 }
4364
4365 int
4366 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4367 {
4368 int rval;
4369 mbx_cmd_t mc;
4370 mbx_cmd_t *mcp = &mc;
4371
4372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4373 "Entered %s.\n", __func__);
4374
4375 if (!IS_FWI2_CAPABLE(vha->hw))
4376 return QLA_FUNCTION_FAILED;
4377
4378 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4379 mcp->mb[1] = LSW(risc_addr);
4380 mcp->mb[2] = LSW(data);
4381 mcp->mb[3] = MSW(data);
4382 mcp->mb[8] = MSW(risc_addr);
4383 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4384 mcp->in_mb = MBX_0;
4385 mcp->tov = 30;
4386 mcp->flags = 0;
4387 rval = qla2x00_mailbox_command(vha, mcp);
4388 if (rval != QLA_SUCCESS) {
4389 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4390 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4391 } else {
4392 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4393 "Done %s.\n", __func__);
4394 }
4395
4396 return rval;
4397 }
4398
4399 int
4400 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4401 {
4402 int rval;
4403 uint32_t stat, timer;
4404 uint16_t mb0 = 0;
4405 struct qla_hw_data *ha = vha->hw;
4406 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4407
4408 rval = QLA_SUCCESS;
4409
4410 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4411 "Entered %s.\n", __func__);
4412
4413 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4414
4415 /* Write the MBC data to the registers */
4416 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4417 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4418 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4419 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4420 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4421
4422 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4423
4424 /* Poll for MBC interrupt */
4425 for (timer = 6000000; timer; timer--) {
4426 /* Check for pending interrupts. */
4427 stat = RD_REG_DWORD(&reg->host_status);
4428 if (stat & HSRX_RISC_INT) {
4429 stat &= 0xff;
4430
4431 if (stat == 0x1 || stat == 0x2 ||
4432 stat == 0x10 || stat == 0x11) {
4433 set_bit(MBX_INTERRUPT,
4434 &ha->mbx_cmd_flags);
4435 mb0 = RD_REG_WORD(&reg->mailbox0);
4436 WRT_REG_DWORD(&reg->hccr,
4437 HCCRX_CLR_RISC_INT);
4438 RD_REG_DWORD(&reg->hccr);
4439 break;
4440 }
4441 }
4442 udelay(5);
4443 }
4444
4445 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4446 rval = mb0 & MBS_MASK;
4447 else
4448 rval = QLA_FUNCTION_FAILED;
4449
4450 if (rval != QLA_SUCCESS) {
4451 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4452 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
4453 } else {
4454 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4455 "Done %s.\n", __func__);
4456 }
4457
4458 return rval;
4459 }
4460
4461 int
4462 qla2x00_get_data_rate(scsi_qla_host_t *vha)
4463 {
4464 int rval;
4465 mbx_cmd_t mc;
4466 mbx_cmd_t *mcp = &mc;
4467 struct qla_hw_data *ha = vha->hw;
4468
4469 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
4470 "Entered %s.\n", __func__);
4471
4472 if (!IS_FWI2_CAPABLE(ha))
4473 return QLA_FUNCTION_FAILED;
4474
4475 mcp->mb[0] = MBC_DATA_RATE;
4476 mcp->mb[1] = 0;
4477 mcp->out_mb = MBX_1|MBX_0;
4478 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4479 if (IS_QLA83XX(ha))
4480 mcp->in_mb |= MBX_3;
4481 mcp->tov = MBX_TOV_SECONDS;
4482 mcp->flags = 0;
4483 rval = qla2x00_mailbox_command(vha, mcp);
4484 if (rval != QLA_SUCCESS) {
4485 ql_dbg(ql_dbg_mbx, vha, 0x1107,
4486 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4487 } else {
4488 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
4489 "Done %s.\n", __func__);
4490 if (mcp->mb[1] != 0x7)
4491 ha->link_data_rate = mcp->mb[1];
4492 }
4493
4494 return rval;
4495 }
4496
4497 int
4498 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4499 {
4500 int rval;
4501 mbx_cmd_t mc;
4502 mbx_cmd_t *mcp = &mc;
4503 struct qla_hw_data *ha = vha->hw;
4504
4505 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
4506 "Entered %s.\n", __func__);
4507
4508 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha))
4509 return QLA_FUNCTION_FAILED;
4510 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4511 mcp->out_mb = MBX_0;
4512 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4513 mcp->tov = MBX_TOV_SECONDS;
4514 mcp->flags = 0;
4515
4516 rval = qla2x00_mailbox_command(vha, mcp);
4517
4518 if (rval != QLA_SUCCESS) {
4519 ql_dbg(ql_dbg_mbx, vha, 0x110a,
4520 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4521 } else {
4522 /* Copy all bits to preserve original value */
4523 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
4524
4525 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
4526 "Done %s.\n", __func__);
4527 }
4528 return rval;
4529 }
4530
4531 int
4532 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4533 {
4534 int rval;
4535 mbx_cmd_t mc;
4536 mbx_cmd_t *mcp = &mc;
4537
4538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
4539 "Entered %s.\n", __func__);
4540
4541 mcp->mb[0] = MBC_SET_PORT_CONFIG;
4542 /* Copy all bits to preserve original setting */
4543 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
4544 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4545 mcp->in_mb = MBX_0;
4546 mcp->tov = MBX_TOV_SECONDS;
4547 mcp->flags = 0;
4548 rval = qla2x00_mailbox_command(vha, mcp);
4549
4550 if (rval != QLA_SUCCESS) {
4551 ql_dbg(ql_dbg_mbx, vha, 0x110d,
4552 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4553 } else
4554 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
4555 "Done %s.\n", __func__);
4556
4557 return rval;
4558 }
4559
4560
4561 int
4562 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
4563 uint16_t *mb)
4564 {
4565 int rval;
4566 mbx_cmd_t mc;
4567 mbx_cmd_t *mcp = &mc;
4568 struct qla_hw_data *ha = vha->hw;
4569
4570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
4571 "Entered %s.\n", __func__);
4572
4573 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
4574 return QLA_FUNCTION_FAILED;
4575
4576 mcp->mb[0] = MBC_PORT_PARAMS;
4577 mcp->mb[1] = loop_id;
4578 if (ha->flags.fcp_prio_enabled)
4579 mcp->mb[2] = BIT_1;
4580 else
4581 mcp->mb[2] = BIT_2;
4582 mcp->mb[4] = priority & 0xf;
4583 mcp->mb[9] = vha->vp_idx;
4584 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4585 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4586 mcp->tov = 30;
4587 mcp->flags = 0;
4588 rval = qla2x00_mailbox_command(vha, mcp);
4589 if (mb != NULL) {
4590 mb[0] = mcp->mb[0];
4591 mb[1] = mcp->mb[1];
4592 mb[3] = mcp->mb[3];
4593 mb[4] = mcp->mb[4];
4594 }
4595
4596 if (rval != QLA_SUCCESS) {
4597 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
4598 } else {
4599 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
4600 "Done %s.\n", __func__);
4601 }
4602
4603 return rval;
4604 }
4605
4606 int
4607 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
4608 {
4609 int rval = QLA_FUNCTION_FAILED;
4610 struct qla_hw_data *ha = vha->hw;
4611 uint8_t byte;
4612
4613 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
4614 ql_dbg(ql_dbg_mbx, vha, 0x1150,
4615 "Thermal not supported by this card.\n");
4616 return rval;
4617 }
4618
4619 if (IS_QLA25XX(ha)) {
4620 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4621 ha->pdev->subsystem_device == 0x0175) {
4622 rval = qla2x00_read_sfp(vha, 0, &byte,
4623 0x98, 0x1, 1, BIT_13|BIT_0);
4624 *temp = byte;
4625 return rval;
4626 }
4627 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
4628 ha->pdev->subsystem_device == 0x338e) {
4629 rval = qla2x00_read_sfp(vha, 0, &byte,
4630 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
4631 *temp = byte;
4632 return rval;
4633 }
4634 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
4635 "Thermal not supported by this card.\n");
4636 return rval;
4637 }
4638
4639 if (IS_QLA82XX(ha)) {
4640 *temp = qla82xx_read_temperature(vha);
4641 rval = QLA_SUCCESS;
4642 return rval;
4643 } else if (IS_QLA8044(ha)) {
4644 *temp = qla8044_read_temperature(vha);
4645 rval = QLA_SUCCESS;
4646 return rval;
4647 }
4648
4649 rval = qla2x00_read_asic_temperature(vha, temp);
4650 return rval;
4651 }
4652
4653 int
4654 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
4655 {
4656 int rval;
4657 struct qla_hw_data *ha = vha->hw;
4658 mbx_cmd_t mc;
4659 mbx_cmd_t *mcp = &mc;
4660
4661 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
4662 "Entered %s.\n", __func__);
4663
4664 if (!IS_FWI2_CAPABLE(ha))
4665 return QLA_FUNCTION_FAILED;
4666
4667 memset(mcp, 0, sizeof(mbx_cmd_t));
4668 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4669 mcp->mb[1] = 1;
4670
4671 mcp->out_mb = MBX_1|MBX_0;
4672 mcp->in_mb = MBX_0;
4673 mcp->tov = 30;
4674 mcp->flags = 0;
4675
4676 rval = qla2x00_mailbox_command(vha, mcp);
4677 if (rval != QLA_SUCCESS) {
4678 ql_dbg(ql_dbg_mbx, vha, 0x1016,
4679 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4680 } else {
4681 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
4682 "Done %s.\n", __func__);
4683 }
4684
4685 return rval;
4686 }
4687
4688 int
4689 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
4690 {
4691 int rval;
4692 struct qla_hw_data *ha = vha->hw;
4693 mbx_cmd_t mc;
4694 mbx_cmd_t *mcp = &mc;
4695
4696 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
4697 "Entered %s.\n", __func__);
4698
4699 if (!IS_P3P_TYPE(ha))
4700 return QLA_FUNCTION_FAILED;
4701
4702 memset(mcp, 0, sizeof(mbx_cmd_t));
4703 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4704 mcp->mb[1] = 0;
4705
4706 mcp->out_mb = MBX_1|MBX_0;
4707 mcp->in_mb = MBX_0;
4708 mcp->tov = 30;
4709 mcp->flags = 0;
4710
4711 rval = qla2x00_mailbox_command(vha, mcp);
4712 if (rval != QLA_SUCCESS) {
4713 ql_dbg(ql_dbg_mbx, vha, 0x100c,
4714 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4715 } else {
4716 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
4717 "Done %s.\n", __func__);
4718 }
4719
4720 return rval;
4721 }
4722
4723 int
4724 qla82xx_md_get_template_size(scsi_qla_host_t *vha)
4725 {
4726 struct qla_hw_data *ha = vha->hw;
4727 mbx_cmd_t mc;
4728 mbx_cmd_t *mcp = &mc;
4729 int rval = QLA_FUNCTION_FAILED;
4730
4731 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
4732 "Entered %s.\n", __func__);
4733
4734 memset(mcp->mb, 0 , sizeof(mcp->mb));
4735 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4736 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4737 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
4738 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
4739
4740 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4741 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
4742 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4743
4744 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4745 mcp->tov = MBX_TOV_SECONDS;
4746 rval = qla2x00_mailbox_command(vha, mcp);
4747
4748 /* Always copy back return mailbox values. */
4749 if (rval != QLA_SUCCESS) {
4750 ql_dbg(ql_dbg_mbx, vha, 0x1120,
4751 "mailbox command FAILED=0x%x, subcode=%x.\n",
4752 (mcp->mb[1] << 16) | mcp->mb[0],
4753 (mcp->mb[3] << 16) | mcp->mb[2]);
4754 } else {
4755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
4756 "Done %s.\n", __func__);
4757 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
4758 if (!ha->md_template_size) {
4759 ql_dbg(ql_dbg_mbx, vha, 0x1122,
4760 "Null template size obtained.\n");
4761 rval = QLA_FUNCTION_FAILED;
4762 }
4763 }
4764 return rval;
4765 }
4766
4767 int
4768 qla82xx_md_get_template(scsi_qla_host_t *vha)
4769 {
4770 struct qla_hw_data *ha = vha->hw;
4771 mbx_cmd_t mc;
4772 mbx_cmd_t *mcp = &mc;
4773 int rval = QLA_FUNCTION_FAILED;
4774
4775 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
4776 "Entered %s.\n", __func__);
4777
4778 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4779 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4780 if (!ha->md_tmplt_hdr) {
4781 ql_log(ql_log_warn, vha, 0x1124,
4782 "Unable to allocate memory for Minidump template.\n");
4783 return rval;
4784 }
4785
4786 memset(mcp->mb, 0 , sizeof(mcp->mb));
4787 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4788 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4789 mcp->mb[2] = LSW(RQST_TMPLT);
4790 mcp->mb[3] = MSW(RQST_TMPLT);
4791 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
4792 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
4793 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
4794 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
4795 mcp->mb[8] = LSW(ha->md_template_size);
4796 mcp->mb[9] = MSW(ha->md_template_size);
4797
4798 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4799 mcp->tov = MBX_TOV_SECONDS;
4800 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4801 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4802 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4803 rval = qla2x00_mailbox_command(vha, mcp);
4804
4805 if (rval != QLA_SUCCESS) {
4806 ql_dbg(ql_dbg_mbx, vha, 0x1125,
4807 "mailbox command FAILED=0x%x, subcode=%x.\n",
4808 ((mcp->mb[1] << 16) | mcp->mb[0]),
4809 ((mcp->mb[3] << 16) | mcp->mb[2]));
4810 } else
4811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
4812 "Done %s.\n", __func__);
4813 return rval;
4814 }
4815
4816 int
4817 qla8044_md_get_template(scsi_qla_host_t *vha)
4818 {
4819 struct qla_hw_data *ha = vha->hw;
4820 mbx_cmd_t mc;
4821 mbx_cmd_t *mcp = &mc;
4822 int rval = QLA_FUNCTION_FAILED;
4823 int offset = 0, size = MINIDUMP_SIZE_36K;
4824 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
4825 "Entered %s.\n", __func__);
4826
4827 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4828 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4829 if (!ha->md_tmplt_hdr) {
4830 ql_log(ql_log_warn, vha, 0xb11b,
4831 "Unable to allocate memory for Minidump template.\n");
4832 return rval;
4833 }
4834
4835 memset(mcp->mb, 0 , sizeof(mcp->mb));
4836 while (offset < ha->md_template_size) {
4837 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4838 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4839 mcp->mb[2] = LSW(RQST_TMPLT);
4840 mcp->mb[3] = MSW(RQST_TMPLT);
4841 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
4842 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
4843 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
4844 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
4845 mcp->mb[8] = LSW(size);
4846 mcp->mb[9] = MSW(size);
4847 mcp->mb[10] = offset & 0x0000FFFF;
4848 mcp->mb[11] = offset & 0xFFFF0000;
4849 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4850 mcp->tov = MBX_TOV_SECONDS;
4851 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4852 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4853 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4854 rval = qla2x00_mailbox_command(vha, mcp);
4855
4856 if (rval != QLA_SUCCESS) {
4857 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
4858 "mailbox command FAILED=0x%x, subcode=%x.\n",
4859 ((mcp->mb[1] << 16) | mcp->mb[0]),
4860 ((mcp->mb[3] << 16) | mcp->mb[2]));
4861 return rval;
4862 } else
4863 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
4864 "Done %s.\n", __func__);
4865 offset = offset + size;
4866 }
4867 return rval;
4868 }
4869
4870 int
4871 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4872 {
4873 int rval;
4874 struct qla_hw_data *ha = vha->hw;
4875 mbx_cmd_t mc;
4876 mbx_cmd_t *mcp = &mc;
4877
4878 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
4879 return QLA_FUNCTION_FAILED;
4880
4881 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
4882 "Entered %s.\n", __func__);
4883
4884 memset(mcp, 0, sizeof(mbx_cmd_t));
4885 mcp->mb[0] = MBC_SET_LED_CONFIG;
4886 mcp->mb[1] = led_cfg[0];
4887 mcp->mb[2] = led_cfg[1];
4888 if (IS_QLA8031(ha)) {
4889 mcp->mb[3] = led_cfg[2];
4890 mcp->mb[4] = led_cfg[3];
4891 mcp->mb[5] = led_cfg[4];
4892 mcp->mb[6] = led_cfg[5];
4893 }
4894
4895 mcp->out_mb = MBX_2|MBX_1|MBX_0;
4896 if (IS_QLA8031(ha))
4897 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
4898 mcp->in_mb = MBX_0;
4899 mcp->tov = 30;
4900 mcp->flags = 0;
4901
4902 rval = qla2x00_mailbox_command(vha, mcp);
4903 if (rval != QLA_SUCCESS) {
4904 ql_dbg(ql_dbg_mbx, vha, 0x1134,
4905 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4906 } else {
4907 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
4908 "Done %s.\n", __func__);
4909 }
4910
4911 return rval;
4912 }
4913
4914 int
4915 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4916 {
4917 int rval;
4918 struct qla_hw_data *ha = vha->hw;
4919 mbx_cmd_t mc;
4920 mbx_cmd_t *mcp = &mc;
4921
4922 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
4923 return QLA_FUNCTION_FAILED;
4924
4925 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
4926 "Entered %s.\n", __func__);
4927
4928 memset(mcp, 0, sizeof(mbx_cmd_t));
4929 mcp->mb[0] = MBC_GET_LED_CONFIG;
4930
4931 mcp->out_mb = MBX_0;
4932 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4933 if (IS_QLA8031(ha))
4934 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
4935 mcp->tov = 30;
4936 mcp->flags = 0;
4937
4938 rval = qla2x00_mailbox_command(vha, mcp);
4939 if (rval != QLA_SUCCESS) {
4940 ql_dbg(ql_dbg_mbx, vha, 0x1137,
4941 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4942 } else {
4943 led_cfg[0] = mcp->mb[1];
4944 led_cfg[1] = mcp->mb[2];
4945 if (IS_QLA8031(ha)) {
4946 led_cfg[2] = mcp->mb[3];
4947 led_cfg[3] = mcp->mb[4];
4948 led_cfg[4] = mcp->mb[5];
4949 led_cfg[5] = mcp->mb[6];
4950 }
4951 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
4952 "Done %s.\n", __func__);
4953 }
4954
4955 return rval;
4956 }
4957
4958 int
4959 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
4960 {
4961 int rval;
4962 struct qla_hw_data *ha = vha->hw;
4963 mbx_cmd_t mc;
4964 mbx_cmd_t *mcp = &mc;
4965
4966 if (!IS_P3P_TYPE(ha))
4967 return QLA_FUNCTION_FAILED;
4968
4969 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
4970 "Entered %s.\n", __func__);
4971
4972 memset(mcp, 0, sizeof(mbx_cmd_t));
4973 mcp->mb[0] = MBC_SET_LED_CONFIG;
4974 if (enable)
4975 mcp->mb[7] = 0xE;
4976 else
4977 mcp->mb[7] = 0xD;
4978
4979 mcp->out_mb = MBX_7|MBX_0;
4980 mcp->in_mb = MBX_0;
4981 mcp->tov = MBX_TOV_SECONDS;
4982 mcp->flags = 0;
4983
4984 rval = qla2x00_mailbox_command(vha, mcp);
4985 if (rval != QLA_SUCCESS) {
4986 ql_dbg(ql_dbg_mbx, vha, 0x1128,
4987 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4988 } else {
4989 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
4990 "Done %s.\n", __func__);
4991 }
4992
4993 return rval;
4994 }
4995
4996 int
4997 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
4998 {
4999 int rval;
5000 struct qla_hw_data *ha = vha->hw;
5001 mbx_cmd_t mc;
5002 mbx_cmd_t *mcp = &mc;
5003
5004 if (!IS_QLA83XX(ha))
5005 return QLA_FUNCTION_FAILED;
5006
5007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5008 "Entered %s.\n", __func__);
5009
5010 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5011 mcp->mb[1] = LSW(reg);
5012 mcp->mb[2] = MSW(reg);
5013 mcp->mb[3] = LSW(data);
5014 mcp->mb[4] = MSW(data);
5015 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5016
5017 mcp->in_mb = MBX_1|MBX_0;
5018 mcp->tov = MBX_TOV_SECONDS;
5019 mcp->flags = 0;
5020 rval = qla2x00_mailbox_command(vha, mcp);
5021
5022 if (rval != QLA_SUCCESS) {
5023 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5024 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5025 } else {
5026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
5027 "Done %s.\n", __func__);
5028 }
5029
5030 return rval;
5031 }
5032
5033 int
5034 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5035 {
5036 int rval;
5037 struct qla_hw_data *ha = vha->hw;
5038 mbx_cmd_t mc;
5039 mbx_cmd_t *mcp = &mc;
5040
5041 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5042 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
5043 "Implicit LOGO Unsupported.\n");
5044 return QLA_FUNCTION_FAILED;
5045 }
5046
5047
5048 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5049 "Entering %s.\n", __func__);
5050
5051 /* Perform Implicit LOGO. */
5052 mcp->mb[0] = MBC_PORT_LOGOUT;
5053 mcp->mb[1] = fcport->loop_id;
5054 mcp->mb[10] = BIT_15;
5055 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5056 mcp->in_mb = MBX_0;
5057 mcp->tov = MBX_TOV_SECONDS;
5058 mcp->flags = 0;
5059 rval = qla2x00_mailbox_command(vha, mcp);
5060 if (rval != QLA_SUCCESS)
5061 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5062 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5063 else
5064 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5065 "Done %s.\n", __func__);
5066
5067 return rval;
5068 }
5069
5070 int
5071 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5072 {
5073 int rval;
5074 mbx_cmd_t mc;
5075 mbx_cmd_t *mcp = &mc;
5076 struct qla_hw_data *ha = vha->hw;
5077 unsigned long retry_max_time = jiffies + (2 * HZ);
5078
5079 if (!IS_QLA83XX(ha))
5080 return QLA_FUNCTION_FAILED;
5081
5082 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5083
5084 retry_rd_reg:
5085 mcp->mb[0] = MBC_READ_REMOTE_REG;
5086 mcp->mb[1] = LSW(reg);
5087 mcp->mb[2] = MSW(reg);
5088 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5089 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5090 mcp->tov = MBX_TOV_SECONDS;
5091 mcp->flags = 0;
5092 rval = qla2x00_mailbox_command(vha, mcp);
5093
5094 if (rval != QLA_SUCCESS) {
5095 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5096 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5097 rval, mcp->mb[0], mcp->mb[1]);
5098 } else {
5099 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5100 if (*data == QLA8XXX_BAD_VALUE) {
5101 /*
5102 * During soft-reset CAMRAM register reads might
5103 * return 0xbad0bad0. So retry for MAX of 2 sec
5104 * while reading camram registers.
5105 */
5106 if (time_after(jiffies, retry_max_time)) {
5107 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5108 "Failure to read CAMRAM register. "
5109 "data=0x%x.\n", *data);
5110 return QLA_FUNCTION_FAILED;
5111 }
5112 msleep(100);
5113 goto retry_rd_reg;
5114 }
5115 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5116 }
5117
5118 return rval;
5119 }
5120
5121 int
5122 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5123 {
5124 int rval;
5125 mbx_cmd_t mc;
5126 mbx_cmd_t *mcp = &mc;
5127 struct qla_hw_data *ha = vha->hw;
5128
5129 if (!IS_QLA83XX(ha))
5130 return QLA_FUNCTION_FAILED;
5131
5132 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5133
5134 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5135 mcp->out_mb = MBX_0;
5136 mcp->in_mb = MBX_1|MBX_0;
5137 mcp->tov = MBX_TOV_SECONDS;
5138 mcp->flags = 0;
5139 rval = qla2x00_mailbox_command(vha, mcp);
5140
5141 if (rval != QLA_SUCCESS) {
5142 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5143 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5144 rval, mcp->mb[0], mcp->mb[1]);
5145 ha->isp_ops->fw_dump(vha, 0);
5146 } else {
5147 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5148 }
5149
5150 return rval;
5151 }
5152
5153 int
5154 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5155 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5156 {
5157 int rval;
5158 mbx_cmd_t mc;
5159 mbx_cmd_t *mcp = &mc;
5160 uint8_t subcode = (uint8_t)options;
5161 struct qla_hw_data *ha = vha->hw;
5162
5163 if (!IS_QLA8031(ha))
5164 return QLA_FUNCTION_FAILED;
5165
5166 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5167
5168 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5169 mcp->mb[1] = options;
5170 mcp->out_mb = MBX_1|MBX_0;
5171 if (subcode & BIT_2) {
5172 mcp->mb[2] = LSW(start_addr);
5173 mcp->mb[3] = MSW(start_addr);
5174 mcp->mb[4] = LSW(end_addr);
5175 mcp->mb[5] = MSW(end_addr);
5176 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5177 }
5178 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5179 if (!(subcode & (BIT_2 | BIT_5)))
5180 mcp->in_mb |= MBX_4|MBX_3;
5181 mcp->tov = MBX_TOV_SECONDS;
5182 mcp->flags = 0;
5183 rval = qla2x00_mailbox_command(vha, mcp);
5184
5185 if (rval != QLA_SUCCESS) {
5186 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5187 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5188 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5189 mcp->mb[4]);
5190 ha->isp_ops->fw_dump(vha, 0);
5191 } else {
5192 if (subcode & BIT_5)
5193 *sector_size = mcp->mb[1];
5194 else if (subcode & (BIT_6 | BIT_7)) {
5195 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5196 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5197 } else if (subcode & (BIT_3 | BIT_4)) {
5198 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5199 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5200 }
5201 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5202 }
5203
5204 return rval;
5205 }
5206
5207 int
5208 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5209 uint32_t size)
5210 {
5211 int rval;
5212 mbx_cmd_t mc;
5213 mbx_cmd_t *mcp = &mc;
5214
5215 if (!IS_MCTP_CAPABLE(vha->hw))
5216 return QLA_FUNCTION_FAILED;
5217
5218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5219 "Entered %s.\n", __func__);
5220
5221 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5222 mcp->mb[1] = LSW(addr);
5223 mcp->mb[2] = MSW(req_dma);
5224 mcp->mb[3] = LSW(req_dma);
5225 mcp->mb[4] = MSW(size);
5226 mcp->mb[5] = LSW(size);
5227 mcp->mb[6] = MSW(MSD(req_dma));
5228 mcp->mb[7] = LSW(MSD(req_dma));
5229 mcp->mb[8] = MSW(addr);
5230 /* Setting RAM ID to valid */
5231 mcp->mb[10] |= BIT_7;
5232 /* For MCTP RAM ID is 0x40 */
5233 mcp->mb[10] |= 0x40;
5234
5235 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5236 MBX_0;
5237
5238 mcp->in_mb = MBX_0;
5239 mcp->tov = MBX_TOV_SECONDS;
5240 mcp->flags = 0;
5241 rval = qla2x00_mailbox_command(vha, mcp);
5242
5243 if (rval != QLA_SUCCESS) {
5244 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5245 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5246 } else {
5247 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5248 "Done %s.\n", __func__);
5249 }
5250
5251 return rval;
5252 }
Linux with added FPC-III support