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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux/fpc-iii.git] / drivers / gpio / gpio-tegra.c
blobec891a27952f88e33bd9a7d6f6bfe6e5069f995a
1 /*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/module.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm.h>
33
34 #define GPIO_BANK(x) ((x) >> 5)
35 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
36 #define GPIO_BIT(x) ((x) & 0x7)
37
38 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
39 GPIO_PORT(x) * 4)
40
41 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
49 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
50
51
52 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
55 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
56 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
59
60 #define GPIO_INT_LVL_MASK 0x010101
61 #define GPIO_INT_LVL_EDGE_RISING 0x000101
62 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
63 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
64 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
66
67 struct tegra_gpio_info;
68
69 struct tegra_gpio_bank {
70 int bank;
71 int irq;
72 spinlock_t lvl_lock[4];
73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
74 #ifdef CONFIG_PM_SLEEP
75 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
80 u32 wake_enb[4];
81 u32 dbc_enb[4];
82 #endif
83 u32 dbc_cnt[4];
84 struct tegra_gpio_info *tgi;
85 };
86
87 struct tegra_gpio_soc_config {
88 bool debounce_supported;
89 u32 bank_stride;
90 u32 upper_offset;
91 };
92
93 struct tegra_gpio_info {
94 struct device *dev;
95 void __iomem *regs;
96 struct irq_domain *irq_domain;
97 struct tegra_gpio_bank *bank_info;
98 const struct tegra_gpio_soc_config *soc;
99 struct gpio_chip gc;
100 struct irq_chip ic;
101 struct lock_class_key lock_class;
102 u32 bank_count;
103 };
104
105 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
106 u32 val, u32 reg)
107 {
108 __raw_writel(val, tgi->regs + reg);
109 }
110
111 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
112 {
113 return __raw_readl(tgi->regs + reg);
114 }
115
116 static int tegra_gpio_compose(int bank, int port, int bit)
117 {
118 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
119 }
120
121 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
122 int gpio, int value)
123 {
124 u32 val;
125
126 val = 0x100 << GPIO_BIT(gpio);
127 if (value)
128 val |= 1 << GPIO_BIT(gpio);
129 tegra_gpio_writel(tgi, val, reg);
130 }
131
132 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio)
133 {
134 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
135 }
136
137 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio)
138 {
139 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
140 }
141
142 static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
143 {
144 return pinctrl_request_gpio(offset);
145 }
146
147 static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
148 {
149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
150
151 pinctrl_free_gpio(offset);
152 tegra_gpio_disable(tgi, offset);
153 }
154
155 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
156 {
157 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
158
159 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
160 }
161
162 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
163 {
164 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
165 int bval = BIT(GPIO_BIT(offset));
166
167 /* If gpio is in output mode then read from the out value */
168 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
169 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
170
171 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
172 }
173
174 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
175 {
176 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
177
178 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
179 tegra_gpio_enable(tgi, offset);
180 return 0;
181 }
182
183 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
184 int value)
185 {
186 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
187
188 tegra_gpio_set(chip, offset, value);
189 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
190 tegra_gpio_enable(tgi, offset);
191 return 0;
192 }
193
194 static int tegra_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
195 {
196 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
197 u32 pin_mask = BIT(GPIO_BIT(offset));
198 u32 cnf, oe;
199
200 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
201 if (!(cnf & pin_mask))
202 return -EINVAL;
203
204 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
205
206 return (oe & pin_mask) ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
207 }
208
209 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
210 unsigned int debounce)
211 {
212 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
213 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
214 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
215 unsigned long flags;
216 int port;
217
218 if (!debounce_ms) {
219 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
220 offset, 0);
221 return 0;
222 }
223
224 debounce_ms = min(debounce_ms, 255U);
225 port = GPIO_PORT(offset);
226
227 /* There is only one debounce count register per port and hence
228 * set the maximum of current and requested debounce time.
229 */
230 spin_lock_irqsave(&bank->dbc_lock[port], flags);
231 if (bank->dbc_cnt[port] < debounce_ms) {
232 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
233 bank->dbc_cnt[port] = debounce_ms;
234 }
235 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
236
237 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
238
239 return 0;
240 }
241
242 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
243 {
244 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
245
246 return irq_find_mapping(tgi->irq_domain, offset);
247 }
248
249 static void tegra_gpio_irq_ack(struct irq_data *d)
250 {
251 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
252 struct tegra_gpio_info *tgi = bank->tgi;
253 int gpio = d->hwirq;
254
255 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
256 }
257
258 static void tegra_gpio_irq_mask(struct irq_data *d)
259 {
260 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
261 struct tegra_gpio_info *tgi = bank->tgi;
262 int gpio = d->hwirq;
263
264 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
265 }
266
267 static void tegra_gpio_irq_unmask(struct irq_data *d)
268 {
269 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
270 struct tegra_gpio_info *tgi = bank->tgi;
271 int gpio = d->hwirq;
272
273 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
274 }
275
276 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
277 {
278 int gpio = d->hwirq;
279 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
280 struct tegra_gpio_info *tgi = bank->tgi;
281 int port = GPIO_PORT(gpio);
282 int lvl_type;
283 int val;
284 unsigned long flags;
285 int ret;
286
287 switch (type & IRQ_TYPE_SENSE_MASK) {
288 case IRQ_TYPE_EDGE_RISING:
289 lvl_type = GPIO_INT_LVL_EDGE_RISING;
290 break;
291
292 case IRQ_TYPE_EDGE_FALLING:
293 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
294 break;
295
296 case IRQ_TYPE_EDGE_BOTH:
297 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
298 break;
299
300 case IRQ_TYPE_LEVEL_HIGH:
301 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
302 break;
303
304 case IRQ_TYPE_LEVEL_LOW:
305 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
306 break;
307
308 default:
309 return -EINVAL;
310 }
311
312 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
313 if (ret) {
314 dev_err(tgi->dev,
315 "unable to lock Tegra GPIO %d as IRQ\n", gpio);
316 return ret;
317 }
318
319 spin_lock_irqsave(&bank->lvl_lock[port], flags);
320
321 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
322 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
323 val |= lvl_type << GPIO_BIT(gpio);
324 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
325
326 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
327
328 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
329 tegra_gpio_enable(tgi, gpio);
330
331 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
332 irq_set_handler_locked(d, handle_level_irq);
333 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
334 irq_set_handler_locked(d, handle_edge_irq);
335
336 return 0;
337 }
338
339 static void tegra_gpio_irq_shutdown(struct irq_data *d)
340 {
341 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
342 struct tegra_gpio_info *tgi = bank->tgi;
343 int gpio = d->hwirq;
344
345 gpiochip_unlock_as_irq(&tgi->gc, gpio);
346 }
347
348 static void tegra_gpio_irq_handler(struct irq_desc *desc)
349 {
350 int port;
351 int pin;
352 int unmasked = 0;
353 int gpio;
354 u32 lvl;
355 unsigned long sta;
356 struct irq_chip *chip = irq_desc_get_chip(desc);
357 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
358 struct tegra_gpio_info *tgi = bank->tgi;
359
360 chained_irq_enter(chip, desc);
361
362 for (port = 0; port < 4; port++) {
363 gpio = tegra_gpio_compose(bank->bank, port, 0);
364 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
365 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
366 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
367
368 for_each_set_bit(pin, &sta, 8) {
369 tegra_gpio_writel(tgi, 1 << pin,
370 GPIO_INT_CLR(tgi, gpio));
371
372 /* if gpio is edge triggered, clear condition
373 * before executing the handler so that we don't
374 * miss edges
375 */
376 if (lvl & (0x100 << pin)) {
377 unmasked = 1;
378 chained_irq_exit(chip, desc);
379 }
380
381 generic_handle_irq(gpio_to_irq(gpio + pin));
382 }
383 }
384
385 if (!unmasked)
386 chained_irq_exit(chip, desc);
387
388 }
389
390 #ifdef CONFIG_PM_SLEEP
391 static int tegra_gpio_resume(struct device *dev)
392 {
393 struct platform_device *pdev = to_platform_device(dev);
394 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
395 unsigned long flags;
396 int b;
397 int p;
398
399 local_irq_save(flags);
400
401 for (b = 0; b < tgi->bank_count; b++) {
402 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
403
404 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
405 unsigned int gpio = (b<<5) | (p<<3);
406 tegra_gpio_writel(tgi, bank->cnf[p],
407 GPIO_CNF(tgi, gpio));
408
409 if (tgi->soc->debounce_supported) {
410 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
411 GPIO_DBC_CNT(tgi, gpio));
412 tegra_gpio_writel(tgi, bank->dbc_enb[p],
413 GPIO_MSK_DBC_EN(tgi, gpio));
414 }
415
416 tegra_gpio_writel(tgi, bank->out[p],
417 GPIO_OUT(tgi, gpio));
418 tegra_gpio_writel(tgi, bank->oe[p],
419 GPIO_OE(tgi, gpio));
420 tegra_gpio_writel(tgi, bank->int_lvl[p],
421 GPIO_INT_LVL(tgi, gpio));
422 tegra_gpio_writel(tgi, bank->int_enb[p],
423 GPIO_INT_ENB(tgi, gpio));
424 }
425 }
426
427 local_irq_restore(flags);
428 return 0;
429 }
430
431 static int tegra_gpio_suspend(struct device *dev)
432 {
433 struct platform_device *pdev = to_platform_device(dev);
434 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
435 unsigned long flags;
436 int b;
437 int p;
438
439 local_irq_save(flags);
440 for (b = 0; b < tgi->bank_count; b++) {
441 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
442
443 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
444 unsigned int gpio = (b<<5) | (p<<3);
445 bank->cnf[p] = tegra_gpio_readl(tgi,
446 GPIO_CNF(tgi, gpio));
447 bank->out[p] = tegra_gpio_readl(tgi,
448 GPIO_OUT(tgi, gpio));
449 bank->oe[p] = tegra_gpio_readl(tgi,
450 GPIO_OE(tgi, gpio));
451 if (tgi->soc->debounce_supported) {
452 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
453 GPIO_MSK_DBC_EN(tgi, gpio));
454 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
455 bank->dbc_enb[p];
456 }
457
458 bank->int_enb[p] = tegra_gpio_readl(tgi,
459 GPIO_INT_ENB(tgi, gpio));
460 bank->int_lvl[p] = tegra_gpio_readl(tgi,
461 GPIO_INT_LVL(tgi, gpio));
462
463 /* Enable gpio irq for wake up source */
464 tegra_gpio_writel(tgi, bank->wake_enb[p],
465 GPIO_INT_ENB(tgi, gpio));
466 }
467 }
468 local_irq_restore(flags);
469 return 0;
470 }
471
472 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
473 {
474 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
475 int gpio = d->hwirq;
476 u32 port, bit, mask;
477
478 port = GPIO_PORT(gpio);
479 bit = GPIO_BIT(gpio);
480 mask = BIT(bit);
481
482 if (enable)
483 bank->wake_enb[port] |= mask;
484 else
485 bank->wake_enb[port] &= ~mask;
486
487 return irq_set_irq_wake(bank->irq, enable);
488 }
489 #endif
490
491 #ifdef CONFIG_DEBUG_FS
492
493 #include <linux/debugfs.h>
494 #include <linux/seq_file.h>
495
496 static int dbg_gpio_show(struct seq_file *s, void *unused)
497 {
498 struct tegra_gpio_info *tgi = s->private;
499 int i;
500 int j;
501
502 for (i = 0; i < tgi->bank_count; i++) {
503 for (j = 0; j < 4; j++) {
504 int gpio = tegra_gpio_compose(i, j, 0);
505 seq_printf(s,
506 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
507 i, j,
508 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
509 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
510 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
511 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
512 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
513 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
514 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
515 }
516 }
517 return 0;
518 }
519
520 static int dbg_gpio_open(struct inode *inode, struct file *file)
521 {
522 return single_open(file, dbg_gpio_show, inode->i_private);
523 }
524
525 static const struct file_operations debug_fops = {
526 .open = dbg_gpio_open,
527 .read = seq_read,
528 .llseek = seq_lseek,
529 .release = single_release,
530 };
531
532 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
533 {
534 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
535 NULL, tgi, &debug_fops);
536 }
537
538 #else
539
540 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
541 {
542 }
543
544 #endif
545
546 static const struct dev_pm_ops tegra_gpio_pm_ops = {
547 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
548 };
549
550 static int tegra_gpio_probe(struct platform_device *pdev)
551 {
552 const struct tegra_gpio_soc_config *config;
553 struct tegra_gpio_info *tgi;
554 struct resource *res;
555 struct tegra_gpio_bank *bank;
556 int ret;
557 int gpio;
558 int i;
559 int j;
560
561 config = of_device_get_match_data(&pdev->dev);
562 if (!config) {
563 dev_err(&pdev->dev, "Error: No device match found\n");
564 return -ENODEV;
565 }
566
567 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
568 if (!tgi)
569 return -ENODEV;
570
571 tgi->soc = config;
572 tgi->dev = &pdev->dev;
573
574 for (;;) {
575 res = platform_get_resource(pdev, IORESOURCE_IRQ,
576 tgi->bank_count);
577 if (!res)
578 break;
579 tgi->bank_count++;
580 }
581 if (!tgi->bank_count) {
582 dev_err(&pdev->dev, "Missing IRQ resource\n");
583 return -ENODEV;
584 }
585
586 tgi->gc.label = "tegra-gpio";
587 tgi->gc.request = tegra_gpio_request;
588 tgi->gc.free = tegra_gpio_free;
589 tgi->gc.direction_input = tegra_gpio_direction_input;
590 tgi->gc.get = tegra_gpio_get;
591 tgi->gc.direction_output = tegra_gpio_direction_output;
592 tgi->gc.set = tegra_gpio_set;
593 tgi->gc.get_direction = tegra_gpio_get_direction;
594 tgi->gc.to_irq = tegra_gpio_to_irq;
595 tgi->gc.base = 0;
596 tgi->gc.ngpio = tgi->bank_count * 32;
597 tgi->gc.parent = &pdev->dev;
598 tgi->gc.of_node = pdev->dev.of_node;
599
600 tgi->ic.name = "GPIO";
601 tgi->ic.irq_ack = tegra_gpio_irq_ack;
602 tgi->ic.irq_mask = tegra_gpio_irq_mask;
603 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
604 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
605 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
606 #ifdef CONFIG_PM_SLEEP
607 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
608 #endif
609
610 platform_set_drvdata(pdev, tgi);
611
612 if (config->debounce_supported)
613 tgi->gc.set_debounce = tegra_gpio_set_debounce;
614
615 tgi->bank_info = devm_kzalloc(&pdev->dev, tgi->bank_count *
616 sizeof(*tgi->bank_info), GFP_KERNEL);
617 if (!tgi->bank_info)
618 return -ENODEV;
619
620 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
621 tgi->gc.ngpio,
622 &irq_domain_simple_ops, NULL);
623 if (!tgi->irq_domain)
624 return -ENODEV;
625
626 for (i = 0; i < tgi->bank_count; i++) {
627 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
628 if (!res) {
629 dev_err(&pdev->dev, "Missing IRQ resource\n");
630 return -ENODEV;
631 }
632
633 bank = &tgi->bank_info[i];
634 bank->bank = i;
635 bank->irq = res->start;
636 bank->tgi = tgi;
637 }
638
639 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
641 if (IS_ERR(tgi->regs))
642 return PTR_ERR(tgi->regs);
643
644 for (i = 0; i < tgi->bank_count; i++) {
645 for (j = 0; j < 4; j++) {
646 int gpio = tegra_gpio_compose(i, j, 0);
647 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
648 }
649 }
650
651 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
652 if (ret < 0) {
653 irq_domain_remove(tgi->irq_domain);
654 return ret;
655 }
656
657 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
658 int irq = irq_create_mapping(tgi->irq_domain, gpio);
659 /* No validity check; all Tegra GPIOs are valid IRQs */
660
661 bank = &tgi->bank_info[GPIO_BANK(gpio)];
662
663 irq_set_lockdep_class(irq, &tgi->lock_class);
664 irq_set_chip_data(irq, bank);
665 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
666 }
667
668 for (i = 0; i < tgi->bank_count; i++) {
669 bank = &tgi->bank_info[i];
670
671 irq_set_chained_handler_and_data(bank->irq,
672 tegra_gpio_irq_handler, bank);
673
674 for (j = 0; j < 4; j++) {
675 spin_lock_init(&bank->lvl_lock[j]);
676 spin_lock_init(&bank->dbc_lock[j]);
677 }
678 }
679
680 tegra_gpio_debuginit(tgi);
681
682 return 0;
683 }
684
685 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
686 .bank_stride = 0x80,
687 .upper_offset = 0x800,
688 };
689
690 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
691 .bank_stride = 0x100,
692 .upper_offset = 0x80,
693 };
694
695 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
696 .debounce_supported = true,
697 .bank_stride = 0x100,
698 .upper_offset = 0x80,
699 };
700
701 static const struct of_device_id tegra_gpio_of_match[] = {
702 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
703 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
704 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
705 { },
706 };
707
708 static struct platform_driver tegra_gpio_driver = {
709 .driver = {
710 .name = "tegra-gpio",
711 .pm = &tegra_gpio_pm_ops,
712 .of_match_table = tegra_gpio_of_match,
713 },
714 .probe = tegra_gpio_probe,
715 };
716
717 static int __init tegra_gpio_init(void)
718 {
719 return platform_driver_register(&tegra_gpio_driver);
720 }
721 postcore_initcall(tegra_gpio_init);
Linux with added FPC-III support