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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux/fpc-iii.git] / drivers / iommu / mtk_iommu.c
blobc3043d8754e380ceaa763a944f603fe680ab827e
1 /*
2 * Copyright (c) 2015-2016 MediaTek Inc.
3 * Author: Yong Wu <yong.wu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14 #include <linux/bootmem.h>
15 #include <linux/bug.h>
16 #include <linux/clk.h>
17 #include <linux/component.h>
18 #include <linux/device.h>
19 #include <linux/dma-iommu.h>
20 #include <linux/err.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/iommu.h>
24 #include <linux/iopoll.h>
25 #include <linux/list.h>
26 #include <linux/of_address.h>
27 #include <linux/of_iommu.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <asm/barrier.h>
34 #include <dt-bindings/memory/mt8173-larb-port.h>
35 #include <soc/mediatek/smi.h>
36
37 #include "io-pgtable.h"
38
39 #define REG_MMU_PT_BASE_ADDR 0x000
40
41 #define REG_MMU_INVALIDATE 0x020
42 #define F_ALL_INVLD 0x2
43 #define F_MMU_INV_RANGE 0x1
44
45 #define REG_MMU_INVLD_START_A 0x024
46 #define REG_MMU_INVLD_END_A 0x028
47
48 #define REG_MMU_INV_SEL 0x038
49 #define F_INVLD_EN0 BIT(0)
50 #define F_INVLD_EN1 BIT(1)
51
52 #define REG_MMU_STANDARD_AXI_MODE 0x048
53 #define REG_MMU_DCM_DIS 0x050
54
55 #define REG_MMU_CTRL_REG 0x110
56 #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
57 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
58
59 #define REG_MMU_IVRP_PADDR 0x114
60 #define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31))
61
62 #define REG_MMU_INT_CONTROL0 0x120
63 #define F_L2_MULIT_HIT_EN BIT(0)
64 #define F_TABLE_WALK_FAULT_INT_EN BIT(1)
65 #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
66 #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
67 #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
68 #define F_MISS_FIFO_ERR_INT_EN BIT(6)
69 #define F_INT_CLR_BIT BIT(12)
70
71 #define REG_MMU_INT_MAIN_CONTROL 0x124
72 #define F_INT_TRANSLATION_FAULT BIT(0)
73 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
74 #define F_INT_INVALID_PA_FAULT BIT(2)
75 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
76 #define F_INT_TLB_MISS_FAULT BIT(4)
77 #define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
78 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
79
80 #define REG_MMU_CPE_DONE 0x12C
81
82 #define REG_MMU_FAULT_ST1 0x134
83
84 #define REG_MMU_FAULT_VA 0x13c
85 #define F_MMU_FAULT_VA_MSK 0xfffff000
86 #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
87 #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
88
89 #define REG_MMU_INVLD_PA 0x140
90 #define REG_MMU_INT_ID 0x150
91 #define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
92 #define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
93
94 #define MTK_PROTECT_PA_ALIGN 128
95
96 struct mtk_iommu_suspend_reg {
97 u32 standard_axi_mode;
98 u32 dcm_dis;
99 u32 ctrl_reg;
100 u32 int_control0;
101 u32 int_main_control;
102 };
103
104 struct mtk_iommu_client_priv {
105 struct list_head client;
106 unsigned int mtk_m4u_id;
107 struct device *m4udev;
108 };
109
110 struct mtk_iommu_domain {
111 spinlock_t pgtlock; /* lock for page table */
112
113 struct io_pgtable_cfg cfg;
114 struct io_pgtable_ops *iop;
115
116 struct iommu_domain domain;
117 };
118
119 struct mtk_iommu_data {
120 void __iomem *base;
121 int irq;
122 struct device *dev;
123 struct clk *bclk;
124 phys_addr_t protect_base; /* protect memory base */
125 struct mtk_iommu_suspend_reg reg;
126 struct mtk_iommu_domain *m4u_dom;
127 struct iommu_group *m4u_group;
128 struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
129 bool enable_4GB;
130 };
131
132 static struct iommu_ops mtk_iommu_ops;
133
134 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
135 {
136 return container_of(dom, struct mtk_iommu_domain, domain);
137 }
138
139 static void mtk_iommu_tlb_flush_all(void *cookie)
140 {
141 struct mtk_iommu_data *data = cookie;
142
143 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
144 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
145 wmb(); /* Make sure the tlb flush all done */
146 }
147
148 static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
149 size_t granule, bool leaf,
150 void *cookie)
151 {
152 struct mtk_iommu_data *data = cookie;
153
154 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
155
156 writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
157 writel_relaxed(iova + size - 1, data->base + REG_MMU_INVLD_END_A);
158 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
159 }
160
161 static void mtk_iommu_tlb_sync(void *cookie)
162 {
163 struct mtk_iommu_data *data = cookie;
164 int ret;
165 u32 tmp;
166
167 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, tmp,
168 tmp != 0, 10, 100000);
169 if (ret) {
170 dev_warn(data->dev,
171 "Partial TLB flush timed out, falling back to full flush\n");
172 mtk_iommu_tlb_flush_all(cookie);
173 }
174 /* Clear the CPE status */
175 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
176 }
177
178 static const struct iommu_gather_ops mtk_iommu_gather_ops = {
179 .tlb_flush_all = mtk_iommu_tlb_flush_all,
180 .tlb_add_flush = mtk_iommu_tlb_add_flush_nosync,
181 .tlb_sync = mtk_iommu_tlb_sync,
182 };
183
184 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
185 {
186 struct mtk_iommu_data *data = dev_id;
187 struct mtk_iommu_domain *dom = data->m4u_dom;
188 u32 int_state, regval, fault_iova, fault_pa;
189 unsigned int fault_larb, fault_port;
190 bool layer, write;
191
192 /* Read error info from registers */
193 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
194 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
195 layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
196 write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
197 fault_iova &= F_MMU_FAULT_VA_MSK;
198 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
199 regval = readl_relaxed(data->base + REG_MMU_INT_ID);
200 fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
201 fault_port = F_MMU0_INT_ID_PORT_ID(regval);
202
203 if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
204 write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
205 dev_err_ratelimited(
206 data->dev,
207 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
208 int_state, fault_iova, fault_pa, fault_larb, fault_port,
209 layer, write ? "write" : "read");
210 }
211
212 /* Interrupt clear */
213 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
214 regval |= F_INT_CLR_BIT;
215 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
216
217 mtk_iommu_tlb_flush_all(data);
218
219 return IRQ_HANDLED;
220 }
221
222 static void mtk_iommu_config(struct mtk_iommu_data *data,
223 struct device *dev, bool enable)
224 {
225 struct mtk_iommu_client_priv *head, *cur, *next;
226 struct mtk_smi_larb_iommu *larb_mmu;
227 unsigned int larbid, portid;
228
229 head = dev->archdata.iommu;
230 list_for_each_entry_safe(cur, next, &head->client, client) {
231 larbid = MTK_M4U_TO_LARB(cur->mtk_m4u_id);
232 portid = MTK_M4U_TO_PORT(cur->mtk_m4u_id);
233 larb_mmu = &data->smi_imu.larb_imu[larbid];
234
235 dev_dbg(dev, "%s iommu port: %d\n",
236 enable ? "enable" : "disable", portid);
237
238 if (enable)
239 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
240 else
241 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
242 }
243 }
244
245 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
246 {
247 struct mtk_iommu_domain *dom = data->m4u_dom;
248
249 spin_lock_init(&dom->pgtlock);
250
251 dom->cfg = (struct io_pgtable_cfg) {
252 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
253 IO_PGTABLE_QUIRK_NO_PERMS |
254 IO_PGTABLE_QUIRK_TLBI_ON_MAP,
255 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
256 .ias = 32,
257 .oas = 32,
258 .tlb = &mtk_iommu_gather_ops,
259 .iommu_dev = data->dev,
260 };
261
262 if (data->enable_4GB)
263 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB;
264
265 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
266 if (!dom->iop) {
267 dev_err(data->dev, "Failed to alloc io pgtable\n");
268 return -EINVAL;
269 }
270
271 /* Update our support page sizes bitmap */
272 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
273
274 writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
275 data->base + REG_MMU_PT_BASE_ADDR);
276 return 0;
277 }
278
279 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
280 {
281 struct mtk_iommu_domain *dom;
282
283 if (type != IOMMU_DOMAIN_DMA)
284 return NULL;
285
286 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
287 if (!dom)
288 return NULL;
289
290 if (iommu_get_dma_cookie(&dom->domain)) {
291 kfree(dom);
292 return NULL;
293 }
294
295 dom->domain.geometry.aperture_start = 0;
296 dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
297 dom->domain.geometry.force_aperture = true;
298
299 return &dom->domain;
300 }
301
302 static void mtk_iommu_domain_free(struct iommu_domain *domain)
303 {
304 iommu_put_dma_cookie(domain);
305 kfree(to_mtk_domain(domain));
306 }
307
308 static int mtk_iommu_attach_device(struct iommu_domain *domain,
309 struct device *dev)
310 {
311 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
312 struct mtk_iommu_client_priv *priv = dev->archdata.iommu;
313 struct mtk_iommu_data *data;
314 int ret;
315
316 if (!priv)
317 return -ENODEV;
318
319 data = dev_get_drvdata(priv->m4udev);
320 if (!data->m4u_dom) {
321 data->m4u_dom = dom;
322 ret = mtk_iommu_domain_finalise(data);
323 if (ret) {
324 data->m4u_dom = NULL;
325 return ret;
326 }
327 } else if (data->m4u_dom != dom) {
328 /* All the client devices should be in the same m4u domain */
329 dev_err(dev, "try to attach into the error iommu domain\n");
330 return -EPERM;
331 }
332
333 mtk_iommu_config(data, dev, true);
334 return 0;
335 }
336
337 static void mtk_iommu_detach_device(struct iommu_domain *domain,
338 struct device *dev)
339 {
340 struct mtk_iommu_client_priv *priv = dev->archdata.iommu;
341 struct mtk_iommu_data *data;
342
343 if (!priv)
344 return;
345
346 data = dev_get_drvdata(priv->m4udev);
347 mtk_iommu_config(data, dev, false);
348 }
349
350 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
351 phys_addr_t paddr, size_t size, int prot)
352 {
353 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
354 unsigned long flags;
355 int ret;
356
357 spin_lock_irqsave(&dom->pgtlock, flags);
358 ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
359 spin_unlock_irqrestore(&dom->pgtlock, flags);
360
361 return ret;
362 }
363
364 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
365 unsigned long iova, size_t size)
366 {
367 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
368 unsigned long flags;
369 size_t unmapsz;
370
371 spin_lock_irqsave(&dom->pgtlock, flags);
372 unmapsz = dom->iop->unmap(dom->iop, iova, size);
373 spin_unlock_irqrestore(&dom->pgtlock, flags);
374
375 return unmapsz;
376 }
377
378 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
379 dma_addr_t iova)
380 {
381 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
382 unsigned long flags;
383 phys_addr_t pa;
384
385 spin_lock_irqsave(&dom->pgtlock, flags);
386 pa = dom->iop->iova_to_phys(dom->iop, iova);
387 spin_unlock_irqrestore(&dom->pgtlock, flags);
388
389 return pa;
390 }
391
392 static int mtk_iommu_add_device(struct device *dev)
393 {
394 struct iommu_group *group;
395
396 if (!dev->archdata.iommu) /* Not a iommu client device */
397 return -ENODEV;
398
399 group = iommu_group_get_for_dev(dev);
400 if (IS_ERR(group))
401 return PTR_ERR(group);
402
403 iommu_group_put(group);
404 return 0;
405 }
406
407 static void mtk_iommu_remove_device(struct device *dev)
408 {
409 struct mtk_iommu_client_priv *head, *cur, *next;
410
411 head = dev->archdata.iommu;
412 if (!head)
413 return;
414
415 list_for_each_entry_safe(cur, next, &head->client, client) {
416 list_del(&cur->client);
417 kfree(cur);
418 }
419 kfree(head);
420 dev->archdata.iommu = NULL;
421
422 iommu_group_remove_device(dev);
423 }
424
425 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
426 {
427 struct mtk_iommu_data *data;
428 struct mtk_iommu_client_priv *priv;
429
430 priv = dev->archdata.iommu;
431 if (!priv)
432 return ERR_PTR(-ENODEV);
433
434 /* All the client devices are in the same m4u iommu-group */
435 data = dev_get_drvdata(priv->m4udev);
436 if (!data->m4u_group) {
437 data->m4u_group = iommu_group_alloc();
438 if (IS_ERR(data->m4u_group))
439 dev_err(dev, "Failed to allocate M4U IOMMU group\n");
440 }
441 return data->m4u_group;
442 }
443
444 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
445 {
446 struct mtk_iommu_client_priv *head, *priv, *next;
447 struct platform_device *m4updev;
448
449 if (args->args_count != 1) {
450 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
451 args->args_count);
452 return -EINVAL;
453 }
454
455 if (!dev->archdata.iommu) {
456 /* Get the m4u device */
457 m4updev = of_find_device_by_node(args->np);
458 of_node_put(args->np);
459 if (WARN_ON(!m4updev))
460 return -EINVAL;
461
462 head = kzalloc(sizeof(*head), GFP_KERNEL);
463 if (!head)
464 return -ENOMEM;
465
466 dev->archdata.iommu = head;
467 INIT_LIST_HEAD(&head->client);
468 head->m4udev = &m4updev->dev;
469 } else {
470 head = dev->archdata.iommu;
471 }
472
473 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
474 if (!priv)
475 goto err_free_mem;
476
477 priv->mtk_m4u_id = args->args[0];
478 list_add_tail(&priv->client, &head->client);
479
480 return 0;
481
482 err_free_mem:
483 list_for_each_entry_safe(priv, next, &head->client, client)
484 kfree(priv);
485 kfree(head);
486 dev->archdata.iommu = NULL;
487 return -ENOMEM;
488 }
489
490 static struct iommu_ops mtk_iommu_ops = {
491 .domain_alloc = mtk_iommu_domain_alloc,
492 .domain_free = mtk_iommu_domain_free,
493 .attach_dev = mtk_iommu_attach_device,
494 .detach_dev = mtk_iommu_detach_device,
495 .map = mtk_iommu_map,
496 .unmap = mtk_iommu_unmap,
497 .map_sg = default_iommu_map_sg,
498 .iova_to_phys = mtk_iommu_iova_to_phys,
499 .add_device = mtk_iommu_add_device,
500 .remove_device = mtk_iommu_remove_device,
501 .device_group = mtk_iommu_device_group,
502 .of_xlate = mtk_iommu_of_xlate,
503 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
504 };
505
506 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
507 {
508 u32 regval;
509 int ret;
510
511 ret = clk_prepare_enable(data->bclk);
512 if (ret) {
513 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
514 return ret;
515 }
516
517 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
518 F_MMU_TF_PROTECT_SEL(2);
519 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
520
521 regval = F_L2_MULIT_HIT_EN |
522 F_TABLE_WALK_FAULT_INT_EN |
523 F_PREETCH_FIFO_OVERFLOW_INT_EN |
524 F_MISS_FIFO_OVERFLOW_INT_EN |
525 F_PREFETCH_FIFO_ERR_INT_EN |
526 F_MISS_FIFO_ERR_INT_EN;
527 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
528
529 regval = F_INT_TRANSLATION_FAULT |
530 F_INT_MAIN_MULTI_HIT_FAULT |
531 F_INT_INVALID_PA_FAULT |
532 F_INT_ENTRY_REPLACEMENT_FAULT |
533 F_INT_TLB_MISS_FAULT |
534 F_INT_MISS_TRANSACTION_FIFO_FAULT |
535 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
536 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
537
538 writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
539 data->base + REG_MMU_IVRP_PADDR);
540
541 writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
542 writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
543
544 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
545 dev_name(data->dev), (void *)data)) {
546 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
547 clk_disable_unprepare(data->bclk);
548 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
549 return -ENODEV;
550 }
551
552 return 0;
553 }
554
555 static int compare_of(struct device *dev, void *data)
556 {
557 return dev->of_node == data;
558 }
559
560 static int mtk_iommu_bind(struct device *dev)
561 {
562 struct mtk_iommu_data *data = dev_get_drvdata(dev);
563
564 return component_bind_all(dev, &data->smi_imu);
565 }
566
567 static void mtk_iommu_unbind(struct device *dev)
568 {
569 struct mtk_iommu_data *data = dev_get_drvdata(dev);
570
571 component_unbind_all(dev, &data->smi_imu);
572 }
573
574 static const struct component_master_ops mtk_iommu_com_ops = {
575 .bind = mtk_iommu_bind,
576 .unbind = mtk_iommu_unbind,
577 };
578
579 static int mtk_iommu_probe(struct platform_device *pdev)
580 {
581 struct mtk_iommu_data *data;
582 struct device *dev = &pdev->dev;
583 struct resource *res;
584 struct component_match *match = NULL;
585 void *protect;
586 int i, larb_nr, ret;
587
588 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
589 if (!data)
590 return -ENOMEM;
591 data->dev = dev;
592
593 /* Protect memory. HW will access here while translation fault.*/
594 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
595 if (!protect)
596 return -ENOMEM;
597 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
598
599 /* Whether the current dram is over 4GB */
600 data->enable_4GB = !!(max_pfn > (0xffffffffUL >> PAGE_SHIFT));
601
602 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
603 data->base = devm_ioremap_resource(dev, res);
604 if (IS_ERR(data->base))
605 return PTR_ERR(data->base);
606
607 data->irq = platform_get_irq(pdev, 0);
608 if (data->irq < 0)
609 return data->irq;
610
611 data->bclk = devm_clk_get(dev, "bclk");
612 if (IS_ERR(data->bclk))
613 return PTR_ERR(data->bclk);
614
615 larb_nr = of_count_phandle_with_args(dev->of_node,
616 "mediatek,larbs", NULL);
617 if (larb_nr < 0)
618 return larb_nr;
619 data->smi_imu.larb_nr = larb_nr;
620
621 for (i = 0; i < larb_nr; i++) {
622 struct device_node *larbnode;
623 struct platform_device *plarbdev;
624
625 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
626 if (!larbnode)
627 return -EINVAL;
628
629 if (!of_device_is_available(larbnode))
630 continue;
631
632 plarbdev = of_find_device_by_node(larbnode);
633 of_node_put(larbnode);
634 if (!plarbdev) {
635 plarbdev = of_platform_device_create(
636 larbnode, NULL,
637 platform_bus_type.dev_root);
638 if (!plarbdev)
639 return -EPROBE_DEFER;
640 }
641 data->smi_imu.larb_imu[i].dev = &plarbdev->dev;
642
643 component_match_add(dev, &match, compare_of, larbnode);
644 }
645
646 platform_set_drvdata(pdev, data);
647
648 ret = mtk_iommu_hw_init(data);
649 if (ret)
650 return ret;
651
652 if (!iommu_present(&platform_bus_type))
653 bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
654
655 return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
656 }
657
658 static int mtk_iommu_remove(struct platform_device *pdev)
659 {
660 struct mtk_iommu_data *data = platform_get_drvdata(pdev);
661
662 if (iommu_present(&platform_bus_type))
663 bus_set_iommu(&platform_bus_type, NULL);
664
665 free_io_pgtable_ops(data->m4u_dom->iop);
666 clk_disable_unprepare(data->bclk);
667 devm_free_irq(&pdev->dev, data->irq, data);
668 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
669 return 0;
670 }
671
672 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
673 {
674 struct mtk_iommu_data *data = dev_get_drvdata(dev);
675 struct mtk_iommu_suspend_reg *reg = &data->reg;
676 void __iomem *base = data->base;
677
678 reg->standard_axi_mode = readl_relaxed(base +
679 REG_MMU_STANDARD_AXI_MODE);
680 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
681 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
682 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
683 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
684 return 0;
685 }
686
687 static int __maybe_unused mtk_iommu_resume(struct device *dev)
688 {
689 struct mtk_iommu_data *data = dev_get_drvdata(dev);
690 struct mtk_iommu_suspend_reg *reg = &data->reg;
691 void __iomem *base = data->base;
692
693 writel_relaxed(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
694 base + REG_MMU_PT_BASE_ADDR);
695 writel_relaxed(reg->standard_axi_mode,
696 base + REG_MMU_STANDARD_AXI_MODE);
697 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
698 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
699 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
700 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
701 writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
702 base + REG_MMU_IVRP_PADDR);
703 return 0;
704 }
705
706 const struct dev_pm_ops mtk_iommu_pm_ops = {
707 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
708 };
709
710 static const struct of_device_id mtk_iommu_of_ids[] = {
711 { .compatible = "mediatek,mt8173-m4u", },
712 {}
713 };
714
715 static struct platform_driver mtk_iommu_driver = {
716 .probe = mtk_iommu_probe,
717 .remove = mtk_iommu_remove,
718 .driver = {
719 .name = "mtk-iommu",
720 .of_match_table = mtk_iommu_of_ids,
721 .pm = &mtk_iommu_pm_ops,
722 }
723 };
724
725 static int mtk_iommu_init_fn(struct device_node *np)
726 {
727 int ret;
728 struct platform_device *pdev;
729
730 pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
731 if (!pdev)
732 return -ENOMEM;
733
734 ret = platform_driver_register(&mtk_iommu_driver);
735 if (ret) {
736 pr_err("%s: Failed to register driver\n", __func__);
737 return ret;
738 }
739
740 of_iommu_set_ops(np, &mtk_iommu_ops);
741 return 0;
742 }
743
744 IOMMU_OF_DECLARE(mtkm4u, "mediatek,mt8173-m4u", mtk_iommu_init_fn);
Linux with added FPC-III support