arch/c6x/include/asm/cache.h

   1 /*
   2  *  Port on Texas Instruments TMS320C6x architecture
   3  *
   4  *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
   5  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 as
   9  *  published by the Free Software Foundation.
  10  */
  11 #ifndef _ASM_C6X_CACHE_H
  12 #define _ASM_C6X_CACHE_H
  13
  14 #include <linux/irqflags.h>
  15 #include <linux/init.h>
  16
  17 /*
  18  * Cache line size
  19  */
  20 #define L1D_CACHE_SHIFT   6
  21 #define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)
  22
  23 #define L1P_CACHE_SHIFT   5
  24 #define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)
  25
  26 #define L2_CACHE_SHIFT    7
  27 #define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)
  28
  29 /*
  30  * L2 used as cache
  31  */
  32 #define L2MODE_SIZE       L2MODE_256K_CACHE
  33
  34 /*
  35  * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
  36  * the L2 line size
  37  */
  38 #define L1_CACHE_SHIFT        L2_CACHE_SHIFT
  39 #define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
  40
  41 #define L2_CACHE_ALIGN_LOW(x) \
  42         (((x) & ~(L2_CACHE_BYTES - 1)))
  43 #define L2_CACHE_ALIGN_UP(x) \
  44         (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
  45 #define L2_CACHE_ALIGN_CNT(x) \
  46         (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
  47
  48 #define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
  49 #define ARCH_SLAB_MINALIGN      L1_CACHE_BYTES
  50
  51 /*
  52  * This is the granularity of hardware cacheability control.
  53  */
  54 #define CACHEABILITY_ALIGN      0x01000000
  55
  56 /*
  57  * Align a physical address to MAR regions
  58  */
  59 #define CACHE_REGION_START(v) \
  60         (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
  61 #define CACHE_REGION_END(v) \
  62         (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
  63
  64 extern void __init c6x_cache_init(void);
  65
  66 extern void enable_caching(unsigned long start, unsigned long end);
  67 extern void disable_caching(unsigned long start, unsigned long end);
  68
  69 extern void L1_cache_off(void);
  70 extern void L1_cache_on(void);
  71
  72 extern void L1P_cache_global_invalidate(void);
  73 extern void L1D_cache_global_invalidate(void);
  74 extern void L1D_cache_global_writeback(void);
  75 extern void L1D_cache_global_writeback_invalidate(void);
  76 extern void L2_cache_set_mode(unsigned int mode);
  77 extern void L2_cache_global_writeback_invalidate(void);
  78 extern void L2_cache_global_writeback(void);
  79
  80 extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
  81 extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
  82 extern void L1D_cache_block_writeback_invalidate(unsigned int start,
  83                                                  unsigned int end);
  84 extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
  85 extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
  86 extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
  87 extern void L2_cache_block_writeback_invalidate(unsigned int start,
  88                                                 unsigned int end);
  89 extern void L2_cache_block_invalidate_nowait(unsigned int start,
  90                                              unsigned int end);
  91 extern void L2_cache_block_writeback_nowait(unsigned int start,
  92                                             unsigned int end);
  93
  94 extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
  95                                                        unsigned int end);
  96
  97 #endif /* _ASM_C6X_CACHE_H */