1 /* Wrapper for DMA channel allocator that starts clocks etc */
3 #include <linux/kernel.h>
4 #include <linux/spinlock.h>
6 #include <hwregs/reg_map.h>
7 #include <hwregs/reg_rdwr.h>
8 #include <hwregs/marb_defs.h>
9 #include <hwregs/clkgen_defs.h>
10 #include <hwregs/strmux_defs.h>
11 #include <linux/errno.h>
14 static char used_dma_channels
[MAX_DMA_CHANNELS
];
15 static const char *used_dma_channels_users
[MAX_DMA_CHANNELS
];
17 static DEFINE_SPINLOCK(dma_lock
);
19 int crisv32_request_dma(unsigned int dmanr
, const char *device_id
,
20 unsigned options
, unsigned int bandwidth
, enum dma_owner owner
)
23 reg_clkgen_rw_clk_ctrl clk_ctrl
;
24 reg_strmux_rw_cfg strmux_cfg
;
26 if (crisv32_arbiter_allocate_bandwidth(dmanr
,
27 options
& DMA_INT_MEM
? INT_REGION
: EXT_REGION
,
31 spin_lock_irqsave(&dma_lock
, flags
);
33 if (used_dma_channels
[dmanr
]) {
34 spin_unlock_irqrestore(&dma_lock
, flags
);
35 if (options
& DMA_VERBOSE_ON_ERROR
)
36 printk(KERN_ERR
"Failed to request DMA %i for %s, "
37 "already allocated by %s\n",
40 used_dma_channels_users
[dmanr
]);
42 if (options
& DMA_PANIC_ON_ERROR
)
43 panic("request_dma error!");
44 spin_unlock_irqrestore(&dma_lock
, flags
);
47 clk_ctrl
= REG_RD(clkgen
, regi_clkgen
, rw_clk_ctrl
);
48 strmux_cfg
= REG_RD(strmux
, regi_strmux
, rw_cfg
);
53 clk_ctrl
.dma0_1_eth
= 1;
57 clk_ctrl
.dma2_3_strcop
= 1;
61 clk_ctrl
.dma4_5_iop
= 1;
65 clk_ctrl
.sser_ser_dma6_7
= 1;
71 #if MAX_DMA_CHANNELS-1 != 11
75 spin_unlock_irqrestore(&dma_lock
, flags
);
76 if (options
& DMA_VERBOSE_ON_ERROR
)
77 printk(KERN_ERR
"Failed to request DMA %i for %s, "
79 dmanr
, device_id
, MAX_DMA_CHANNELS
-1);
81 if (options
& DMA_PANIC_ON_ERROR
)
82 panic("request_dma error!");
89 strmux_cfg
.dma0
= regk_strmux_eth
;
91 strmux_cfg
.dma1
= regk_strmux_eth
;
93 panic("Invalid DMA channel for eth\n");
97 strmux_cfg
.dma0
= regk_strmux_ser0
;
99 strmux_cfg
.dma1
= regk_strmux_ser0
;
101 panic("Invalid DMA channel for ser0\n");
105 strmux_cfg
.dma2
= regk_strmux_ser3
;
107 strmux_cfg
.dma3
= regk_strmux_ser3
;
109 panic("Invalid DMA channel for ser3\n");
113 strmux_cfg
.dma2
= regk_strmux_strcop
;
115 strmux_cfg
.dma3
= regk_strmux_strcop
;
117 panic("Invalid DMA channel for strp\n");
121 strmux_cfg
.dma4
= regk_strmux_ser1
;
123 strmux_cfg
.dma5
= regk_strmux_ser1
;
125 panic("Invalid DMA channel for ser1\n");
129 strmux_cfg
.dma4
= regk_strmux_iop
;
131 strmux_cfg
.dma5
= regk_strmux_iop
;
133 panic("Invalid DMA channel for iop\n");
137 strmux_cfg
.dma6
= regk_strmux_ser2
;
139 strmux_cfg
.dma7
= regk_strmux_ser2
;
141 panic("Invalid DMA channel for ser2\n");
145 strmux_cfg
.dma6
= regk_strmux_sser
;
147 strmux_cfg
.dma7
= regk_strmux_sser
;
149 panic("Invalid DMA channel for sser\n");
153 strmux_cfg
.dma9
= regk_strmux_ser4
;
155 panic("Invalid DMA channel for ser4\n");
159 strmux_cfg
.dma9
= regk_strmux_jpeg
;
161 panic("Invalid DMA channel for JPEG\n");
165 strmux_cfg
.dma11
= regk_strmux_h264
;
167 panic("Invalid DMA channel for H264\n");
171 used_dma_channels
[dmanr
] = 1;
172 used_dma_channels_users
[dmanr
] = device_id
;
173 REG_WR(clkgen
, regi_clkgen
, rw_clk_ctrl
, clk_ctrl
);
174 REG_WR(strmux
, regi_strmux
, rw_cfg
, strmux_cfg
);
175 spin_unlock_irqrestore(&dma_lock
, flags
);
179 void crisv32_free_dma(unsigned int dmanr
)
181 spin_lock(&dma_lock
);
182 used_dma_channels
[dmanr
] = 0;
183 spin_unlock(&dma_lock
);