2 * linux/arch/parisc/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
11 * "A Kernel Model for Precision Timekeeping" by Dave Mills
13 #include <linux/errno.h>
14 #include <linux/module.h>
15 #include <linux/rtc.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/param.h>
19 #include <linux/string.h>
21 #include <linux/interrupt.h>
22 #include <linux/time.h>
23 #include <linux/init.h>
24 #include <linux/smp.h>
25 #include <linux/profile.h>
26 #include <linux/clocksource.h>
27 #include <linux/platform_device.h>
28 #include <linux/ftrace.h>
30 #include <asm/uaccess.h>
34 #include <asm/param.h>
38 #include <linux/timex.h>
40 static unsigned long clocktick __read_mostly
; /* timer cycles per tick */
44 * The processor-internal cycle counter (Control Register 16) is used as time
45 * source for the sched_clock() function. This register is 64bit wide on a
46 * 64-bit kernel and 32bit on a 32-bit kernel. Since sched_clock() always
47 * requires a 64bit counter we emulate on the 32-bit kernel the higher 32bits
48 * with a per-cpu variable which we increase every time the counter
49 * wraps-around (which happens every ~4 secounds).
51 static DEFINE_PER_CPU(unsigned long, cr16_high_32_bits
);
55 * We keep time on PA-RISC Linux by using the Interval Timer which is
56 * a pair of registers; one is read-only and one is write-only; both
57 * accessed through CR16. The read-only register is 32 or 64 bits wide,
58 * and increments by 1 every CPU clock tick. The architecture only
59 * guarantees us a rate between 0.5 and 2, but all implementations use a
60 * rate of 1. The write-only register is 32-bits wide. When the lowest
61 * 32 bits of the read-only register compare equal to the write-only
62 * register, it raises a maskable external interrupt. Each processor has
63 * an Interval Timer of its own and they are not synchronised.
65 * We want to generate an interrupt every 1/HZ seconds. So we program
66 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
67 * is programmed with the intended time of the next tick. We can be
68 * held off for an arbitrarily long period of time by interrupts being
69 * disabled, so we may miss one or more ticks.
71 irqreturn_t __irq_entry
timer_interrupt(int irq
, void *dev_id
)
73 unsigned long now
, now2
;
74 unsigned long next_tick
;
75 unsigned long cycles_elapsed
, ticks_elapsed
= 1;
76 unsigned long cycles_remainder
;
77 unsigned int cpu
= smp_processor_id();
78 struct cpuinfo_parisc
*cpuinfo
= &per_cpu(cpu_data
, cpu
);
80 /* gcc can optimize for "read-only" case with a local clocktick */
81 unsigned long cpt
= clocktick
;
83 profile_tick(CPU_PROFILING
);
85 /* Initialize next_tick to the expected tick time. */
86 next_tick
= cpuinfo
->it_value
;
88 /* Get current cycle counter (Control Register 16). */
91 cycles_elapsed
= now
- next_tick
;
93 if ((cycles_elapsed
>> 6) < cpt
) {
94 /* use "cheap" math (add/subtract) instead
95 * of the more expensive div/mul method
97 cycles_remainder
= cycles_elapsed
;
98 while (cycles_remainder
> cpt
) {
99 cycles_remainder
-= cpt
;
103 /* TODO: Reduce this to one fdiv op */
104 cycles_remainder
= cycles_elapsed
% cpt
;
105 ticks_elapsed
+= cycles_elapsed
/ cpt
;
108 /* convert from "division remainder" to "remainder of clock tick" */
109 cycles_remainder
= cpt
- cycles_remainder
;
111 /* Determine when (in CR16 cycles) next IT interrupt will fire.
112 * We want IT to fire modulo clocktick even if we miss/skip some.
113 * But those interrupts don't in fact get delivered that regularly.
115 next_tick
= now
+ cycles_remainder
;
117 cpuinfo
->it_value
= next_tick
;
119 /* Program the IT when to deliver the next interrupt.
120 * Only bottom 32-bits of next_tick are writable in CR16!
122 mtctl(next_tick
, 16);
124 #if !defined(CONFIG_64BIT)
125 /* check for overflow on a 32bit kernel (every ~4 seconds). */
126 if (unlikely(next_tick
< now
))
127 this_cpu_inc(cr16_high_32_bits
);
130 /* Skip one clocktick on purpose if we missed next_tick.
131 * The new CR16 must be "later" than current CR16 otherwise
132 * itimer would not fire until CR16 wrapped - e.g 4 seconds
133 * later on a 1Ghz processor. We'll account for the missed
134 * tick on the next timer interrupt.
136 * "next_tick - now" will always give the difference regardless
137 * if one or the other wrapped. If "now" is "bigger" we'll end up
138 * with a very large unsigned number.
141 if (next_tick
- now2
> cpt
)
142 mtctl(next_tick
+cpt
, 16);
146 * GGG: DEBUG code for how many cycles programming CR16 used.
148 if (unlikely(now2
- now
> 0x3000)) /* 12K cycles */
149 printk (KERN_CRIT
"timer_interrupt(CPU %d): SLOW! 0x%lx cycles!"
151 " next/now %lX/%lX\n",
152 cpu
, now2
- now
, cycles_elapsed
, cycles_remainder
,
156 /* Can we differentiate between "early CR16" (aka Scenario 1) and
157 * "long delay" (aka Scenario 3)? I don't think so.
159 * Timer_interrupt will be delivered at least a few hundred cycles
160 * after the IT fires. But it's arbitrary how much time passes
161 * before we call it "late". I've picked one second.
163 * It's important NO printk's are between reading CR16 and
164 * setting up the next value. May introduce huge variance.
166 if (unlikely(ticks_elapsed
> HZ
)) {
167 /* Scenario 3: very long delay? bad in any case */
168 printk (KERN_CRIT
"timer_interrupt(CPU %d): delayed!"
169 " cycles %lX rem %lX "
170 " next/now %lX/%lX\n",
172 cycles_elapsed
, cycles_remainder
,
176 /* Done mucking with unreliable delivery of interrupts.
177 * Go do system house keeping.
180 if (!--cpuinfo
->prof_counter
) {
181 cpuinfo
->prof_counter
= cpuinfo
->prof_multiplier
;
182 update_process_times(user_mode(get_irq_regs()));
186 xtime_update(ticks_elapsed
);
192 unsigned long profile_pc(struct pt_regs
*regs
)
194 unsigned long pc
= instruction_pointer(regs
);
196 if (regs
->gr
[0] & PSW_N
)
200 if (in_lock_functions(pc
))
206 EXPORT_SYMBOL(profile_pc
);
209 /* clock source code */
211 static cycle_t
read_cr16(struct clocksource
*cs
)
216 static struct clocksource clocksource_cr16
= {
220 .mask
= CLOCKSOURCE_MASK(BITS_PER_LONG
),
221 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
224 void __init
start_cpu_itimer(void)
226 unsigned int cpu
= smp_processor_id();
227 unsigned long next_tick
= mfctl(16) + clocktick
;
229 #if defined(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK) && defined(CONFIG_64BIT)
230 /* With multiple 64bit CPUs online, the cr16's are not syncronized. */
232 clear_sched_clock_stable();
235 mtctl(next_tick
, 16); /* kick off Interval Timer (CR16) */
237 per_cpu(cpu_data
, cpu
).it_value
= next_tick
;
240 #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
241 static int rtc_generic_get_time(struct device
*dev
, struct rtc_time
*tm
)
243 struct pdc_tod tod_data
;
245 memset(tm
, 0, sizeof(*tm
));
246 if (pdc_tod_read(&tod_data
) < 0)
249 /* we treat tod_sec as unsigned, so this can work until year 2106 */
250 rtc_time64_to_tm(tod_data
.tod_sec
, tm
);
251 return rtc_valid_tm(tm
);
254 static int rtc_generic_set_time(struct device
*dev
, struct rtc_time
*tm
)
256 time64_t secs
= rtc_tm_to_time64(tm
);
258 if (pdc_tod_set(secs
, 0) < 0)
264 static const struct rtc_class_ops rtc_generic_ops
= {
265 .read_time
= rtc_generic_get_time
,
266 .set_time
= rtc_generic_set_time
,
269 static int __init
rtc_init(void)
271 struct platform_device
*pdev
;
273 pdev
= platform_device_register_data(NULL
, "rtc-generic", -1,
275 sizeof(rtc_generic_ops
));
277 return PTR_ERR_OR_ZERO(pdev
);
279 device_initcall(rtc_init
);
282 void read_persistent_clock(struct timespec
*ts
)
284 static struct pdc_tod tod_data
;
285 if (pdc_tod_read(&tod_data
) == 0) {
286 ts
->tv_sec
= tod_data
.tod_sec
;
287 ts
->tv_nsec
= tod_data
.tod_usec
* 1000;
289 printk(KERN_ERR
"Error reading tod clock\n");
297 * sched_clock() framework
300 static u32 cyc2ns_mul __read_mostly
;
301 static u32 cyc2ns_shift __read_mostly
;
303 u64
sched_clock(void)
307 /* Get current cycle counter (Control Register 16). */
311 now
= mfctl(16) + (((u64
) this_cpu_read(cr16_high_32_bits
)) << 32);
314 /* return the value in ns (cycles_2_ns) */
315 return mul_u64_u32_shr(now
, cyc2ns_mul
, cyc2ns_shift
);
320 * timer interrupt and sched_clock() initialization
323 void __init
time_init(void)
325 unsigned long current_cr16_khz
;
327 current_cr16_khz
= PAGE0
->mem_10msec
/10; /* kHz */
328 clocktick
= (100 * PAGE0
->mem_10msec
) / HZ
;
330 /* calculate mult/shift values for cr16 */
331 clocks_calc_mult_shift(&cyc2ns_mul
, &cyc2ns_shift
, current_cr16_khz
,
334 start_cpu_itimer(); /* get CPU 0 started */
336 /* register at clocksource framework */
337 clocksource_register_khz(&clocksource_cr16
, current_cr16_khz
);