2 * BPF Jit compiler for s390.
4 * Minimum build requirements:
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
12 * Copyright IBM Corp. 2012,2015
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <linux/bpf.h>
25 #include <asm/cacheflush.h>
29 int bpf_jit_enable __read_mostly
;
32 u32 seen
; /* Flags to remember seen eBPF instructions */
33 u32 seen_reg
[16]; /* Array to remember which registers are used */
34 u32
*addrs
; /* Array with relative instruction addresses */
35 u8
*prg_buf
; /* Start of program */
36 int size
; /* Size of program and literal pool */
37 int size_prg
; /* Size of program */
38 int prg
; /* Current position in program */
39 int lit_start
; /* Start of literal pool */
40 int lit
; /* Current position in literal pool */
41 int base_ip
; /* Base address for literal pool */
42 int ret0_ip
; /* Address of return 0 */
43 int exit_ip
; /* Address of exit */
44 int tail_call_start
; /* Tail call start offset */
45 int labels
[1]; /* Labels for local jumps */
48 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
50 #define SEEN_SKB 1 /* skb access */
51 #define SEEN_MEM 2 /* use mem[] for temporary storage */
52 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
53 #define SEEN_LITERAL 8 /* code uses literals */
54 #define SEEN_FUNC 16 /* calls C functions */
55 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
56 #define SEEN_SKB_CHANGE 64 /* code changes skb data */
57 #define SEEN_REG_AX 128 /* code uses constant blinding */
58 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
63 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
64 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
65 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */
66 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */
67 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */
68 #define REG_0 REG_W0 /* Register 0 */
69 #define REG_1 REG_W1 /* Register 1 */
70 #define REG_2 BPF_REG_1 /* Register 2 */
71 #define REG_14 BPF_REG_0 /* Register 14 */
74 * Mapping of BPF registers to s390 registers
76 static const int reg2hex
[] = {
79 /* Function parameters */
85 /* Call saved registers */
90 /* BPF stack pointer */
92 /* Register for blinding (shared with REG_SKB_DATA) */
94 /* SKB data pointer */
96 /* Work registers for s390x backend */
103 static inline u32
reg(u32 dst_reg
, u32 src_reg
)
105 return reg2hex
[dst_reg
] << 4 | reg2hex
[src_reg
];
108 static inline u32
reg_high(u32 reg
)
110 return reg2hex
[reg
] << 4;
113 static inline void reg_set_seen(struct bpf_jit
*jit
, u32 b1
)
115 u32 r1
= reg2hex
[b1
];
117 if (!jit
->seen_reg
[r1
] && r1
>= 6 && r1
<= 15)
118 jit
->seen_reg
[r1
] = 1;
121 #define REG_SET_SEEN(b1) \
123 reg_set_seen(jit, b1); \
126 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
129 * EMIT macros for code generation
135 *(u16 *) (jit->prg_buf + jit->prg) = op; \
139 #define EMIT2(op, b1, b2) \
141 _EMIT2(op | reg(b1, b2)); \
149 *(u32 *) (jit->prg_buf + jit->prg) = op; \
153 #define EMIT4(op, b1, b2) \
155 _EMIT4(op | reg(b1, b2)); \
160 #define EMIT4_RRF(op, b1, b2, b3) \
162 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
168 #define _EMIT4_DISP(op, disp) \
170 unsigned int __disp = (disp) & 0xfff; \
171 _EMIT4(op | __disp); \
174 #define EMIT4_DISP(op, b1, b2, disp) \
176 _EMIT4_DISP(op | reg_high(b1) << 16 | \
177 reg_high(b2) << 8, disp); \
182 #define EMIT4_IMM(op, b1, imm) \
184 unsigned int __imm = (imm) & 0xffff; \
185 _EMIT4(op | reg_high(b1) << 16 | __imm); \
189 #define EMIT4_PCREL(op, pcrel) \
191 long __pcrel = ((pcrel) >> 1) & 0xffff; \
192 _EMIT4(op | __pcrel); \
195 #define _EMIT6(op1, op2) \
197 if (jit->prg_buf) { \
198 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
199 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
204 #define _EMIT6_DISP(op1, op2, disp) \
206 unsigned int __disp = (disp) & 0xfff; \
207 _EMIT6(op1 | __disp, op2); \
210 #define _EMIT6_DISP_LH(op1, op2, disp) \
212 u32 _disp = (u32) disp; \
213 unsigned int __disp_h = _disp & 0xff000; \
214 unsigned int __disp_l = _disp & 0x00fff; \
215 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
218 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
220 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
221 reg_high(b3) << 8, op2, disp); \
227 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
229 int rel = (jit->labels[label] - jit->prg) >> 1; \
230 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
236 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
238 int rel = (jit->labels[label] - jit->prg) >> 1; \
239 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
240 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
242 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
245 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
247 /* Branch instruction needs 6 bytes */ \
248 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
249 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
254 #define _EMIT6_IMM(op, imm) \
256 unsigned int __imm = (imm); \
257 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
260 #define EMIT6_IMM(op, b1, imm) \
262 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
266 #define EMIT_CONST_U32(val) \
269 ret = jit->lit - jit->base_ip; \
270 jit->seen |= SEEN_LITERAL; \
272 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
277 #define EMIT_CONST_U64(val) \
280 ret = jit->lit - jit->base_ip; \
281 jit->seen |= SEEN_LITERAL; \
283 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
288 #define EMIT_ZERO(b1) \
290 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
291 EMIT4(0xb9160000, b1, b1); \
296 * Fill whole space with illegal instructions
298 static void jit_fill_hole(void *area
, unsigned int size
)
300 memset(area
, 0, size
);
304 * Save registers from "rs" (register start) to "re" (register end) on stack
306 static void save_regs(struct bpf_jit
*jit
, u32 rs
, u32 re
)
308 u32 off
= STK_OFF_R6
+ (rs
- 6) * 8;
311 /* stg %rs,off(%r15) */
312 _EMIT6(0xe300f000 | rs
<< 20 | off
, 0x0024);
314 /* stmg %rs,%re,off(%r15) */
315 _EMIT6_DISP(0xeb00f000 | rs
<< 20 | re
<< 16, 0x0024, off
);
319 * Restore registers from "rs" (register start) to "re" (register end) on stack
321 static void restore_regs(struct bpf_jit
*jit
, u32 rs
, u32 re
)
323 u32 off
= STK_OFF_R6
+ (rs
- 6) * 8;
325 if (jit
->seen
& SEEN_STACK
)
329 /* lg %rs,off(%r15) */
330 _EMIT6(0xe300f000 | rs
<< 20 | off
, 0x0004);
332 /* lmg %rs,%re,off(%r15) */
333 _EMIT6_DISP(0xeb00f000 | rs
<< 20 | re
<< 16, 0x0004, off
);
337 * Return first seen register (from start)
339 static int get_start(struct bpf_jit
*jit
, int start
)
343 for (i
= start
; i
<= 15; i
++) {
344 if (jit
->seen_reg
[i
])
351 * Return last seen register (from start) (gap >= 2)
353 static int get_end(struct bpf_jit
*jit
, int start
)
357 for (i
= start
; i
< 15; i
++) {
358 if (!jit
->seen_reg
[i
] && !jit
->seen_reg
[i
+ 1])
361 return jit
->seen_reg
[15] ? 15 : 14;
365 #define REGS_RESTORE 0
367 * Save and restore clobbered registers (6-15) on stack.
368 * We save/restore registers in chunks with gap >= 2 registers.
370 static void save_restore_regs(struct bpf_jit
*jit
, int op
)
376 rs
= get_start(jit
, re
);
379 re
= get_end(jit
, rs
+ 1);
381 save_regs(jit
, rs
, re
);
383 restore_regs(jit
, rs
, re
);
389 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
390 * we store the SKB header length on the stack and the SKB data
391 * pointer in REG_SKB_DATA if BPF_REG_AX is not used.
393 static void emit_load_skb_data_hlen(struct bpf_jit
*jit
)
395 /* Header length: llgf %w1,<len>(%b1) */
396 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1
, REG_0
, BPF_REG_1
,
397 offsetof(struct sk_buff
, len
));
398 /* s %w1,<data_len>(%b1) */
399 EMIT4_DISP(0x5b000000, REG_W1
, BPF_REG_1
,
400 offsetof(struct sk_buff
, data_len
));
401 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
402 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1
, REG_0
, REG_15
, STK_OFF_HLEN
);
403 if (!(jit
->seen
& SEEN_REG_AX
))
404 /* lg %skb_data,data_off(%b1) */
405 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA
, REG_0
,
406 BPF_REG_1
, offsetof(struct sk_buff
, data
));
410 * Emit function prologue
412 * Save registers and create stack frame if necessary.
413 * See stack frame layout desription in "bpf_jit.h"!
415 static void bpf_jit_prologue(struct bpf_jit
*jit
)
417 if (jit
->seen
& SEEN_TAIL_CALL
) {
418 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
419 _EMIT6(0xd703f000 | STK_OFF_TCCNT
, 0xf000 | STK_OFF_TCCNT
);
421 /* j tail_call_start: NOP if no tail calls are used */
422 EMIT4_PCREL(0xa7f40000, 6);
425 /* Tail calls have to skip above initialization */
426 jit
->tail_call_start
= jit
->prg
;
428 save_restore_regs(jit
, REGS_SAVE
);
429 /* Setup literal pool */
430 if (jit
->seen
& SEEN_LITERAL
) {
432 EMIT2(0x0d00, REG_L
, REG_0
);
433 jit
->base_ip
= jit
->prg
;
435 /* Setup stack and backchain */
436 if (jit
->seen
& SEEN_STACK
) {
437 if (jit
->seen
& SEEN_FUNC
)
438 /* lgr %w1,%r15 (backchain) */
439 EMIT4(0xb9040000, REG_W1
, REG_15
);
440 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
441 EMIT4_DISP(0x41000000, BPF_REG_FP
, REG_15
, STK_160_UNUSED
);
442 /* aghi %r15,-STK_OFF */
443 EMIT4_IMM(0xa70b0000, REG_15
, -STK_OFF
);
444 if (jit
->seen
& SEEN_FUNC
)
445 /* stg %w1,152(%r15) (backchain) */
446 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1
, REG_0
,
449 if (jit
->seen
& SEEN_SKB
)
450 emit_load_skb_data_hlen(jit
);
451 if (jit
->seen
& SEEN_SKB_CHANGE
)
452 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
453 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1
, REG_0
, REG_15
,
460 static void bpf_jit_epilogue(struct bpf_jit
*jit
)
463 if (jit
->seen
& SEEN_RET0
) {
464 jit
->ret0_ip
= jit
->prg
;
466 EMIT4_IMM(0xa7090000, BPF_REG_0
, 0);
468 jit
->exit_ip
= jit
->prg
;
469 /* Load exit code: lgr %r2,%b0 */
470 EMIT4(0xb9040000, REG_2
, BPF_REG_0
);
471 /* Restore registers */
472 save_restore_regs(jit
, REGS_RESTORE
);
478 * Compile one eBPF instruction into s390x code
480 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
481 * stack space for the large switch statement.
483 static noinline
int bpf_jit_insn(struct bpf_jit
*jit
, struct bpf_prog
*fp
, int i
)
485 struct bpf_insn
*insn
= &fp
->insnsi
[i
];
486 int jmp_off
, last
, insn_count
= 1;
487 unsigned int func_addr
, mask
;
488 u32 dst_reg
= insn
->dst_reg
;
489 u32 src_reg
= insn
->src_reg
;
490 u32
*addrs
= jit
->addrs
;
494 if (dst_reg
== BPF_REG_AX
|| src_reg
== BPF_REG_AX
)
495 jit
->seen
|= SEEN_REG_AX
;
496 switch (insn
->code
) {
500 case BPF_ALU
| BPF_MOV
| BPF_X
: /* dst = (u32) src */
501 /* llgfr %dst,%src */
502 EMIT4(0xb9160000, dst_reg
, src_reg
);
504 case BPF_ALU64
| BPF_MOV
| BPF_X
: /* dst = src */
506 EMIT4(0xb9040000, dst_reg
, src_reg
);
508 case BPF_ALU
| BPF_MOV
| BPF_K
: /* dst = (u32) imm */
510 EMIT6_IMM(0xc00f0000, dst_reg
, imm
);
512 case BPF_ALU64
| BPF_MOV
| BPF_K
: /* dst = imm */
514 EMIT6_IMM(0xc0010000, dst_reg
, imm
);
519 case BPF_LD
| BPF_IMM
| BPF_DW
: /* dst = (u64) imm */
521 /* 16 byte instruction that uses two 'struct bpf_insn' */
524 imm64
= (u64
)(u32
) insn
[0].imm
| ((u64
)(u32
) insn
[1].imm
) << 32;
525 /* lg %dst,<d(imm)>(%l) */
526 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg
, REG_0
, REG_L
,
527 EMIT_CONST_U64(imm64
));
534 case BPF_ALU
| BPF_ADD
| BPF_X
: /* dst = (u32) dst + (u32) src */
536 EMIT2(0x1a00, dst_reg
, src_reg
);
539 case BPF_ALU64
| BPF_ADD
| BPF_X
: /* dst = dst + src */
541 EMIT4(0xb9080000, dst_reg
, src_reg
);
543 case BPF_ALU
| BPF_ADD
| BPF_K
: /* dst = (u32) dst + (u32) imm */
547 EMIT6_IMM(0xc20b0000, dst_reg
, imm
);
550 case BPF_ALU64
| BPF_ADD
| BPF_K
: /* dst = dst + imm */
554 EMIT6_IMM(0xc2080000, dst_reg
, imm
);
559 case BPF_ALU
| BPF_SUB
| BPF_X
: /* dst = (u32) dst - (u32) src */
561 EMIT2(0x1b00, dst_reg
, src_reg
);
564 case BPF_ALU64
| BPF_SUB
| BPF_X
: /* dst = dst - src */
566 EMIT4(0xb9090000, dst_reg
, src_reg
);
568 case BPF_ALU
| BPF_SUB
| BPF_K
: /* dst = (u32) dst - (u32) imm */
572 EMIT6_IMM(0xc20b0000, dst_reg
, -imm
);
575 case BPF_ALU64
| BPF_SUB
| BPF_K
: /* dst = dst - imm */
579 EMIT6_IMM(0xc2080000, dst_reg
, -imm
);
584 case BPF_ALU
| BPF_MUL
| BPF_X
: /* dst = (u32) dst * (u32) src */
586 EMIT4(0xb2520000, dst_reg
, src_reg
);
589 case BPF_ALU64
| BPF_MUL
| BPF_X
: /* dst = dst * src */
591 EMIT4(0xb90c0000, dst_reg
, src_reg
);
593 case BPF_ALU
| BPF_MUL
| BPF_K
: /* dst = (u32) dst * (u32) imm */
597 EMIT6_IMM(0xc2010000, dst_reg
, imm
);
600 case BPF_ALU64
| BPF_MUL
| BPF_K
: /* dst = dst * imm */
604 EMIT6_IMM(0xc2000000, dst_reg
, imm
);
609 case BPF_ALU
| BPF_DIV
| BPF_X
: /* dst = (u32) dst / (u32) src */
610 case BPF_ALU
| BPF_MOD
| BPF_X
: /* dst = (u32) dst % (u32) src */
612 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
614 jit
->seen
|= SEEN_RET0
;
615 /* ltr %src,%src (if src == 0 goto fail) */
616 EMIT2(0x1200, src_reg
, src_reg
);
618 EMIT4_PCREL(0xa7840000, jit
->ret0_ip
- jit
->prg
);
620 EMIT4_IMM(0xa7080000, REG_W0
, 0);
622 EMIT2(0x1800, REG_W1
, dst_reg
);
624 EMIT4(0xb9970000, REG_W0
, src_reg
);
626 EMIT4(0xb9160000, dst_reg
, rc_reg
);
629 case BPF_ALU64
| BPF_DIV
| BPF_X
: /* dst = dst / src */
630 case BPF_ALU64
| BPF_MOD
| BPF_X
: /* dst = dst % src */
632 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
634 jit
->seen
|= SEEN_RET0
;
635 /* ltgr %src,%src (if src == 0 goto fail) */
636 EMIT4(0xb9020000, src_reg
, src_reg
);
638 EMIT4_PCREL(0xa7840000, jit
->ret0_ip
- jit
->prg
);
640 EMIT4_IMM(0xa7090000, REG_W0
, 0);
642 EMIT4(0xb9040000, REG_W1
, dst_reg
);
644 EMIT4(0xb9870000, REG_W0
, src_reg
);
646 EMIT4(0xb9040000, dst_reg
, rc_reg
);
649 case BPF_ALU
| BPF_DIV
| BPF_K
: /* dst = (u32) dst / (u32) imm */
650 case BPF_ALU
| BPF_MOD
| BPF_K
: /* dst = (u32) dst % (u32) imm */
652 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
655 if (BPF_OP(insn
->code
) == BPF_MOD
)
657 EMIT4_IMM(0xa7090000, dst_reg
, 0);
661 EMIT4_IMM(0xa7080000, REG_W0
, 0);
663 EMIT2(0x1800, REG_W1
, dst_reg
);
664 /* dl %w0,<d(imm)>(%l) */
665 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0
, REG_0
, REG_L
,
666 EMIT_CONST_U32(imm
));
668 EMIT4(0xb9160000, dst_reg
, rc_reg
);
671 case BPF_ALU64
| BPF_DIV
| BPF_K
: /* dst = dst / imm */
672 case BPF_ALU64
| BPF_MOD
| BPF_K
: /* dst = dst % imm */
674 int rc_reg
= BPF_OP(insn
->code
) == BPF_DIV
? REG_W1
: REG_W0
;
677 if (BPF_OP(insn
->code
) == BPF_MOD
)
679 EMIT4_IMM(0xa7090000, dst_reg
, 0);
683 EMIT4_IMM(0xa7090000, REG_W0
, 0);
685 EMIT4(0xb9040000, REG_W1
, dst_reg
);
686 /* dlg %w0,<d(imm)>(%l) */
687 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0
, REG_0
, REG_L
,
688 EMIT_CONST_U64(imm
));
690 EMIT4(0xb9040000, dst_reg
, rc_reg
);
696 case BPF_ALU
| BPF_AND
| BPF_X
: /* dst = (u32) dst & (u32) src */
698 EMIT2(0x1400, dst_reg
, src_reg
);
701 case BPF_ALU64
| BPF_AND
| BPF_X
: /* dst = dst & src */
703 EMIT4(0xb9800000, dst_reg
, src_reg
);
705 case BPF_ALU
| BPF_AND
| BPF_K
: /* dst = (u32) dst & (u32) imm */
707 EMIT6_IMM(0xc00b0000, dst_reg
, imm
);
710 case BPF_ALU64
| BPF_AND
| BPF_K
: /* dst = dst & imm */
711 /* ng %dst,<d(imm)>(%l) */
712 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg
, REG_0
, REG_L
,
713 EMIT_CONST_U64(imm
));
718 case BPF_ALU
| BPF_OR
| BPF_X
: /* dst = (u32) dst | (u32) src */
720 EMIT2(0x1600, dst_reg
, src_reg
);
723 case BPF_ALU64
| BPF_OR
| BPF_X
: /* dst = dst | src */
725 EMIT4(0xb9810000, dst_reg
, src_reg
);
727 case BPF_ALU
| BPF_OR
| BPF_K
: /* dst = (u32) dst | (u32) imm */
729 EMIT6_IMM(0xc00d0000, dst_reg
, imm
);
732 case BPF_ALU64
| BPF_OR
| BPF_K
: /* dst = dst | imm */
733 /* og %dst,<d(imm)>(%l) */
734 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg
, REG_0
, REG_L
,
735 EMIT_CONST_U64(imm
));
740 case BPF_ALU
| BPF_XOR
| BPF_X
: /* dst = (u32) dst ^ (u32) src */
742 EMIT2(0x1700, dst_reg
, src_reg
);
745 case BPF_ALU64
| BPF_XOR
| BPF_X
: /* dst = dst ^ src */
747 EMIT4(0xb9820000, dst_reg
, src_reg
);
749 case BPF_ALU
| BPF_XOR
| BPF_K
: /* dst = (u32) dst ^ (u32) imm */
753 EMIT6_IMM(0xc0070000, dst_reg
, imm
);
756 case BPF_ALU64
| BPF_XOR
| BPF_K
: /* dst = dst ^ imm */
757 /* xg %dst,<d(imm)>(%l) */
758 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg
, REG_0
, REG_L
,
759 EMIT_CONST_U64(imm
));
764 case BPF_ALU
| BPF_LSH
| BPF_X
: /* dst = (u32) dst << (u32) src */
765 /* sll %dst,0(%src) */
766 EMIT4_DISP(0x89000000, dst_reg
, src_reg
, 0);
769 case BPF_ALU64
| BPF_LSH
| BPF_X
: /* dst = dst << src */
770 /* sllg %dst,%dst,0(%src) */
771 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg
, dst_reg
, src_reg
, 0);
773 case BPF_ALU
| BPF_LSH
| BPF_K
: /* dst = (u32) dst << (u32) imm */
776 /* sll %dst,imm(%r0) */
777 EMIT4_DISP(0x89000000, dst_reg
, REG_0
, imm
);
780 case BPF_ALU64
| BPF_LSH
| BPF_K
: /* dst = dst << imm */
783 /* sllg %dst,%dst,imm(%r0) */
784 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg
, dst_reg
, REG_0
, imm
);
789 case BPF_ALU
| BPF_RSH
| BPF_X
: /* dst = (u32) dst >> (u32) src */
790 /* srl %dst,0(%src) */
791 EMIT4_DISP(0x88000000, dst_reg
, src_reg
, 0);
794 case BPF_ALU64
| BPF_RSH
| BPF_X
: /* dst = dst >> src */
795 /* srlg %dst,%dst,0(%src) */
796 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg
, dst_reg
, src_reg
, 0);
798 case BPF_ALU
| BPF_RSH
| BPF_K
: /* dst = (u32) dst >> (u32) imm */
801 /* srl %dst,imm(%r0) */
802 EMIT4_DISP(0x88000000, dst_reg
, REG_0
, imm
);
805 case BPF_ALU64
| BPF_RSH
| BPF_K
: /* dst = dst >> imm */
808 /* srlg %dst,%dst,imm(%r0) */
809 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg
, dst_reg
, REG_0
, imm
);
814 case BPF_ALU64
| BPF_ARSH
| BPF_X
: /* ((s64) dst) >>= src */
815 /* srag %dst,%dst,0(%src) */
816 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg
, dst_reg
, src_reg
, 0);
818 case BPF_ALU64
| BPF_ARSH
| BPF_K
: /* ((s64) dst) >>= imm */
821 /* srag %dst,%dst,imm(%r0) */
822 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg
, dst_reg
, REG_0
, imm
);
827 case BPF_ALU
| BPF_NEG
: /* dst = (u32) -dst */
829 EMIT2(0x1300, dst_reg
, dst_reg
);
832 case BPF_ALU64
| BPF_NEG
: /* dst = -dst */
834 EMIT4(0xb9130000, dst_reg
, dst_reg
);
839 case BPF_ALU
| BPF_END
| BPF_FROM_BE
:
840 /* s390 is big endian, therefore only clear high order bytes */
842 case 16: /* dst = (u16) cpu_to_be16(dst) */
843 /* llghr %dst,%dst */
844 EMIT4(0xb9850000, dst_reg
, dst_reg
);
846 case 32: /* dst = (u32) cpu_to_be32(dst) */
847 /* llgfr %dst,%dst */
848 EMIT4(0xb9160000, dst_reg
, dst_reg
);
850 case 64: /* dst = (u64) cpu_to_be64(dst) */
854 case BPF_ALU
| BPF_END
| BPF_FROM_LE
:
856 case 16: /* dst = (u16) cpu_to_le16(dst) */
858 EMIT4(0xb91f0000, dst_reg
, dst_reg
);
859 /* srl %dst,16(%r0) */
860 EMIT4_DISP(0x88000000, dst_reg
, REG_0
, 16);
861 /* llghr %dst,%dst */
862 EMIT4(0xb9850000, dst_reg
, dst_reg
);
864 case 32: /* dst = (u32) cpu_to_le32(dst) */
866 EMIT4(0xb91f0000, dst_reg
, dst_reg
);
867 /* llgfr %dst,%dst */
868 EMIT4(0xb9160000, dst_reg
, dst_reg
);
870 case 64: /* dst = (u64) cpu_to_le64(dst) */
871 /* lrvgr %dst,%dst */
872 EMIT4(0xb90f0000, dst_reg
, dst_reg
);
879 case BPF_STX
| BPF_MEM
| BPF_B
: /* *(u8 *)(dst + off) = src_reg */
880 /* stcy %src,off(%dst) */
881 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg
, dst_reg
, REG_0
, off
);
882 jit
->seen
|= SEEN_MEM
;
884 case BPF_STX
| BPF_MEM
| BPF_H
: /* (u16 *)(dst + off) = src */
885 /* sthy %src,off(%dst) */
886 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg
, dst_reg
, REG_0
, off
);
887 jit
->seen
|= SEEN_MEM
;
889 case BPF_STX
| BPF_MEM
| BPF_W
: /* *(u32 *)(dst + off) = src */
890 /* sty %src,off(%dst) */
891 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg
, dst_reg
, REG_0
, off
);
892 jit
->seen
|= SEEN_MEM
;
894 case BPF_STX
| BPF_MEM
| BPF_DW
: /* (u64 *)(dst + off) = src */
895 /* stg %src,off(%dst) */
896 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg
, dst_reg
, REG_0
, off
);
897 jit
->seen
|= SEEN_MEM
;
899 case BPF_ST
| BPF_MEM
| BPF_B
: /* *(u8 *)(dst + off) = imm */
901 EMIT4_IMM(0xa7080000, REG_W0
, (u8
) imm
);
902 /* stcy %w0,off(dst) */
903 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0
, dst_reg
, REG_0
, off
);
904 jit
->seen
|= SEEN_MEM
;
906 case BPF_ST
| BPF_MEM
| BPF_H
: /* (u16 *)(dst + off) = imm */
908 EMIT4_IMM(0xa7080000, REG_W0
, (u16
) imm
);
909 /* sthy %w0,off(dst) */
910 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0
, dst_reg
, REG_0
, off
);
911 jit
->seen
|= SEEN_MEM
;
913 case BPF_ST
| BPF_MEM
| BPF_W
: /* *(u32 *)(dst + off) = imm */
915 EMIT6_IMM(0xc00f0000, REG_W0
, (u32
) imm
);
916 /* sty %w0,off(%dst) */
917 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0
, dst_reg
, REG_0
, off
);
918 jit
->seen
|= SEEN_MEM
;
920 case BPF_ST
| BPF_MEM
| BPF_DW
: /* *(u64 *)(dst + off) = imm */
922 EMIT6_IMM(0xc0010000, REG_W0
, imm
);
923 /* stg %w0,off(%dst) */
924 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0
, dst_reg
, REG_0
, off
);
925 jit
->seen
|= SEEN_MEM
;
928 * BPF_STX XADD (atomic_add)
930 case BPF_STX
| BPF_XADD
| BPF_W
: /* *(u32 *)(dst + off) += src */
931 /* laal %w0,%src,off(%dst) */
932 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0
, src_reg
,
934 jit
->seen
|= SEEN_MEM
;
936 case BPF_STX
| BPF_XADD
| BPF_DW
: /* *(u64 *)(dst + off) += src */
937 /* laalg %w0,%src,off(%dst) */
938 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0
, src_reg
,
940 jit
->seen
|= SEEN_MEM
;
945 case BPF_LDX
| BPF_MEM
| BPF_B
: /* dst = *(u8 *)(ul) (src + off) */
946 /* llgc %dst,0(off,%src) */
947 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg
, src_reg
, REG_0
, off
);
948 jit
->seen
|= SEEN_MEM
;
950 case BPF_LDX
| BPF_MEM
| BPF_H
: /* dst = *(u16 *)(ul) (src + off) */
951 /* llgh %dst,0(off,%src) */
952 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg
, src_reg
, REG_0
, off
);
953 jit
->seen
|= SEEN_MEM
;
955 case BPF_LDX
| BPF_MEM
| BPF_W
: /* dst = *(u32 *)(ul) (src + off) */
956 /* llgf %dst,off(%src) */
957 jit
->seen
|= SEEN_MEM
;
958 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg
, src_reg
, REG_0
, off
);
960 case BPF_LDX
| BPF_MEM
| BPF_DW
: /* dst = *(u64 *)(ul) (src + off) */
961 /* lg %dst,0(off,%src) */
962 jit
->seen
|= SEEN_MEM
;
963 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg
, src_reg
, REG_0
, off
);
968 case BPF_JMP
| BPF_CALL
:
971 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
973 const u64 func
= (u64
)__bpf_call_base
+ imm
;
975 REG_SET_SEEN(BPF_REG_5
);
976 jit
->seen
|= SEEN_FUNC
;
977 /* lg %w1,<d(imm)>(%l) */
978 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1
, REG_0
, REG_L
,
979 EMIT_CONST_U64(func
));
981 EMIT2(0x0d00, REG_14
, REG_W1
);
982 /* lgr %b0,%r2: load return value into %b0 */
983 EMIT4(0xb9040000, BPF_REG_0
, REG_2
);
984 if (bpf_helper_changes_skb_data((void *)func
)) {
985 jit
->seen
|= SEEN_SKB_CHANGE
;
986 /* lg %b1,ST_OFF_SKBP(%r15) */
987 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1
, REG_0
,
988 REG_15
, STK_OFF_SKBP
);
989 emit_load_skb_data_hlen(jit
);
993 case BPF_JMP
| BPF_CALL
| BPF_X
:
997 * B2: pointer to bpf_array
998 * B3: index in bpf_array
1000 jit
->seen
|= SEEN_TAIL_CALL
;
1003 * if (index >= array->map.max_entries)
1007 /* llgf %w1,map.max_entries(%b2) */
1008 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1
, REG_0
, BPF_REG_2
,
1009 offsetof(struct bpf_array
, map
.max_entries
));
1010 /* clgrj %b3,%w1,0xa,label0: if %b3 >= %w1 goto out */
1011 EMIT6_PCREL_LABEL(0xec000000, 0x0065, BPF_REG_3
,
1015 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1019 if (jit
->seen
& SEEN_STACK
)
1020 off
= STK_OFF_TCCNT
+ STK_OFF
;
1022 off
= STK_OFF_TCCNT
;
1024 EMIT4_IMM(0xa7080000, REG_W0
, 1);
1025 /* laal %w1,%w0,off(%r15) */
1026 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1
, REG_W0
, REG_15
, off
);
1027 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1028 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1
,
1029 MAX_TAIL_CALL_CNT
, 0, 0x2);
1032 * prog = array->ptrs[index];
1037 /* sllg %r1,%b3,3: %r1 = index * 8 */
1038 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1
, BPF_REG_3
, REG_0
, 3);
1039 /* lg %r1,prog(%b2,%r1) */
1040 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1
, BPF_REG_2
,
1041 REG_1
, offsetof(struct bpf_array
, ptrs
));
1042 /* clgij %r1,0,0x8,label0 */
1043 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1
, 0, 0, 0x8);
1046 * Restore registers before calling function
1048 save_restore_regs(jit
, REGS_RESTORE
);
1051 * goto *(prog->bpf_func + tail_call_start);
1054 /* lg %r1,bpf_func(%r1) */
1055 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1
, REG_1
, REG_0
,
1056 offsetof(struct bpf_prog
, bpf_func
));
1057 /* bc 0xf,tail_call_start(%r1) */
1058 _EMIT4(0x47f01000 + jit
->tail_call_start
);
1060 jit
->labels
[0] = jit
->prg
;
1062 case BPF_JMP
| BPF_EXIT
: /* return b0 */
1063 last
= (i
== fp
->len
- 1) ? 1 : 0;
1064 if (last
&& !(jit
->seen
& SEEN_RET0
))
1067 EMIT4_PCREL(0xa7f40000, jit
->exit_ip
- jit
->prg
);
1070 * Branch relative (number of skipped instructions) to offset on
1073 * Condition code to mask mapping:
1075 * CC | Description | Mask
1076 * ------------------------------
1077 * 0 | Operands equal | 8
1078 * 1 | First operand low | 4
1079 * 2 | First operand high | 2
1082 * For s390x relative branches: ip = ip + off_bytes
1083 * For BPF relative branches: insn = insn + off_insns + 1
1085 * For example for s390x with offset 0 we jump to the branch
1086 * instruction itself (loop) and for BPF with offset 0 we
1087 * branch to the instruction behind the branch.
1089 case BPF_JMP
| BPF_JA
: /* if (true) */
1090 mask
= 0xf000; /* j */
1092 case BPF_JMP
| BPF_JSGT
| BPF_K
: /* ((s64) dst > (s64) imm) */
1093 mask
= 0x2000; /* jh */
1095 case BPF_JMP
| BPF_JSGE
| BPF_K
: /* ((s64) dst >= (s64) imm) */
1096 mask
= 0xa000; /* jhe */
1098 case BPF_JMP
| BPF_JGT
| BPF_K
: /* (dst_reg > imm) */
1099 mask
= 0x2000; /* jh */
1101 case BPF_JMP
| BPF_JGE
| BPF_K
: /* (dst_reg >= imm) */
1102 mask
= 0xa000; /* jhe */
1104 case BPF_JMP
| BPF_JNE
| BPF_K
: /* (dst_reg != imm) */
1105 mask
= 0x7000; /* jne */
1107 case BPF_JMP
| BPF_JEQ
| BPF_K
: /* (dst_reg == imm) */
1108 mask
= 0x8000; /* je */
1110 case BPF_JMP
| BPF_JSET
| BPF_K
: /* (dst_reg & imm) */
1111 mask
= 0x7000; /* jnz */
1112 /* lgfi %w1,imm (load sign extend imm) */
1113 EMIT6_IMM(0xc0010000, REG_W1
, imm
);
1115 EMIT4(0xb9800000, REG_W1
, dst_reg
);
1118 case BPF_JMP
| BPF_JSGT
| BPF_X
: /* ((s64) dst > (s64) src) */
1119 mask
= 0x2000; /* jh */
1121 case BPF_JMP
| BPF_JSGE
| BPF_X
: /* ((s64) dst >= (s64) src) */
1122 mask
= 0xa000; /* jhe */
1124 case BPF_JMP
| BPF_JGT
| BPF_X
: /* (dst > src) */
1125 mask
= 0x2000; /* jh */
1127 case BPF_JMP
| BPF_JGE
| BPF_X
: /* (dst >= src) */
1128 mask
= 0xa000; /* jhe */
1130 case BPF_JMP
| BPF_JNE
| BPF_X
: /* (dst != src) */
1131 mask
= 0x7000; /* jne */
1133 case BPF_JMP
| BPF_JEQ
| BPF_X
: /* (dst == src) */
1134 mask
= 0x8000; /* je */
1136 case BPF_JMP
| BPF_JSET
| BPF_X
: /* (dst & src) */
1137 mask
= 0x7000; /* jnz */
1138 /* ngrk %w1,%dst,%src */
1139 EMIT4_RRF(0xb9e40000, REG_W1
, dst_reg
, src_reg
);
1142 /* lgfi %w1,imm (load sign extend imm) */
1143 EMIT6_IMM(0xc0010000, REG_W1
, imm
);
1144 /* cgrj %dst,%w1,mask,off */
1145 EMIT6_PCREL(0xec000000, 0x0064, dst_reg
, REG_W1
, i
, off
, mask
);
1148 /* lgfi %w1,imm (load sign extend imm) */
1149 EMIT6_IMM(0xc0010000, REG_W1
, imm
);
1150 /* clgrj %dst,%w1,mask,off */
1151 EMIT6_PCREL(0xec000000, 0x0065, dst_reg
, REG_W1
, i
, off
, mask
);
1154 /* cgrj %dst,%src,mask,off */
1155 EMIT6_PCREL(0xec000000, 0x0064, dst_reg
, src_reg
, i
, off
, mask
);
1158 /* clgrj %dst,%src,mask,off */
1159 EMIT6_PCREL(0xec000000, 0x0065, dst_reg
, src_reg
, i
, off
, mask
);
1162 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1163 jmp_off
= addrs
[i
+ off
+ 1] - (addrs
[i
+ 1] - 4);
1164 EMIT4_PCREL(0xa7040000 | mask
<< 8, jmp_off
);
1169 case BPF_LD
| BPF_ABS
| BPF_B
: /* b0 = *(u8 *) (skb->data+imm) */
1170 case BPF_LD
| BPF_IND
| BPF_B
: /* b0 = *(u8 *) (skb->data+imm+src) */
1171 if ((BPF_MODE(insn
->code
) == BPF_ABS
) && (imm
>= 0))
1172 func_addr
= __pa(sk_load_byte_pos
);
1174 func_addr
= __pa(sk_load_byte
);
1176 case BPF_LD
| BPF_ABS
| BPF_H
: /* b0 = *(u16 *) (skb->data+imm) */
1177 case BPF_LD
| BPF_IND
| BPF_H
: /* b0 = *(u16 *) (skb->data+imm+src) */
1178 if ((BPF_MODE(insn
->code
) == BPF_ABS
) && (imm
>= 0))
1179 func_addr
= __pa(sk_load_half_pos
);
1181 func_addr
= __pa(sk_load_half
);
1183 case BPF_LD
| BPF_ABS
| BPF_W
: /* b0 = *(u32 *) (skb->data+imm) */
1184 case BPF_LD
| BPF_IND
| BPF_W
: /* b0 = *(u32 *) (skb->data+imm+src) */
1185 if ((BPF_MODE(insn
->code
) == BPF_ABS
) && (imm
>= 0))
1186 func_addr
= __pa(sk_load_word_pos
);
1188 func_addr
= __pa(sk_load_word
);
1191 jit
->seen
|= SEEN_SKB
| SEEN_RET0
| SEEN_FUNC
;
1192 REG_SET_SEEN(REG_14
); /* Return address of possible func call */
1196 * BPF_REG_6 (R7) : skb pointer
1197 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX)
1200 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1201 * BPF_REG_5 (R6) : return address
1204 * BPF_REG_0 (R14): data read from skb
1206 * Scratch registers (BPF_REG_1-5)
1209 /* Call function: llilf %w1,func_addr */
1210 EMIT6_IMM(0xc00f0000, REG_W1
, func_addr
);
1212 /* Offset: lgfi %b2,imm */
1213 EMIT6_IMM(0xc0010000, BPF_REG_2
, imm
);
1214 if (BPF_MODE(insn
->code
) == BPF_IND
)
1215 /* agfr %b2,%src (%src is s32 here) */
1216 EMIT4(0xb9180000, BPF_REG_2
, src_reg
);
1218 /* Reload REG_SKB_DATA if BPF_REG_AX is used */
1219 if (jit
->seen
& SEEN_REG_AX
)
1220 /* lg %skb_data,data_off(%b6) */
1221 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA
, REG_0
,
1222 BPF_REG_6
, offsetof(struct sk_buff
, data
));
1223 /* basr %b5,%w1 (%b5 is call saved) */
1224 EMIT2(0x0d00, BPF_REG_5
, REG_W1
);
1227 * Note: For fast access we jump directly after the
1228 * jnz instruction from bpf_jit.S
1231 EMIT4_PCREL(0xa7740000, jit
->ret0_ip
- jit
->prg
);
1233 default: /* too complex, give up */
1234 pr_err("Unknown opcode %02x\n", insn
->code
);
1241 * Compile eBPF program into s390x code
1243 static int bpf_jit_prog(struct bpf_jit
*jit
, struct bpf_prog
*fp
)
1247 jit
->lit
= jit
->lit_start
;
1250 bpf_jit_prologue(jit
);
1251 for (i
= 0; i
< fp
->len
; i
+= insn_count
) {
1252 insn_count
= bpf_jit_insn(jit
, fp
, i
);
1255 jit
->addrs
[i
+ 1] = jit
->prg
; /* Next instruction address */
1257 bpf_jit_epilogue(jit
);
1259 jit
->lit_start
= jit
->prg
;
1260 jit
->size
= jit
->lit
;
1261 jit
->size_prg
= jit
->prg
;
1266 * Classic BPF function stub. BPF programs will be converted into
1267 * eBPF and then bpf_int_jit_compile() will be called.
1269 void bpf_jit_compile(struct bpf_prog
*fp
)
1274 * Compile eBPF program "fp"
1276 struct bpf_prog
*bpf_int_jit_compile(struct bpf_prog
*fp
)
1278 struct bpf_prog
*tmp
, *orig_fp
= fp
;
1279 struct bpf_binary_header
*header
;
1280 bool tmp_blinded
= false;
1284 if (!bpf_jit_enable
)
1287 tmp
= bpf_jit_blind_constants(fp
);
1289 * If blinding was requested and we failed during blinding,
1290 * we must fall back to the interpreter.
1299 memset(&jit
, 0, sizeof(jit
));
1300 jit
.addrs
= kcalloc(fp
->len
+ 1, sizeof(*jit
.addrs
), GFP_KERNEL
);
1301 if (jit
.addrs
== NULL
) {
1306 * Three initial passes:
1307 * - 1/2: Determine clobbered registers
1308 * - 3: Calculate program size and addrs arrray
1310 for (pass
= 1; pass
<= 3; pass
++) {
1311 if (bpf_jit_prog(&jit
, fp
)) {
1317 * Final pass: Allocate and generate program
1319 if (jit
.size
>= BPF_SIZE_MAX
) {
1323 header
= bpf_jit_binary_alloc(jit
.size
, &jit
.prg_buf
, 2, jit_fill_hole
);
1328 if (bpf_jit_prog(&jit
, fp
)) {
1332 if (bpf_jit_enable
> 1) {
1333 bpf_jit_dump(fp
->len
, jit
.size
, pass
, jit
.prg_buf
);
1335 print_fn_code(jit
.prg_buf
, jit
.size_prg
);
1338 set_memory_ro((unsigned long)header
, header
->pages
);
1339 fp
->bpf_func
= (void *) jit
.prg_buf
;
1346 bpf_jit_prog_release_other(fp
, fp
== orig_fp
?
1354 void bpf_jit_free(struct bpf_prog
*fp
)
1356 unsigned long addr
= (unsigned long)fp
->bpf_func
& PAGE_MASK
;
1357 struct bpf_binary_header
*header
= (void *)addr
;
1362 set_memory_rw(addr
, header
->pages
);
1363 bpf_jit_binary_free(header
);
1366 bpf_prog_unlock_free(fp
);