arch/sh/kernel/cpu/sh2/probe.c

   1 /*
   2  * arch/sh/kernel/cpu/sh2/probe.c
   3  *
   4  * CPU Subtype Probing for SH-2.
   5  *
   6  * Copyright (C) 2002 Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/of_fdt.h>
  14 #include <linux/smp.h>
  15 #include <linux/io.h>
  16 #include <asm/processor.h>
  17 #include <asm/cache.h>
  18
  19 #if defined(CONFIG_CPU_J2)
  20 extern u32 __iomem *j2_ccr_base;
  21 static int __init scan_cache(unsigned long node, const char *uname,
  22                              int depth, void *data)
  23 {
  24         if (!of_flat_dt_is_compatible(node, "jcore,cache"))
  25                 return 0;
  26
  27         j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node);
  28
  29         return 1;
  30 }
  31 #endif
  32
  33 void __ref cpu_probe(void)
  34 {
  35 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
  36         boot_cpu_data.type                      = CPU_SH7619;
  37         boot_cpu_data.dcache.ways               = 4;
  38         boot_cpu_data.dcache.way_incr   = (1<<12);
  39         boot_cpu_data.dcache.sets               = 256;
  40         boot_cpu_data.dcache.entry_shift        = 4;
  41         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
  42         boot_cpu_data.dcache.flags              = 0;
  43 #endif
  44
  45 #if defined(CONFIG_CPU_J2)
  46         unsigned cpu = hard_smp_processor_id();
  47         if (cpu == 0) of_scan_flat_dt(scan_cache, NULL);
  48         if (j2_ccr_base) __raw_writel(0x80000303, j2_ccr_base + 4*cpu);
  49         if (cpu != 0) return;
  50         boot_cpu_data.type                      = CPU_J2;
  51
  52         /* These defaults are appropriate for the original/current
  53          * J2 cache. Once there is a proper framework for getting cache
  54          * info from device tree, we should switch to that. */
  55         boot_cpu_data.dcache.ways               = 1;
  56         boot_cpu_data.dcache.sets               = 256;
  57         boot_cpu_data.dcache.entry_shift        = 5;
  58         boot_cpu_data.dcache.linesz             = 32;
  59         boot_cpu_data.dcache.flags              = 0;
  60
  61         boot_cpu_data.flags |= CPU_HAS_CAS_L;
  62 #else
  63         /*
  64          * SH-2 doesn't have separate caches
  65          */
  66         boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
  67 #endif
  68         boot_cpu_data.icache = boot_cpu_data.dcache;
  69         boot_cpu_data.family = CPU_FAMILY_SH2;
  70 }