arch/sparc/include/asm/pgtsrmmu.h

   1 /*
   2  * pgtsrmmu.h:  SRMMU page table defines and code.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_PGTSRMMU_H
   8 #define _SPARC_PGTSRMMU_H
   9
  10 #include <asm/page.h>
  11
  12 #ifdef __ASSEMBLY__
  13 #include <asm/thread_info.h>    /* TI_UWINMASK for WINDOW_FLUSH */
  14 #endif
  15
  16 /* Number of contexts is implementation-dependent; 64k is the most we support */
  17 #define SRMMU_MAX_CONTEXTS      65536
  18
  19 /* PMD_SHIFT determines the size of the area a second-level page table entry can map */
  20 #define SRMMU_REAL_PMD_SHIFT            18
  21 #define SRMMU_REAL_PMD_SIZE             (1UL << SRMMU_REAL_PMD_SHIFT)
  22 #define SRMMU_REAL_PMD_MASK             (~(SRMMU_REAL_PMD_SIZE-1))
  23 #define SRMMU_REAL_PMD_ALIGN(__addr)    (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
  24
  25 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  26 #define SRMMU_PGDIR_SHIFT       24
  27 #define SRMMU_PGDIR_SIZE        (1UL << SRMMU_PGDIR_SHIFT)
  28 #define SRMMU_PGDIR_MASK        (~(SRMMU_PGDIR_SIZE-1))
  29 #define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
  30
  31 #define SRMMU_REAL_PTRS_PER_PTE 64
  32 #define SRMMU_REAL_PTRS_PER_PMD 64
  33 #define SRMMU_PTRS_PER_PGD      256
  34
  35 #define SRMMU_REAL_PTE_TABLE_SIZE       (SRMMU_REAL_PTRS_PER_PTE*4)
  36 #define SRMMU_PMD_TABLE_SIZE            (SRMMU_REAL_PTRS_PER_PMD*4)
  37 #define SRMMU_PGD_TABLE_SIZE            (SRMMU_PTRS_PER_PGD*4)
  38
  39 /*
  40  * To support pagetables in highmem, Linux introduces APIs which
  41  * return struct page* and generally manipulate page tables when
  42  * they are not mapped into kernel space. Our hardware page tables
  43  * are smaller than pages. We lump hardware tabes into big, page sized
  44  * software tables.
  45  *
  46  * PMD_SHIFT determines the size of the area a second-level page table entry
  47  * can map, and our pmd_t is 16 times larger than normal.  The values which
  48  * were once defined here are now generic for 4c and srmmu, so they're
  49  * found in pgtable.h.
  50  */
  51 #define SRMMU_PTRS_PER_PMD      4
  52
  53 /* Definition of the values in the ET field of PTD's and PTE's */
  54 #define SRMMU_ET_MASK         0x3
  55 #define SRMMU_ET_INVALID      0x0
  56 #define SRMMU_ET_PTD          0x1
  57 #define SRMMU_ET_PTE          0x2
  58 #define SRMMU_ET_REPTE        0x3 /* AIEEE, SuperSparc II reverse endian page! */
  59
  60 /* Physical page extraction from PTP's and PTE's. */
  61 #define SRMMU_CTX_PMASK    0xfffffff0
  62 #define SRMMU_PTD_PMASK    0xfffffff0
  63 #define SRMMU_PTE_PMASK    0xffffff00
  64
  65 /* The pte non-page bits.  Some notes:
  66  * 1) cache, dirty, valid, and ref are frobbable
  67  *    for both supervisor and user pages.
  68  * 2) exec and write will only give the desired effect
  69  *    on user pages
  70  * 3) use priv and priv_readonly for changing the
  71  *    characteristics of supervisor ptes
  72  */
  73 #define SRMMU_CACHE        0x80
  74 #define SRMMU_DIRTY        0x40
  75 #define SRMMU_REF          0x20
  76 #define SRMMU_NOREAD       0x10
  77 #define SRMMU_EXEC         0x08
  78 #define SRMMU_WRITE        0x04
  79 #define SRMMU_VALID        0x02 /* SRMMU_ET_PTE */
  80 #define SRMMU_PRIV         0x1c
  81 #define SRMMU_PRIV_RDONLY  0x18
  82
  83 #define SRMMU_CHG_MASK    (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
  84
  85 /* SRMMU swap entry encoding
  86  *
  87  * We use 5 bits for the type and 19 for the offset.  This gives us
  88  * 32 swapfiles of 4GB each.  Encoding looks like:
  89  *
  90  * oooooooooooooooooootttttRRRRRRRR
  91  * fedcba9876543210fedcba9876543210
  92  *
  93  * The bottom 7 bits are reserved for protection and status bits, especially
  94  * PRESENT.
  95  */
  96 #define SRMMU_SWP_TYPE_MASK     0x1f
  97 #define SRMMU_SWP_TYPE_SHIFT    7
  98 #define SRMMU_SWP_OFF_MASK      0xfffff
  99 #define SRMMU_SWP_OFF_SHIFT     (SRMMU_SWP_TYPE_SHIFT + 5)
 100
 101 /* Some day I will implement true fine grained access bits for
 102  * user pages because the SRMMU gives us the capabilities to
 103  * enforce all the protection levels that vma's can have.
 104  * XXX But for now...
 105  */
 106 #define SRMMU_PAGE_NONE    __pgprot(SRMMU_CACHE | \
 107                                     SRMMU_PRIV | SRMMU_REF)
 108 #define SRMMU_PAGE_SHARED  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
 109                                     SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
 110 #define SRMMU_PAGE_COPY    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
 111                                     SRMMU_EXEC | SRMMU_REF)
 112 #define SRMMU_PAGE_RDONLY  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
 113                                     SRMMU_EXEC | SRMMU_REF)
 114 #define SRMMU_PAGE_KERNEL  __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
 115                                     SRMMU_DIRTY | SRMMU_REF)
 116
 117 /* SRMMU Register addresses in ASI 0x4.  These are valid for all
 118  * current SRMMU implementations that exist.
 119  */
 120 #define SRMMU_CTRL_REG           0x00000000
 121 #define SRMMU_CTXTBL_PTR         0x00000100
 122 #define SRMMU_CTX_REG            0x00000200
 123 #define SRMMU_FAULT_STATUS       0x00000300
 124 #define SRMMU_FAULT_ADDR         0x00000400
 125
 126 #define WINDOW_FLUSH(tmp1, tmp2)                                        \
 127         mov     0, tmp1;                                                \
 128 98:     ld      [%g6 + TI_UWINMASK], tmp2;                              \
 129         orcc    %g0, tmp2, %g0;                                         \
 130         add     tmp1, 1, tmp1;                                          \
 131         bne     98b;                                                    \
 132          save   %sp, -64, %sp;                                          \
 133 99:     subcc   tmp1, 1, tmp1;                                          \
 134         bne     99b;                                                    \
 135          restore %g0, %g0, %g0;
 136
 137 #ifndef __ASSEMBLY__
 138 extern unsigned long last_valid_pfn;
 139
 140 /* This makes sense. Honest it does - Anton */
 141 /* XXX Yes but it's ugly as sin.  FIXME. -KMW */
 142 extern void *srmmu_nocache_pool;
 143 #define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
 144 #define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
 145 #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
 146
 147 /* Accessing the MMU control register. */
 148 unsigned int srmmu_get_mmureg(void);
 149 void srmmu_set_mmureg(unsigned long regval);
 150 void srmmu_set_ctable_ptr(unsigned long paddr);
 151 void srmmu_set_context(int context);
 152 int srmmu_get_context(void);
 153 unsigned int srmmu_get_fstatus(void);
 154 unsigned int srmmu_get_faddr(void);
 155
 156 /* This is guaranteed on all SRMMU's. */
 157 static inline void srmmu_flush_whole_tlb(void)
 158 {
 159         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 160                              "r" (0x400),        /* Flush entire TLB!! */
 161                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 162
 163 }
 164
 165 static inline int
 166 srmmu_get_pte (unsigned long addr)
 167 {
 168         register unsigned long entry;
 169
 170         __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
 171                                 "=r" (entry):
 172                                 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
 173         return entry;
 174 }
 175
 176 #endif /* !(__ASSEMBLY__) */
 177
 178 #endif /* !(_SPARC_PGTSRMMU_H) */