2 * rtrap.S: Preparing for return from trap on Sparc V9.
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
10 #include <asm/pstate.h>
11 #include <asm/ptrace.h>
12 #include <asm/spitfire.h>
14 #include <asm/visasm.h>
15 #include <asm/processor.h>
17 #ifdef CONFIG_CONTEXT_TRACKING
18 # define SCHEDULE_USER schedule_user
20 # define SCHEDULE_USER schedule
27 wrpr %g0, RTRAP_PSTATE, %pstate
28 ba,pt %xcc, __handle_preemption_continue
29 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
31 __handle_user_windows:
32 call fault_in_user_windows
33 wrpr %g0, RTRAP_PSTATE, %pstate
34 ba,pt %xcc, __handle_preemption_continue
35 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
39 andcc %l5, FPRS_FEF, %g0
40 sethi %hi(TSTATE_PEF), %o0
41 be,a,pn %icc, __handle_userfpu_continue
43 ba,a,pt %xcc, __handle_userfpu_continue
47 add %sp, PTREGS_OFF, %o0
50 wrpr %g0, RTRAP_PSTATE, %pstate
51 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
53 /* Signal delivery can modify pt_regs tstate, so we must
56 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
57 sethi %hi(0xf << 20), %l4
59 ba,pt %xcc, __handle_preemption_continue
62 /* When returning from a NMI (%pil==15) interrupt we want to
63 * avoid running softirqs, doing IRQ tracing, preempting, etc.
66 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
67 sethi %hi(0xf << 20), %l4
71 ba,pt %xcc, rtrap_no_irq_enable
73 /* Do not actually set the %pil here. We will do that
74 * below after we clear PSTATE_IE in the %pstate register.
75 * If we re-enable interrupts here, we can recurse down
76 * the hardirq stack potentially endlessly, causing a
81 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
84 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
87 sethi %hi(0xf << 20), %l4
91 #ifdef CONFIG_TRACE_IRQFLAGS
92 brnz,pn %l4, rtrap_no_irq_enable
94 call trace_hardirqs_on
96 /* Do not actually set the %pil here. We will do that
97 * below after we clear PSTATE_IE in the %pstate register.
98 * If we re-enable interrupts here, we can recurse down
99 * the hardirq stack potentially endlessly, causing a
102 * It is tempting to put this test and trace_hardirqs_on
103 * call at the 'rt_continue' label, but that will not work
104 * as that path hits unconditionally and we do not want to
105 * execute this in NMI return paths, for example.
109 andcc %l1, TSTATE_PRIV, %l3
110 bne,pn %icc, to_kernel
113 /* We must hold IRQs off and atomically test schedule+signal
114 * state, then hold them off all the way back to userspace.
115 * If we are returning to kernel, none of this matters. Note
116 * that we are disabling interrupts via PSTATE_IE, not using
119 * If we do not do this, there is a window where we would do
120 * the tests, later the signal/resched event arrives but we do
121 * not process it since we are still in kernel mode. It would
122 * take until the next local IRQ before the signal/resched
123 * event would be handled.
125 * This also means that if we have to deal with user
126 * windows, we have to redo all of these sched+signal checks
127 * with IRQs disabled.
129 to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
131 __handle_preemption_continue:
132 ldx [%g6 + TI_FLAGS], %l0
133 sethi %hi(_TIF_USER_WORK_MASK), %o0
134 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
136 sethi %hi(TSTATE_PEF), %o0
137 be,pt %xcc, user_nowork
139 andcc %l0, _TIF_NEED_RESCHED, %g0
140 bne,pn %xcc, __handle_preemption
141 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
142 bne,pn %xcc, __handle_signal
143 ldub [%g6 + TI_WSAVED], %o2
144 brnz,pn %o2, __handle_user_windows
146 sethi %hi(TSTATE_PEF), %o0
149 /* This fpdepth clear is necessary for non-syscall rtraps only */
151 bne,pn %xcc, __handle_userfpu
152 stb %g0, [%g6 + TI_FPDEPTH]
153 __handle_userfpu_continue:
155 rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
156 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
158 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
159 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
160 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
164 /* Must do this before thread reg is clobbered below. */
165 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
167 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
168 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
170 /* Normal globals are restored, go to trap globals. */
171 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
173 .section .sun4v_2insn_patch, "ax"
175 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
181 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
182 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
184 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
185 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
186 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
187 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
188 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
189 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
190 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
191 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
193 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
197 andn %l1, TSTATE_SYSCALL, %l1
198 wrpr %l1, %g0, %tstate
202 brnz,pn %l3, kern_rtt
203 mov PRIMARY_CONTEXT, %l7
205 661: ldxa [%l7 + %l7] ASI_DMMU, %l0
206 .section .sun4v_1insn_patch, "ax"
208 ldxa [%l7 + %l7] ASI_MMU, %l0
211 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
212 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
215 661: stxa %l0, [%l7] ASI_DMMU
216 .section .sun4v_1insn_patch, "ax"
218 stxa %l0, [%l7] ASI_MMU
221 sethi %hi(KERNBASE), %l7
227 wrpr %l2, %g0, %canrestore
228 wrpr %l1, %g0, %wstate
229 brnz,pt %l2, user_rtt_restore
230 wrpr %g0, %g0, %otherwin
232 ldx [%g6 + TI_FLAGS], %g3
233 wr %g0, ASI_AIUP, %asi
235 andcc %g3, _TIF_32BIT, %g0
237 bne,pt %xcc, user_rtt_fill_32bit
239 ba,a,pt %xcc, user_rtt_fill_64bit
241 user_rtt_fill_fixup_dax:
242 ba,pt %xcc, user_rtt_fill_fixup_common
245 user_rtt_fill_fixup_mna:
246 ba,pt %xcc, user_rtt_fill_fixup_common
250 ba,pt %xcc, user_rtt_fill_fixup_common
253 user_rtt_pre_restore:
259 rdpr %canrestore, %g1
260 wrpr %g1, 0x0, %cleanwin
264 kern_rtt: rdpr %canrestore, %g1
265 brz,pn %g1, kern_rtt_fill
268 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
273 #ifdef CONFIG_PREEMPT
274 ldsw [%g6 + TI_PRE_COUNT], %l5
275 brnz %l5, kern_fpucheck
276 ldx [%g6 + TI_FLAGS], %l5
277 andcc %l5, _TIF_NEED_RESCHED, %g0
278 be,pt %xcc, kern_fpucheck
281 bne,pn %xcc, kern_fpucheck
283 call preempt_schedule_irq
287 kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
288 brz,pt %l5, rt_continue
290 add %g6, TI_FPSAVED, %l6
291 ldub [%l6 + %o0], %l2
295 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
297 and %l2, FPRS_DL, %l6
298 andcc %l2, FPRS_FEF, %g0
303 wr %g1, FPRS_FEF, %fprs
305 add %g6, TI_XFSR, %o1
307 add %g6, TI_FPREGS, %o3
309 add %g6, TI_FPREGS+0x40, %o4
312 ldda [%o3 + %o2] ASI_BLK_P, %f0
313 ldda [%o4 + %o2] ASI_BLK_P, %f16
315 1: andcc %l2, FPRS_DU, %g0
320 ldda [%o3 + %o2] ASI_BLK_P, %f32
321 ldda [%o4 + %o2] ASI_BLK_P, %f48
323 ldx [%o1 + %o5], %fsr
324 2: stb %l5, [%g6 + TI_FPDEPTH]
325 ba,pt %xcc, rt_continue
327 5: wr %g0, FPRS_FEF, %fprs
330 add %g6, TI_FPREGS+0x80, %o3
331 add %g6, TI_FPREGS+0xc0, %o4
333 ldda [%o3 + %o2] ASI_BLK_P, %f32
334 ldda [%o4 + %o2] ASI_BLK_P, %f48
336 wr %g0, FPRS_DU, %fprs
337 ba,pt %xcc, rt_continue
338 stb %l5, [%g6 + TI_FPDEPTH]