2 * linux/arch/sparc64/kernel/setup.c
4 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/errno.h>
9 #include <linux/sched.h>
10 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/unistd.h>
14 #include <linux/ptrace.h>
16 #include <linux/user.h>
17 #include <linux/screen_info.h>
18 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/syscalls.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/inet.h>
27 #include <linux/console.h>
28 #include <linux/root_dev.h>
29 #include <linux/interrupt.h>
30 #include <linux/cpu.h>
31 #include <linux/initrd.h>
32 #include <linux/module.h>
33 #include <linux/start_kernel.h>
36 #include <asm/processor.h>
37 #include <asm/oplib.h>
39 #include <asm/pgtable.h>
40 #include <asm/idprom.h>
42 #include <asm/starfire.h>
43 #include <asm/mmu_context.h>
44 #include <asm/timer.h>
45 #include <asm/sections.h>
46 #include <asm/setup.h>
48 #include <asm/ns87303.h>
49 #include <asm/btext.h>
51 #include <asm/mdesc.h>
52 #include <asm/cacheflush.h>
55 #include <net/ipconfig.h>
61 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
62 * operations in asm/ns87303.h
64 DEFINE_SPINLOCK(ns87303_lock
);
65 EXPORT_SYMBOL(ns87303_lock
);
67 struct screen_info screen_info
= {
68 0, 0, /* orig-x, orig-y */
70 0, /* orig-video-page */
71 0, /* orig-video-mode */
72 128, /* orig-video-cols */
73 0, 0, 0, /* unused, ega_bx, unused */
74 54, /* orig-video-lines */
75 0, /* orig-video-isVGA */
76 16 /* orig-video-points */
80 prom_console_write(struct console
*con
, const char *s
, unsigned int n
)
85 /* Exported for mm/init.c:paging_init. */
86 unsigned long cmdline_memory_size
= 0;
88 static struct console prom_early_console
= {
90 .write
= prom_console_write
,
91 .flags
= CON_PRINTBUFFER
| CON_BOOT
| CON_ANYTIME
,
96 * Process kernel command line switches that are specific to the
97 * SPARC or that require special low-level processing.
99 static void __init
process_switch(char c
)
106 prom_printf("boot_flags_init: Halt!\n");
110 prom_early_console
.flags
&= ~CON_BOOT
;
113 /* Force UltraSPARC-III P-Cache on. */
114 if (tlb_type
!= cheetah
) {
115 printk("BOOT: Ignoring P-Cache force option.\n");
118 cheetah_pcache_forced_on
= 1;
119 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
120 cheetah_enable_pcache();
124 printk("Unknown boot switch (-%c)\n", c
);
129 static void __init
boot_flags_init(char *commands
)
132 /* Move to the start of the next "argument". */
133 while (*commands
&& *commands
== ' ')
136 /* Process any command switches, otherwise skip it. */
137 if (*commands
== '\0')
139 if (*commands
== '-') {
141 while (*commands
&& *commands
!= ' ')
142 process_switch(*commands
++);
145 if (!strncmp(commands
, "mem=", 4))
146 cmdline_memory_size
= memparse(commands
+ 4, &commands
);
148 while (*commands
&& *commands
!= ' ')
153 extern unsigned short root_flags
;
154 extern unsigned short root_dev
;
155 extern unsigned short ram_flags
;
156 #define RAMDISK_IMAGE_START_MASK 0x07FF
157 #define RAMDISK_PROMPT_FLAG 0x8000
158 #define RAMDISK_LOAD_FLAG 0x4000
160 extern int root_mountflags
;
162 char reboot_command
[COMMAND_LINE_SIZE
];
164 static struct pt_regs fake_swapper_regs
= { { 0, }, 0, 0, 0, 0 };
166 static void __init
per_cpu_patch(void)
168 struct cpuid_patch_entry
*p
;
172 if (tlb_type
== spitfire
&& !this_is_starfire
)
176 if (tlb_type
!= hypervisor
) {
177 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
178 is_jbus
= ((ver
>> 32UL) == __JALAPENO_ID
||
179 (ver
>> 32UL) == __SERRANO_ID
);
183 while (p
< &__cpuid_patch_end
) {
184 unsigned long addr
= p
->addr
;
189 insns
= &p
->starfire
[0];
194 insns
= &p
->cheetah_jbus
[0];
196 insns
= &p
->cheetah_safari
[0];
199 insns
= &p
->sun4v
[0];
202 prom_printf("Unknown cpu type, halting.\n");
206 *(unsigned int *) (addr
+ 0) = insns
[0];
208 __asm__
__volatile__("flush %0" : : "r" (addr
+ 0));
210 *(unsigned int *) (addr
+ 4) = insns
[1];
212 __asm__
__volatile__("flush %0" : : "r" (addr
+ 4));
214 *(unsigned int *) (addr
+ 8) = insns
[2];
216 __asm__
__volatile__("flush %0" : : "r" (addr
+ 8));
218 *(unsigned int *) (addr
+ 12) = insns
[3];
220 __asm__
__volatile__("flush %0" : : "r" (addr
+ 12));
226 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry
*start
,
227 struct sun4v_1insn_patch_entry
*end
)
229 while (start
< end
) {
230 unsigned long addr
= start
->addr
;
232 *(unsigned int *) (addr
+ 0) = start
->insn
;
234 __asm__
__volatile__("flush %0" : : "r" (addr
+ 0));
240 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry
*start
,
241 struct sun4v_2insn_patch_entry
*end
)
243 while (start
< end
) {
244 unsigned long addr
= start
->addr
;
246 *(unsigned int *) (addr
+ 0) = start
->insns
[0];
248 __asm__
__volatile__("flush %0" : : "r" (addr
+ 0));
250 *(unsigned int *) (addr
+ 4) = start
->insns
[1];
252 __asm__
__volatile__("flush %0" : : "r" (addr
+ 4));
258 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry
*start
,
259 struct sun4v_2insn_patch_entry
*end
)
261 while (start
< end
) {
262 unsigned long addr
= start
->addr
;
264 *(unsigned int *) (addr
+ 0) = start
->insns
[0];
266 __asm__
__volatile__("flush %0" : : "r" (addr
+ 0));
268 *(unsigned int *) (addr
+ 4) = start
->insns
[1];
270 __asm__
__volatile__("flush %0" : : "r" (addr
+ 4));
276 static void __init
sun4v_patch(void)
278 extern void sun4v_hvapi_init(void);
280 if (tlb_type
!= hypervisor
)
283 sun4v_patch_1insn_range(&__sun4v_1insn_patch
,
284 &__sun4v_1insn_patch_end
);
286 sun4v_patch_2insn_range(&__sun4v_2insn_patch
,
287 &__sun4v_2insn_patch_end
);
288 if (sun4v_chip_type
== SUN4V_CHIP_SPARC_M7
||
289 sun4v_chip_type
== SUN4V_CHIP_SPARC_SN
)
290 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch
,
291 &__sun_m7_2insn_patch_end
);
296 static void __init
popc_patch(void)
298 struct popc_3insn_patch_entry
*p3
;
299 struct popc_6insn_patch_entry
*p6
;
301 p3
= &__popc_3insn_patch
;
302 while (p3
< &__popc_3insn_patch_end
) {
303 unsigned long i
, addr
= p3
->addr
;
305 for (i
= 0; i
< 3; i
++) {
306 *(unsigned int *) (addr
+ (i
* 4)) = p3
->insns
[i
];
308 __asm__
__volatile__("flush %0"
309 : : "r" (addr
+ (i
* 4)));
315 p6
= &__popc_6insn_patch
;
316 while (p6
< &__popc_6insn_patch_end
) {
317 unsigned long i
, addr
= p6
->addr
;
319 for (i
= 0; i
< 6; i
++) {
320 *(unsigned int *) (addr
+ (i
* 4)) = p6
->insns
[i
];
322 __asm__
__volatile__("flush %0"
323 : : "r" (addr
+ (i
* 4)));
330 static void __init
pause_patch(void)
332 struct pause_patch_entry
*p
;
334 p
= &__pause_3insn_patch
;
335 while (p
< &__pause_3insn_patch_end
) {
336 unsigned long i
, addr
= p
->addr
;
338 for (i
= 0; i
< 3; i
++) {
339 *(unsigned int *) (addr
+ (i
* 4)) = p
->insns
[i
];
341 __asm__
__volatile__("flush %0"
342 : : "r" (addr
+ (i
* 4)));
349 void __init
start_early_boot(void)
357 cpu
= hard_smp_processor_id();
358 if (cpu
>= NR_CPUS
) {
359 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
363 current_thread_info()->cpu
= cpu
;
369 /* On Ultra, we support all of the v8 capabilities. */
370 unsigned long sparc64_elf_hwcap
= (HWCAP_SPARC_FLUSH
| HWCAP_SPARC_STBAR
|
371 HWCAP_SPARC_SWAP
| HWCAP_SPARC_MULDIV
|
373 EXPORT_SYMBOL(sparc64_elf_hwcap
);
375 static const char *hwcaps
[] = {
376 "flush", "stbar", "swap", "muldiv", "v9",
377 "ultra3", "blkinit", "n2",
379 /* These strings are as they appear in the machine description
380 * 'hwcap-list' property for cpu nodes.
382 "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
383 "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
384 "ima", "cspare", "pause", "cbcond", NULL
/*reserved for crypto */,
388 static const char *crypto_hwcaps
[] = {
389 "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
390 "sha512", "mpmul", "montmul", "montsqr", "crc32c",
393 void cpucap_info(struct seq_file
*m
)
395 unsigned long caps
= sparc64_elf_hwcap
;
398 seq_puts(m
, "cpucaps\t\t: ");
399 for (i
= 0; i
< ARRAY_SIZE(hwcaps
); i
++) {
400 unsigned long bit
= 1UL << i
;
401 if (hwcaps
[i
] && (caps
& bit
)) {
402 seq_printf(m
, "%s%s",
403 printed
? "," : "", hwcaps
[i
]);
407 if (caps
& HWCAP_SPARC_CRYPTO
) {
410 __asm__
__volatile__("rd %%asr26, %0" : "=r" (cfr
));
411 for (i
= 0; i
< ARRAY_SIZE(crypto_hwcaps
); i
++) {
412 unsigned long bit
= 1UL << i
;
414 seq_printf(m
, "%s%s",
415 printed
? "," : "", crypto_hwcaps
[i
]);
423 static void __init
report_one_hwcap(int *printed
, const char *name
)
426 printk(KERN_INFO
"CPU CAPS: [");
427 printk(KERN_CONT
"%s%s",
428 (*printed
) ? "," : "", name
);
429 if (++(*printed
) == 8) {
430 printk(KERN_CONT
"]\n");
435 static void __init
report_crypto_hwcaps(int *printed
)
440 __asm__
__volatile__("rd %%asr26, %0" : "=r" (cfr
));
442 for (i
= 0; i
< ARRAY_SIZE(crypto_hwcaps
); i
++) {
443 unsigned long bit
= 1UL << i
;
445 report_one_hwcap(printed
, crypto_hwcaps
[i
]);
449 static void __init
report_hwcaps(unsigned long caps
)
453 for (i
= 0; i
< ARRAY_SIZE(hwcaps
); i
++) {
454 unsigned long bit
= 1UL << i
;
455 if (hwcaps
[i
] && (caps
& bit
))
456 report_one_hwcap(&printed
, hwcaps
[i
]);
458 if (caps
& HWCAP_SPARC_CRYPTO
)
459 report_crypto_hwcaps(&printed
);
461 printk(KERN_CONT
"]\n");
464 static unsigned long __init
mdesc_cpu_hwcap_list(void)
466 struct mdesc_handle
*hp
;
467 unsigned long caps
= 0;
476 pn
= mdesc_node_by_name(hp
, MDESC_NODE_NULL
, "cpu");
477 if (pn
== MDESC_NODE_NULL
)
480 prop
= mdesc_get_property(hp
, pn
, "hwcap-list", &len
);
487 for (i
= 0; i
< ARRAY_SIZE(hwcaps
); i
++) {
488 unsigned long bit
= 1UL << i
;
490 if (hwcaps
[i
] && !strcmp(prop
, hwcaps
[i
])) {
495 for (i
= 0; i
< ARRAY_SIZE(crypto_hwcaps
); i
++) {
496 if (!strcmp(prop
, crypto_hwcaps
[i
]))
497 caps
|= HWCAP_SPARC_CRYPTO
;
500 plen
= strlen(prop
) + 1;
510 /* This yields a mask that user programs can use to figure out what
511 * instruction set this cpu supports.
513 static void __init
init_sparc64_elf_hwcap(void)
515 unsigned long cap
= sparc64_elf_hwcap
;
516 unsigned long mdesc_caps
;
518 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
519 cap
|= HWCAP_SPARC_ULTRA3
;
520 else if (tlb_type
== hypervisor
) {
521 if (sun4v_chip_type
== SUN4V_CHIP_NIAGARA1
||
522 sun4v_chip_type
== SUN4V_CHIP_NIAGARA2
||
523 sun4v_chip_type
== SUN4V_CHIP_NIAGARA3
||
524 sun4v_chip_type
== SUN4V_CHIP_NIAGARA4
||
525 sun4v_chip_type
== SUN4V_CHIP_NIAGARA5
||
526 sun4v_chip_type
== SUN4V_CHIP_SPARC_M6
||
527 sun4v_chip_type
== SUN4V_CHIP_SPARC_M7
||
528 sun4v_chip_type
== SUN4V_CHIP_SPARC_SN
||
529 sun4v_chip_type
== SUN4V_CHIP_SPARC64X
)
530 cap
|= HWCAP_SPARC_BLKINIT
;
531 if (sun4v_chip_type
== SUN4V_CHIP_NIAGARA2
||
532 sun4v_chip_type
== SUN4V_CHIP_NIAGARA3
||
533 sun4v_chip_type
== SUN4V_CHIP_NIAGARA4
||
534 sun4v_chip_type
== SUN4V_CHIP_NIAGARA5
||
535 sun4v_chip_type
== SUN4V_CHIP_SPARC_M6
||
536 sun4v_chip_type
== SUN4V_CHIP_SPARC_M7
||
537 sun4v_chip_type
== SUN4V_CHIP_SPARC_SN
||
538 sun4v_chip_type
== SUN4V_CHIP_SPARC64X
)
539 cap
|= HWCAP_SPARC_N2
;
542 cap
|= (AV_SPARC_MUL32
| AV_SPARC_DIV32
| AV_SPARC_V8PLUS
);
544 mdesc_caps
= mdesc_cpu_hwcap_list();
546 if (tlb_type
== spitfire
)
548 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
549 cap
|= AV_SPARC_VIS
| AV_SPARC_VIS2
;
550 if (tlb_type
== cheetah_plus
) {
551 unsigned long impl
, ver
;
553 __asm__
__volatile__("rdpr %%ver, %0" : "=r" (ver
));
554 impl
= ((ver
>> 32) & 0xffff);
555 if (impl
== PANTHER_IMPL
)
556 cap
|= AV_SPARC_POPC
;
558 if (tlb_type
== hypervisor
) {
559 if (sun4v_chip_type
== SUN4V_CHIP_NIAGARA1
)
560 cap
|= AV_SPARC_ASI_BLK_INIT
;
561 if (sun4v_chip_type
== SUN4V_CHIP_NIAGARA2
||
562 sun4v_chip_type
== SUN4V_CHIP_NIAGARA3
||
563 sun4v_chip_type
== SUN4V_CHIP_NIAGARA4
||
564 sun4v_chip_type
== SUN4V_CHIP_NIAGARA5
||
565 sun4v_chip_type
== SUN4V_CHIP_SPARC_M6
||
566 sun4v_chip_type
== SUN4V_CHIP_SPARC_M7
||
567 sun4v_chip_type
== SUN4V_CHIP_SPARC_SN
||
568 sun4v_chip_type
== SUN4V_CHIP_SPARC64X
)
569 cap
|= (AV_SPARC_VIS
| AV_SPARC_VIS2
|
570 AV_SPARC_ASI_BLK_INIT
|
572 if (sun4v_chip_type
== SUN4V_CHIP_NIAGARA3
||
573 sun4v_chip_type
== SUN4V_CHIP_NIAGARA4
||
574 sun4v_chip_type
== SUN4V_CHIP_NIAGARA5
||
575 sun4v_chip_type
== SUN4V_CHIP_SPARC_M6
||
576 sun4v_chip_type
== SUN4V_CHIP_SPARC_M7
||
577 sun4v_chip_type
== SUN4V_CHIP_SPARC_SN
||
578 sun4v_chip_type
== SUN4V_CHIP_SPARC64X
)
579 cap
|= (AV_SPARC_VIS3
| AV_SPARC_HPC
|
583 sparc64_elf_hwcap
= cap
| mdesc_caps
;
585 report_hwcaps(sparc64_elf_hwcap
);
587 if (sparc64_elf_hwcap
& AV_SPARC_POPC
)
589 if (sparc64_elf_hwcap
& AV_SPARC_PAUSE
)
593 void __init
setup_arch(char **cmdline_p
)
595 /* Initialize PROM console and command line. */
596 *cmdline_p
= prom_getbootargs();
597 strlcpy(boot_command_line
, *cmdline_p
, COMMAND_LINE_SIZE
);
600 boot_flags_init(*cmdline_p
);
601 #ifdef CONFIG_EARLYFB
602 if (btext_find_display())
604 register_console(&prom_early_console
);
606 if (tlb_type
== hypervisor
)
607 printk("ARCH: SUN4V\n");
609 printk("ARCH: SUN4U\n");
611 #ifdef CONFIG_DUMMY_CONSOLE
612 conswitchp
= &dummy_con
;
618 root_mountflags
&= ~MS_RDONLY
;
619 ROOT_DEV
= old_decode_dev(root_dev
);
620 #ifdef CONFIG_BLK_DEV_RAM
621 rd_image_start
= ram_flags
& RAMDISK_IMAGE_START_MASK
;
622 rd_prompt
= ((ram_flags
& RAMDISK_PROMPT_FLAG
) != 0);
623 rd_doload
= ((ram_flags
& RAMDISK_LOAD_FLAG
) != 0);
626 task_thread_info(&init_task
)->kregs
= &fake_swapper_regs
;
629 if (!ic_set_manually
) {
630 phandle chosen
= prom_finddevice("/chosen");
633 cl
= prom_getintdefault (chosen
, "client-ip", 0);
634 sv
= prom_getintdefault (chosen
, "server-ip", 0);
635 gw
= prom_getintdefault (chosen
, "gateway-ip", 0);
641 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
642 ic_proto_enabled
= 0;
648 /* Get boot processor trap_block[] setup. */
649 init_cur_cpu_trap(current_thread_info());
652 init_sparc64_elf_hwcap();
655 extern int stop_a_enabled
;
657 void sun_do_break(void)
663 flush_user_windows();
667 EXPORT_SYMBOL(sun_do_break
);
669 int stop_a_enabled
= 1;
670 EXPORT_SYMBOL(stop_a_enabled
);