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Linux 4.8-rc8
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob96de97a460791ae70efa8f6b0ff91e736363c5e9
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
58
59 #define LOOP_TIMEOUT 100000
60
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
65
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
71
72 /*
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
76 * that we support.
77 *
78 * 512GB Pages are not supported due to a hardware bug
79 */
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
81
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
83
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
87
88 LIST_HEAD(ioapic_map);
89 LIST_HEAD(hpet_map);
90 LIST_HEAD(acpihid_map);
91
92 #define FLUSH_QUEUE_SIZE 256
93
94 struct flush_queue_entry {
95 unsigned long iova_pfn;
96 unsigned long pages;
97 struct dma_ops_domain *dma_dom;
98 };
99
100 struct flush_queue {
101 spinlock_t lock;
102 unsigned next;
103 struct flush_queue_entry *entries;
104 };
105
106 DEFINE_PER_CPU(struct flush_queue, flush_queue);
107
108 static atomic_t queue_timer_on;
109 static struct timer_list queue_timer;
110
111 /*
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
114 */
115 static const struct iommu_ops amd_iommu_ops;
116
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
118 int amd_iommu_max_glx_val = -1;
119
120 static struct dma_map_ops amd_iommu_dma_ops;
121
122 /*
123 * This struct contains device specific data for the IOMMU
124 */
125 struct iommu_dev_data {
126 struct list_head list; /* For domain->dev_list */
127 struct list_head dev_data_list; /* For global dev_data_list */
128 struct protection_domain *domain; /* Domain the device is bound to */
129 u16 devid; /* PCI Device ID */
130 u16 alias; /* Alias Device ID */
131 bool iommu_v2; /* Device can make use of IOMMUv2 */
132 bool passthrough; /* Device is identity mapped */
133 struct {
134 bool enabled;
135 int qdep;
136 } ats; /* ATS state */
137 bool pri_tlp; /* PASID TLB required for
138 PPR completions */
139 u32 errata; /* Bitmap for errata to apply */
140 };
141
142 /*
143 * general struct to manage commands send to an IOMMU
144 */
145 struct iommu_cmd {
146 u32 data[4];
147 };
148
149 struct kmem_cache *amd_iommu_irq_cache;
150
151 static void update_domain(struct protection_domain *domain);
152 static int protection_domain_init(struct protection_domain *domain);
153 static void detach_device(struct device *dev);
154
155 /*
156 * Data container for a dma_ops specific protection domain
157 */
158 struct dma_ops_domain {
159 /* generic protection domain information */
160 struct protection_domain domain;
161
162 /* IOVA RB-Tree */
163 struct iova_domain iovad;
164 };
165
166 static struct iova_domain reserved_iova_ranges;
167 static struct lock_class_key reserved_rbtree_key;
168
169 /****************************************************************************
170 *
171 * Helper functions
172 *
173 ****************************************************************************/
174
175 static inline int match_hid_uid(struct device *dev,
176 struct acpihid_map_entry *entry)
177 {
178 const char *hid, *uid;
179
180 hid = acpi_device_hid(ACPI_COMPANION(dev));
181 uid = acpi_device_uid(ACPI_COMPANION(dev));
182
183 if (!hid || !(*hid))
184 return -ENODEV;
185
186 if (!uid || !(*uid))
187 return strcmp(hid, entry->hid);
188
189 if (!(*entry->uid))
190 return strcmp(hid, entry->hid);
191
192 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
193 }
194
195 static inline u16 get_pci_device_id(struct device *dev)
196 {
197 struct pci_dev *pdev = to_pci_dev(dev);
198
199 return PCI_DEVID(pdev->bus->number, pdev->devfn);
200 }
201
202 static inline int get_acpihid_device_id(struct device *dev,
203 struct acpihid_map_entry **entry)
204 {
205 struct acpihid_map_entry *p;
206
207 list_for_each_entry(p, &acpihid_map, list) {
208 if (!match_hid_uid(dev, p)) {
209 if (entry)
210 *entry = p;
211 return p->devid;
212 }
213 }
214 return -EINVAL;
215 }
216
217 static inline int get_device_id(struct device *dev)
218 {
219 int devid;
220
221 if (dev_is_pci(dev))
222 devid = get_pci_device_id(dev);
223 else
224 devid = get_acpihid_device_id(dev, NULL);
225
226 return devid;
227 }
228
229 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
230 {
231 return container_of(dom, struct protection_domain, domain);
232 }
233
234 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
235 {
236 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
237 return container_of(domain, struct dma_ops_domain, domain);
238 }
239
240 static struct iommu_dev_data *alloc_dev_data(u16 devid)
241 {
242 struct iommu_dev_data *dev_data;
243 unsigned long flags;
244
245 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
246 if (!dev_data)
247 return NULL;
248
249 dev_data->devid = devid;
250
251 spin_lock_irqsave(&dev_data_list_lock, flags);
252 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
253 spin_unlock_irqrestore(&dev_data_list_lock, flags);
254
255 return dev_data;
256 }
257
258 static struct iommu_dev_data *search_dev_data(u16 devid)
259 {
260 struct iommu_dev_data *dev_data;
261 unsigned long flags;
262
263 spin_lock_irqsave(&dev_data_list_lock, flags);
264 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
265 if (dev_data->devid == devid)
266 goto out_unlock;
267 }
268
269 dev_data = NULL;
270
271 out_unlock:
272 spin_unlock_irqrestore(&dev_data_list_lock, flags);
273
274 return dev_data;
275 }
276
277 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
278 {
279 *(u16 *)data = alias;
280 return 0;
281 }
282
283 static u16 get_alias(struct device *dev)
284 {
285 struct pci_dev *pdev = to_pci_dev(dev);
286 u16 devid, ivrs_alias, pci_alias;
287
288 /* The callers make sure that get_device_id() does not fail here */
289 devid = get_device_id(dev);
290 ivrs_alias = amd_iommu_alias_table[devid];
291 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
292
293 if (ivrs_alias == pci_alias)
294 return ivrs_alias;
295
296 /*
297 * DMA alias showdown
298 *
299 * The IVRS is fairly reliable in telling us about aliases, but it
300 * can't know about every screwy device. If we don't have an IVRS
301 * reported alias, use the PCI reported alias. In that case we may
302 * still need to initialize the rlookup and dev_table entries if the
303 * alias is to a non-existent device.
304 */
305 if (ivrs_alias == devid) {
306 if (!amd_iommu_rlookup_table[pci_alias]) {
307 amd_iommu_rlookup_table[pci_alias] =
308 amd_iommu_rlookup_table[devid];
309 memcpy(amd_iommu_dev_table[pci_alias].data,
310 amd_iommu_dev_table[devid].data,
311 sizeof(amd_iommu_dev_table[pci_alias].data));
312 }
313
314 return pci_alias;
315 }
316
317 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
318 "for device %s[%04x:%04x], kernel reported alias "
319 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
320 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
321 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
322 PCI_FUNC(pci_alias));
323
324 /*
325 * If we don't have a PCI DMA alias and the IVRS alias is on the same
326 * bus, then the IVRS table may know about a quirk that we don't.
327 */
328 if (pci_alias == devid &&
329 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
330 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
331 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
332 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
333 dev_name(dev));
334 }
335
336 return ivrs_alias;
337 }
338
339 static struct iommu_dev_data *find_dev_data(u16 devid)
340 {
341 struct iommu_dev_data *dev_data;
342
343 dev_data = search_dev_data(devid);
344
345 if (dev_data == NULL)
346 dev_data = alloc_dev_data(devid);
347
348 return dev_data;
349 }
350
351 static struct iommu_dev_data *get_dev_data(struct device *dev)
352 {
353 return dev->archdata.iommu;
354 }
355
356 /*
357 * Find or create an IOMMU group for a acpihid device.
358 */
359 static struct iommu_group *acpihid_device_group(struct device *dev)
360 {
361 struct acpihid_map_entry *p, *entry = NULL;
362 int devid;
363
364 devid = get_acpihid_device_id(dev, &entry);
365 if (devid < 0)
366 return ERR_PTR(devid);
367
368 list_for_each_entry(p, &acpihid_map, list) {
369 if ((devid == p->devid) && p->group)
370 entry->group = p->group;
371 }
372
373 if (!entry->group)
374 entry->group = generic_device_group(dev);
375
376 return entry->group;
377 }
378
379 static bool pci_iommuv2_capable(struct pci_dev *pdev)
380 {
381 static const int caps[] = {
382 PCI_EXT_CAP_ID_ATS,
383 PCI_EXT_CAP_ID_PRI,
384 PCI_EXT_CAP_ID_PASID,
385 };
386 int i, pos;
387
388 for (i = 0; i < 3; ++i) {
389 pos = pci_find_ext_capability(pdev, caps[i]);
390 if (pos == 0)
391 return false;
392 }
393
394 return true;
395 }
396
397 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
398 {
399 struct iommu_dev_data *dev_data;
400
401 dev_data = get_dev_data(&pdev->dev);
402
403 return dev_data->errata & (1 << erratum) ? true : false;
404 }
405
406 /*
407 * This function checks if the driver got a valid device from the caller to
408 * avoid dereferencing invalid pointers.
409 */
410 static bool check_device(struct device *dev)
411 {
412 int devid;
413
414 if (!dev || !dev->dma_mask)
415 return false;
416
417 devid = get_device_id(dev);
418 if (devid < 0)
419 return false;
420
421 /* Out of our scope? */
422 if (devid > amd_iommu_last_bdf)
423 return false;
424
425 if (amd_iommu_rlookup_table[devid] == NULL)
426 return false;
427
428 return true;
429 }
430
431 static void init_iommu_group(struct device *dev)
432 {
433 struct iommu_group *group;
434
435 group = iommu_group_get_for_dev(dev);
436 if (IS_ERR(group))
437 return;
438
439 iommu_group_put(group);
440 }
441
442 static int iommu_init_device(struct device *dev)
443 {
444 struct iommu_dev_data *dev_data;
445 int devid;
446
447 if (dev->archdata.iommu)
448 return 0;
449
450 devid = get_device_id(dev);
451 if (devid < 0)
452 return devid;
453
454 dev_data = find_dev_data(devid);
455 if (!dev_data)
456 return -ENOMEM;
457
458 dev_data->alias = get_alias(dev);
459
460 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
461 struct amd_iommu *iommu;
462
463 iommu = amd_iommu_rlookup_table[dev_data->devid];
464 dev_data->iommu_v2 = iommu->is_iommu_v2;
465 }
466
467 dev->archdata.iommu = dev_data;
468
469 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
470 dev);
471
472 return 0;
473 }
474
475 static void iommu_ignore_device(struct device *dev)
476 {
477 u16 alias;
478 int devid;
479
480 devid = get_device_id(dev);
481 if (devid < 0)
482 return;
483
484 alias = get_alias(dev);
485
486 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
487 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
488
489 amd_iommu_rlookup_table[devid] = NULL;
490 amd_iommu_rlookup_table[alias] = NULL;
491 }
492
493 static void iommu_uninit_device(struct device *dev)
494 {
495 int devid;
496 struct iommu_dev_data *dev_data;
497
498 devid = get_device_id(dev);
499 if (devid < 0)
500 return;
501
502 dev_data = search_dev_data(devid);
503 if (!dev_data)
504 return;
505
506 if (dev_data->domain)
507 detach_device(dev);
508
509 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
510 dev);
511
512 iommu_group_remove_device(dev);
513
514 /* Remove dma-ops */
515 dev->archdata.dma_ops = NULL;
516
517 /*
518 * We keep dev_data around for unplugged devices and reuse it when the
519 * device is re-plugged - not doing so would introduce a ton of races.
520 */
521 }
522
523 /****************************************************************************
524 *
525 * Interrupt handling functions
526 *
527 ****************************************************************************/
528
529 static void dump_dte_entry(u16 devid)
530 {
531 int i;
532
533 for (i = 0; i < 4; ++i)
534 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
535 amd_iommu_dev_table[devid].data[i]);
536 }
537
538 static void dump_command(unsigned long phys_addr)
539 {
540 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
541 int i;
542
543 for (i = 0; i < 4; ++i)
544 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
545 }
546
547 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
548 {
549 int type, devid, domid, flags;
550 volatile u32 *event = __evt;
551 int count = 0;
552 u64 address;
553
554 retry:
555 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
556 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
557 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
558 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
559 address = (u64)(((u64)event[3]) << 32) | event[2];
560
561 if (type == 0) {
562 /* Did we hit the erratum? */
563 if (++count == LOOP_TIMEOUT) {
564 pr_err("AMD-Vi: No event written to event log\n");
565 return;
566 }
567 udelay(1);
568 goto retry;
569 }
570
571 printk(KERN_ERR "AMD-Vi: Event logged [");
572
573 switch (type) {
574 case EVENT_TYPE_ILL_DEV:
575 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
576 "address=0x%016llx flags=0x%04x]\n",
577 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
578 address, flags);
579 dump_dte_entry(devid);
580 break;
581 case EVENT_TYPE_IO_FAULT:
582 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
583 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
584 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
585 domid, address, flags);
586 break;
587 case EVENT_TYPE_DEV_TAB_ERR:
588 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
589 "address=0x%016llx flags=0x%04x]\n",
590 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
591 address, flags);
592 break;
593 case EVENT_TYPE_PAGE_TAB_ERR:
594 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
595 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
596 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
597 domid, address, flags);
598 break;
599 case EVENT_TYPE_ILL_CMD:
600 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
601 dump_command(address);
602 break;
603 case EVENT_TYPE_CMD_HARD_ERR:
604 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
605 "flags=0x%04x]\n", address, flags);
606 break;
607 case EVENT_TYPE_IOTLB_INV_TO:
608 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
609 "address=0x%016llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
611 address);
612 break;
613 case EVENT_TYPE_INV_DEV_REQ:
614 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
615 "address=0x%016llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
617 address, flags);
618 break;
619 default:
620 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
621 }
622
623 memset(__evt, 0, 4 * sizeof(u32));
624 }
625
626 static void iommu_poll_events(struct amd_iommu *iommu)
627 {
628 u32 head, tail;
629
630 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
631 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
632
633 while (head != tail) {
634 iommu_print_event(iommu, iommu->evt_buf + head);
635 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
636 }
637
638 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 }
640
641 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
642 {
643 struct amd_iommu_fault fault;
644
645 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
646 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
647 return;
648 }
649
650 fault.address = raw[1];
651 fault.pasid = PPR_PASID(raw[0]);
652 fault.device_id = PPR_DEVID(raw[0]);
653 fault.tag = PPR_TAG(raw[0]);
654 fault.flags = PPR_FLAGS(raw[0]);
655
656 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
657 }
658
659 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
660 {
661 u32 head, tail;
662
663 if (iommu->ppr_log == NULL)
664 return;
665
666 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
667 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
668
669 while (head != tail) {
670 volatile u64 *raw;
671 u64 entry[2];
672 int i;
673
674 raw = (u64 *)(iommu->ppr_log + head);
675
676 /*
677 * Hardware bug: Interrupt may arrive before the entry is
678 * written to memory. If this happens we need to wait for the
679 * entry to arrive.
680 */
681 for (i = 0; i < LOOP_TIMEOUT; ++i) {
682 if (PPR_REQ_TYPE(raw[0]) != 0)
683 break;
684 udelay(1);
685 }
686
687 /* Avoid memcpy function-call overhead */
688 entry[0] = raw[0];
689 entry[1] = raw[1];
690
691 /*
692 * To detect the hardware bug we need to clear the entry
693 * back to zero.
694 */
695 raw[0] = raw[1] = 0UL;
696
697 /* Update head pointer of hardware ring-buffer */
698 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
699 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700
701 /* Handle PPR entry */
702 iommu_handle_ppr_entry(iommu, entry);
703
704 /* Refresh ring-buffer information */
705 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
706 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
707 }
708 }
709
710 irqreturn_t amd_iommu_int_thread(int irq, void *data)
711 {
712 struct amd_iommu *iommu = (struct amd_iommu *) data;
713 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
714
715 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
716 /* Enable EVT and PPR interrupts again */
717 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
718 iommu->mmio_base + MMIO_STATUS_OFFSET);
719
720 if (status & MMIO_STATUS_EVT_INT_MASK) {
721 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
722 iommu_poll_events(iommu);
723 }
724
725 if (status & MMIO_STATUS_PPR_INT_MASK) {
726 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
727 iommu_poll_ppr_log(iommu);
728 }
729
730 /*
731 * Hardware bug: ERBT1312
732 * When re-enabling interrupt (by writing 1
733 * to clear the bit), the hardware might also try to set
734 * the interrupt bit in the event status register.
735 * In this scenario, the bit will be set, and disable
736 * subsequent interrupts.
737 *
738 * Workaround: The IOMMU driver should read back the
739 * status register and check if the interrupt bits are cleared.
740 * If not, driver will need to go through the interrupt handler
741 * again and re-clear the bits
742 */
743 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
744 }
745 return IRQ_HANDLED;
746 }
747
748 irqreturn_t amd_iommu_int_handler(int irq, void *data)
749 {
750 return IRQ_WAKE_THREAD;
751 }
752
753 /****************************************************************************
754 *
755 * IOMMU command queuing functions
756 *
757 ****************************************************************************/
758
759 static int wait_on_sem(volatile u64 *sem)
760 {
761 int i = 0;
762
763 while (*sem == 0 && i < LOOP_TIMEOUT) {
764 udelay(1);
765 i += 1;
766 }
767
768 if (i == LOOP_TIMEOUT) {
769 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
770 return -EIO;
771 }
772
773 return 0;
774 }
775
776 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
777 struct iommu_cmd *cmd,
778 u32 tail)
779 {
780 u8 *target;
781
782 target = iommu->cmd_buf + tail;
783 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
784
785 /* Copy command to buffer */
786 memcpy(target, cmd, sizeof(*cmd));
787
788 /* Tell the IOMMU about it */
789 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
790 }
791
792 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
793 {
794 WARN_ON(address & 0x7ULL);
795
796 memset(cmd, 0, sizeof(*cmd));
797 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
798 cmd->data[1] = upper_32_bits(__pa(address));
799 cmd->data[2] = 1;
800 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
801 }
802
803 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
804 {
805 memset(cmd, 0, sizeof(*cmd));
806 cmd->data[0] = devid;
807 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
808 }
809
810 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
811 size_t size, u16 domid, int pde)
812 {
813 u64 pages;
814 bool s;
815
816 pages = iommu_num_pages(address, size, PAGE_SIZE);
817 s = false;
818
819 if (pages > 1) {
820 /*
821 * If we have to flush more than one page, flush all
822 * TLB entries for this domain
823 */
824 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
825 s = true;
826 }
827
828 address &= PAGE_MASK;
829
830 memset(cmd, 0, sizeof(*cmd));
831 cmd->data[1] |= domid;
832 cmd->data[2] = lower_32_bits(address);
833 cmd->data[3] = upper_32_bits(address);
834 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
835 if (s) /* size bit - we flush more than one 4kb page */
836 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
837 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
838 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
839 }
840
841 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
842 u64 address, size_t size)
843 {
844 u64 pages;
845 bool s;
846
847 pages = iommu_num_pages(address, size, PAGE_SIZE);
848 s = false;
849
850 if (pages > 1) {
851 /*
852 * If we have to flush more than one page, flush all
853 * TLB entries for this domain
854 */
855 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
856 s = true;
857 }
858
859 address &= PAGE_MASK;
860
861 memset(cmd, 0, sizeof(*cmd));
862 cmd->data[0] = devid;
863 cmd->data[0] |= (qdep & 0xff) << 24;
864 cmd->data[1] = devid;
865 cmd->data[2] = lower_32_bits(address);
866 cmd->data[3] = upper_32_bits(address);
867 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
868 if (s)
869 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
870 }
871
872 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
873 u64 address, bool size)
874 {
875 memset(cmd, 0, sizeof(*cmd));
876
877 address &= ~(0xfffULL);
878
879 cmd->data[0] = pasid;
880 cmd->data[1] = domid;
881 cmd->data[2] = lower_32_bits(address);
882 cmd->data[3] = upper_32_bits(address);
883 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
884 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
885 if (size)
886 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
887 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
888 }
889
890 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
891 int qdep, u64 address, bool size)
892 {
893 memset(cmd, 0, sizeof(*cmd));
894
895 address &= ~(0xfffULL);
896
897 cmd->data[0] = devid;
898 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
899 cmd->data[0] |= (qdep & 0xff) << 24;
900 cmd->data[1] = devid;
901 cmd->data[1] |= (pasid & 0xff) << 16;
902 cmd->data[2] = lower_32_bits(address);
903 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
904 cmd->data[3] = upper_32_bits(address);
905 if (size)
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
907 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
908 }
909
910 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
911 int status, int tag, bool gn)
912 {
913 memset(cmd, 0, sizeof(*cmd));
914
915 cmd->data[0] = devid;
916 if (gn) {
917 cmd->data[1] = pasid;
918 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
919 }
920 cmd->data[3] = tag & 0x1ff;
921 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
922
923 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
924 }
925
926 static void build_inv_all(struct iommu_cmd *cmd)
927 {
928 memset(cmd, 0, sizeof(*cmd));
929 CMD_SET_TYPE(cmd, CMD_INV_ALL);
930 }
931
932 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
933 {
934 memset(cmd, 0, sizeof(*cmd));
935 cmd->data[0] = devid;
936 CMD_SET_TYPE(cmd, CMD_INV_IRT);
937 }
938
939 /*
940 * Writes the command to the IOMMUs command buffer and informs the
941 * hardware about the new command.
942 */
943 static int iommu_queue_command_sync(struct amd_iommu *iommu,
944 struct iommu_cmd *cmd,
945 bool sync)
946 {
947 u32 left, tail, head, next_tail;
948 unsigned long flags;
949
950 again:
951 spin_lock_irqsave(&iommu->lock, flags);
952
953 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
954 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
955 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
956 left = (head - next_tail) % CMD_BUFFER_SIZE;
957
958 if (left <= 2) {
959 struct iommu_cmd sync_cmd;
960 volatile u64 sem = 0;
961 int ret;
962
963 build_completion_wait(&sync_cmd, (u64)&sem);
964 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
965
966 spin_unlock_irqrestore(&iommu->lock, flags);
967
968 if ((ret = wait_on_sem(&sem)) != 0)
969 return ret;
970
971 goto again;
972 }
973
974 copy_cmd_to_buffer(iommu, cmd, tail);
975
976 /* We need to sync now to make sure all commands are processed */
977 iommu->need_sync = sync;
978
979 spin_unlock_irqrestore(&iommu->lock, flags);
980
981 return 0;
982 }
983
984 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
985 {
986 return iommu_queue_command_sync(iommu, cmd, true);
987 }
988
989 /*
990 * This function queues a completion wait command into the command
991 * buffer of an IOMMU
992 */
993 static int iommu_completion_wait(struct amd_iommu *iommu)
994 {
995 struct iommu_cmd cmd;
996 volatile u64 sem = 0;
997 int ret;
998
999 if (!iommu->need_sync)
1000 return 0;
1001
1002 build_completion_wait(&cmd, (u64)&sem);
1003
1004 ret = iommu_queue_command_sync(iommu, &cmd, false);
1005 if (ret)
1006 return ret;
1007
1008 return wait_on_sem(&sem);
1009 }
1010
1011 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1012 {
1013 struct iommu_cmd cmd;
1014
1015 build_inv_dte(&cmd, devid);
1016
1017 return iommu_queue_command(iommu, &cmd);
1018 }
1019
1020 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1021 {
1022 u32 devid;
1023
1024 for (devid = 0; devid <= 0xffff; ++devid)
1025 iommu_flush_dte(iommu, devid);
1026
1027 iommu_completion_wait(iommu);
1028 }
1029
1030 /*
1031 * This function uses heavy locking and may disable irqs for some time. But
1032 * this is no issue because it is only called during resume.
1033 */
1034 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1035 {
1036 u32 dom_id;
1037
1038 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1039 struct iommu_cmd cmd;
1040 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1041 dom_id, 1);
1042 iommu_queue_command(iommu, &cmd);
1043 }
1044
1045 iommu_completion_wait(iommu);
1046 }
1047
1048 static void iommu_flush_all(struct amd_iommu *iommu)
1049 {
1050 struct iommu_cmd cmd;
1051
1052 build_inv_all(&cmd);
1053
1054 iommu_queue_command(iommu, &cmd);
1055 iommu_completion_wait(iommu);
1056 }
1057
1058 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1059 {
1060 struct iommu_cmd cmd;
1061
1062 build_inv_irt(&cmd, devid);
1063
1064 iommu_queue_command(iommu, &cmd);
1065 }
1066
1067 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1068 {
1069 u32 devid;
1070
1071 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1072 iommu_flush_irt(iommu, devid);
1073
1074 iommu_completion_wait(iommu);
1075 }
1076
1077 void iommu_flush_all_caches(struct amd_iommu *iommu)
1078 {
1079 if (iommu_feature(iommu, FEATURE_IA)) {
1080 iommu_flush_all(iommu);
1081 } else {
1082 iommu_flush_dte_all(iommu);
1083 iommu_flush_irt_all(iommu);
1084 iommu_flush_tlb_all(iommu);
1085 }
1086 }
1087
1088 /*
1089 * Command send function for flushing on-device TLB
1090 */
1091 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1092 u64 address, size_t size)
1093 {
1094 struct amd_iommu *iommu;
1095 struct iommu_cmd cmd;
1096 int qdep;
1097
1098 qdep = dev_data->ats.qdep;
1099 iommu = amd_iommu_rlookup_table[dev_data->devid];
1100
1101 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1102
1103 return iommu_queue_command(iommu, &cmd);
1104 }
1105
1106 /*
1107 * Command send function for invalidating a device table entry
1108 */
1109 static int device_flush_dte(struct iommu_dev_data *dev_data)
1110 {
1111 struct amd_iommu *iommu;
1112 u16 alias;
1113 int ret;
1114
1115 iommu = amd_iommu_rlookup_table[dev_data->devid];
1116 alias = dev_data->alias;
1117
1118 ret = iommu_flush_dte(iommu, dev_data->devid);
1119 if (!ret && alias != dev_data->devid)
1120 ret = iommu_flush_dte(iommu, alias);
1121 if (ret)
1122 return ret;
1123
1124 if (dev_data->ats.enabled)
1125 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1126
1127 return ret;
1128 }
1129
1130 /*
1131 * TLB invalidation function which is called from the mapping functions.
1132 * It invalidates a single PTE if the range to flush is within a single
1133 * page. Otherwise it flushes the whole TLB of the IOMMU.
1134 */
1135 static void __domain_flush_pages(struct protection_domain *domain,
1136 u64 address, size_t size, int pde)
1137 {
1138 struct iommu_dev_data *dev_data;
1139 struct iommu_cmd cmd;
1140 int ret = 0, i;
1141
1142 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1143
1144 for (i = 0; i < amd_iommus_present; ++i) {
1145 if (!domain->dev_iommu[i])
1146 continue;
1147
1148 /*
1149 * Devices of this domain are behind this IOMMU
1150 * We need a TLB flush
1151 */
1152 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1153 }
1154
1155 list_for_each_entry(dev_data, &domain->dev_list, list) {
1156
1157 if (!dev_data->ats.enabled)
1158 continue;
1159
1160 ret |= device_flush_iotlb(dev_data, address, size);
1161 }
1162
1163 WARN_ON(ret);
1164 }
1165
1166 static void domain_flush_pages(struct protection_domain *domain,
1167 u64 address, size_t size)
1168 {
1169 __domain_flush_pages(domain, address, size, 0);
1170 }
1171
1172 /* Flush the whole IO/TLB for a given protection domain */
1173 static void domain_flush_tlb(struct protection_domain *domain)
1174 {
1175 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1176 }
1177
1178 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1179 static void domain_flush_tlb_pde(struct protection_domain *domain)
1180 {
1181 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1182 }
1183
1184 static void domain_flush_complete(struct protection_domain *domain)
1185 {
1186 int i;
1187
1188 for (i = 0; i < amd_iommus_present; ++i) {
1189 if (domain && !domain->dev_iommu[i])
1190 continue;
1191
1192 /*
1193 * Devices of this domain are behind this IOMMU
1194 * We need to wait for completion of all commands.
1195 */
1196 iommu_completion_wait(amd_iommus[i]);
1197 }
1198 }
1199
1200
1201 /*
1202 * This function flushes the DTEs for all devices in domain
1203 */
1204 static void domain_flush_devices(struct protection_domain *domain)
1205 {
1206 struct iommu_dev_data *dev_data;
1207
1208 list_for_each_entry(dev_data, &domain->dev_list, list)
1209 device_flush_dte(dev_data);
1210 }
1211
1212 /****************************************************************************
1213 *
1214 * The functions below are used the create the page table mappings for
1215 * unity mapped regions.
1216 *
1217 ****************************************************************************/
1218
1219 /*
1220 * This function is used to add another level to an IO page table. Adding
1221 * another level increases the size of the address space by 9 bits to a size up
1222 * to 64 bits.
1223 */
1224 static bool increase_address_space(struct protection_domain *domain,
1225 gfp_t gfp)
1226 {
1227 u64 *pte;
1228
1229 if (domain->mode == PAGE_MODE_6_LEVEL)
1230 /* address space already 64 bit large */
1231 return false;
1232
1233 pte = (void *)get_zeroed_page(gfp);
1234 if (!pte)
1235 return false;
1236
1237 *pte = PM_LEVEL_PDE(domain->mode,
1238 virt_to_phys(domain->pt_root));
1239 domain->pt_root = pte;
1240 domain->mode += 1;
1241 domain->updated = true;
1242
1243 return true;
1244 }
1245
1246 static u64 *alloc_pte(struct protection_domain *domain,
1247 unsigned long address,
1248 unsigned long page_size,
1249 u64 **pte_page,
1250 gfp_t gfp)
1251 {
1252 int level, end_lvl;
1253 u64 *pte, *page;
1254
1255 BUG_ON(!is_power_of_2(page_size));
1256
1257 while (address > PM_LEVEL_SIZE(domain->mode))
1258 increase_address_space(domain, gfp);
1259
1260 level = domain->mode - 1;
1261 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1262 address = PAGE_SIZE_ALIGN(address, page_size);
1263 end_lvl = PAGE_SIZE_LEVEL(page_size);
1264
1265 while (level > end_lvl) {
1266 u64 __pte, __npte;
1267
1268 __pte = *pte;
1269
1270 if (!IOMMU_PTE_PRESENT(__pte)) {
1271 page = (u64 *)get_zeroed_page(gfp);
1272 if (!page)
1273 return NULL;
1274
1275 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1276
1277 if (cmpxchg64(pte, __pte, __npte)) {
1278 free_page((unsigned long)page);
1279 continue;
1280 }
1281 }
1282
1283 /* No level skipping support yet */
1284 if (PM_PTE_LEVEL(*pte) != level)
1285 return NULL;
1286
1287 level -= 1;
1288
1289 pte = IOMMU_PTE_PAGE(*pte);
1290
1291 if (pte_page && level == end_lvl)
1292 *pte_page = pte;
1293
1294 pte = &pte[PM_LEVEL_INDEX(level, address)];
1295 }
1296
1297 return pte;
1298 }
1299
1300 /*
1301 * This function checks if there is a PTE for a given dma address. If
1302 * there is one, it returns the pointer to it.
1303 */
1304 static u64 *fetch_pte(struct protection_domain *domain,
1305 unsigned long address,
1306 unsigned long *page_size)
1307 {
1308 int level;
1309 u64 *pte;
1310
1311 if (address > PM_LEVEL_SIZE(domain->mode))
1312 return NULL;
1313
1314 level = domain->mode - 1;
1315 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1316 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1317
1318 while (level > 0) {
1319
1320 /* Not Present */
1321 if (!IOMMU_PTE_PRESENT(*pte))
1322 return NULL;
1323
1324 /* Large PTE */
1325 if (PM_PTE_LEVEL(*pte) == 7 ||
1326 PM_PTE_LEVEL(*pte) == 0)
1327 break;
1328
1329 /* No level skipping support yet */
1330 if (PM_PTE_LEVEL(*pte) != level)
1331 return NULL;
1332
1333 level -= 1;
1334
1335 /* Walk to the next level */
1336 pte = IOMMU_PTE_PAGE(*pte);
1337 pte = &pte[PM_LEVEL_INDEX(level, address)];
1338 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1339 }
1340
1341 if (PM_PTE_LEVEL(*pte) == 0x07) {
1342 unsigned long pte_mask;
1343
1344 /*
1345 * If we have a series of large PTEs, make
1346 * sure to return a pointer to the first one.
1347 */
1348 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1349 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1350 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1351 }
1352
1353 return pte;
1354 }
1355
1356 /*
1357 * Generic mapping functions. It maps a physical address into a DMA
1358 * address space. It allocates the page table pages if necessary.
1359 * In the future it can be extended to a generic mapping function
1360 * supporting all features of AMD IOMMU page tables like level skipping
1361 * and full 64 bit address spaces.
1362 */
1363 static int iommu_map_page(struct protection_domain *dom,
1364 unsigned long bus_addr,
1365 unsigned long phys_addr,
1366 unsigned long page_size,
1367 int prot,
1368 gfp_t gfp)
1369 {
1370 u64 __pte, *pte;
1371 int i, count;
1372
1373 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1374 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1375
1376 if (!(prot & IOMMU_PROT_MASK))
1377 return -EINVAL;
1378
1379 count = PAGE_SIZE_PTE_COUNT(page_size);
1380 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1381
1382 if (!pte)
1383 return -ENOMEM;
1384
1385 for (i = 0; i < count; ++i)
1386 if (IOMMU_PTE_PRESENT(pte[i]))
1387 return -EBUSY;
1388
1389 if (count > 1) {
1390 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1391 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1392 } else
1393 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1394
1395 if (prot & IOMMU_PROT_IR)
1396 __pte |= IOMMU_PTE_IR;
1397 if (prot & IOMMU_PROT_IW)
1398 __pte |= IOMMU_PTE_IW;
1399
1400 for (i = 0; i < count; ++i)
1401 pte[i] = __pte;
1402
1403 update_domain(dom);
1404
1405 return 0;
1406 }
1407
1408 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1409 unsigned long bus_addr,
1410 unsigned long page_size)
1411 {
1412 unsigned long long unmapped;
1413 unsigned long unmap_size;
1414 u64 *pte;
1415
1416 BUG_ON(!is_power_of_2(page_size));
1417
1418 unmapped = 0;
1419
1420 while (unmapped < page_size) {
1421
1422 pte = fetch_pte(dom, bus_addr, &unmap_size);
1423
1424 if (pte) {
1425 int i, count;
1426
1427 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1428 for (i = 0; i < count; i++)
1429 pte[i] = 0ULL;
1430 }
1431
1432 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1433 unmapped += unmap_size;
1434 }
1435
1436 BUG_ON(unmapped && !is_power_of_2(unmapped));
1437
1438 return unmapped;
1439 }
1440
1441 /****************************************************************************
1442 *
1443 * The next functions belong to the address allocator for the dma_ops
1444 * interface functions.
1445 *
1446 ****************************************************************************/
1447
1448
1449 static unsigned long dma_ops_alloc_iova(struct device *dev,
1450 struct dma_ops_domain *dma_dom,
1451 unsigned int pages, u64 dma_mask)
1452 {
1453 unsigned long pfn = 0;
1454
1455 pages = __roundup_pow_of_two(pages);
1456
1457 if (dma_mask > DMA_BIT_MASK(32))
1458 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1459 IOVA_PFN(DMA_BIT_MASK(32)));
1460
1461 if (!pfn)
1462 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1463
1464 return (pfn << PAGE_SHIFT);
1465 }
1466
1467 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1468 unsigned long address,
1469 unsigned int pages)
1470 {
1471 pages = __roundup_pow_of_two(pages);
1472 address >>= PAGE_SHIFT;
1473
1474 free_iova_fast(&dma_dom->iovad, address, pages);
1475 }
1476
1477 /****************************************************************************
1478 *
1479 * The next functions belong to the domain allocation. A domain is
1480 * allocated for every IOMMU as the default domain. If device isolation
1481 * is enabled, every device get its own domain. The most important thing
1482 * about domains is the page table mapping the DMA address space they
1483 * contain.
1484 *
1485 ****************************************************************************/
1486
1487 /*
1488 * This function adds a protection domain to the global protection domain list
1489 */
1490 static void add_domain_to_list(struct protection_domain *domain)
1491 {
1492 unsigned long flags;
1493
1494 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1495 list_add(&domain->list, &amd_iommu_pd_list);
1496 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1497 }
1498
1499 /*
1500 * This function removes a protection domain to the global
1501 * protection domain list
1502 */
1503 static void del_domain_from_list(struct protection_domain *domain)
1504 {
1505 unsigned long flags;
1506
1507 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1508 list_del(&domain->list);
1509 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1510 }
1511
1512 static u16 domain_id_alloc(void)
1513 {
1514 unsigned long flags;
1515 int id;
1516
1517 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1518 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1519 BUG_ON(id == 0);
1520 if (id > 0 && id < MAX_DOMAIN_ID)
1521 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1522 else
1523 id = 0;
1524 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1525
1526 return id;
1527 }
1528
1529 static void domain_id_free(int id)
1530 {
1531 unsigned long flags;
1532
1533 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1534 if (id > 0 && id < MAX_DOMAIN_ID)
1535 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1536 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1537 }
1538
1539 #define DEFINE_FREE_PT_FN(LVL, FN) \
1540 static void free_pt_##LVL (unsigned long __pt) \
1541 { \
1542 unsigned long p; \
1543 u64 *pt; \
1544 int i; \
1545 \
1546 pt = (u64 *)__pt; \
1547 \
1548 for (i = 0; i < 512; ++i) { \
1549 /* PTE present? */ \
1550 if (!IOMMU_PTE_PRESENT(pt[i])) \
1551 continue; \
1552 \
1553 /* Large PTE? */ \
1554 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1555 PM_PTE_LEVEL(pt[i]) == 7) \
1556 continue; \
1557 \
1558 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1559 FN(p); \
1560 } \
1561 free_page((unsigned long)pt); \
1562 }
1563
1564 DEFINE_FREE_PT_FN(l2, free_page)
1565 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1566 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1567 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1568 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1569
1570 static void free_pagetable(struct protection_domain *domain)
1571 {
1572 unsigned long root = (unsigned long)domain->pt_root;
1573
1574 switch (domain->mode) {
1575 case PAGE_MODE_NONE:
1576 break;
1577 case PAGE_MODE_1_LEVEL:
1578 free_page(root);
1579 break;
1580 case PAGE_MODE_2_LEVEL:
1581 free_pt_l2(root);
1582 break;
1583 case PAGE_MODE_3_LEVEL:
1584 free_pt_l3(root);
1585 break;
1586 case PAGE_MODE_4_LEVEL:
1587 free_pt_l4(root);
1588 break;
1589 case PAGE_MODE_5_LEVEL:
1590 free_pt_l5(root);
1591 break;
1592 case PAGE_MODE_6_LEVEL:
1593 free_pt_l6(root);
1594 break;
1595 default:
1596 BUG();
1597 }
1598 }
1599
1600 static void free_gcr3_tbl_level1(u64 *tbl)
1601 {
1602 u64 *ptr;
1603 int i;
1604
1605 for (i = 0; i < 512; ++i) {
1606 if (!(tbl[i] & GCR3_VALID))
1607 continue;
1608
1609 ptr = __va(tbl[i] & PAGE_MASK);
1610
1611 free_page((unsigned long)ptr);
1612 }
1613 }
1614
1615 static void free_gcr3_tbl_level2(u64 *tbl)
1616 {
1617 u64 *ptr;
1618 int i;
1619
1620 for (i = 0; i < 512; ++i) {
1621 if (!(tbl[i] & GCR3_VALID))
1622 continue;
1623
1624 ptr = __va(tbl[i] & PAGE_MASK);
1625
1626 free_gcr3_tbl_level1(ptr);
1627 }
1628 }
1629
1630 static void free_gcr3_table(struct protection_domain *domain)
1631 {
1632 if (domain->glx == 2)
1633 free_gcr3_tbl_level2(domain->gcr3_tbl);
1634 else if (domain->glx == 1)
1635 free_gcr3_tbl_level1(domain->gcr3_tbl);
1636 else
1637 BUG_ON(domain->glx != 0);
1638
1639 free_page((unsigned long)domain->gcr3_tbl);
1640 }
1641
1642 /*
1643 * Free a domain, only used if something went wrong in the
1644 * allocation path and we need to free an already allocated page table
1645 */
1646 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1647 {
1648 if (!dom)
1649 return;
1650
1651 del_domain_from_list(&dom->domain);
1652
1653 put_iova_domain(&dom->iovad);
1654
1655 free_pagetable(&dom->domain);
1656
1657 kfree(dom);
1658 }
1659
1660 /*
1661 * Allocates a new protection domain usable for the dma_ops functions.
1662 * It also initializes the page table and the address allocator data
1663 * structures required for the dma_ops interface
1664 */
1665 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1666 {
1667 struct dma_ops_domain *dma_dom;
1668
1669 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1670 if (!dma_dom)
1671 return NULL;
1672
1673 if (protection_domain_init(&dma_dom->domain))
1674 goto free_dma_dom;
1675
1676 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1677 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1678 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1679 if (!dma_dom->domain.pt_root)
1680 goto free_dma_dom;
1681
1682 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1683 IOVA_START_PFN, DMA_32BIT_PFN);
1684
1685 /* Initialize reserved ranges */
1686 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1687
1688 add_domain_to_list(&dma_dom->domain);
1689
1690 return dma_dom;
1691
1692 free_dma_dom:
1693 dma_ops_domain_free(dma_dom);
1694
1695 return NULL;
1696 }
1697
1698 /*
1699 * little helper function to check whether a given protection domain is a
1700 * dma_ops domain
1701 */
1702 static bool dma_ops_domain(struct protection_domain *domain)
1703 {
1704 return domain->flags & PD_DMA_OPS_MASK;
1705 }
1706
1707 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1708 {
1709 u64 pte_root = 0;
1710 u64 flags = 0;
1711
1712 if (domain->mode != PAGE_MODE_NONE)
1713 pte_root = virt_to_phys(domain->pt_root);
1714
1715 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1716 << DEV_ENTRY_MODE_SHIFT;
1717 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1718
1719 flags = amd_iommu_dev_table[devid].data[1];
1720
1721 if (ats)
1722 flags |= DTE_FLAG_IOTLB;
1723
1724 if (domain->flags & PD_IOMMUV2_MASK) {
1725 u64 gcr3 = __pa(domain->gcr3_tbl);
1726 u64 glx = domain->glx;
1727 u64 tmp;
1728
1729 pte_root |= DTE_FLAG_GV;
1730 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1731
1732 /* First mask out possible old values for GCR3 table */
1733 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1734 flags &= ~tmp;
1735
1736 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1737 flags &= ~tmp;
1738
1739 /* Encode GCR3 table into DTE */
1740 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1741 pte_root |= tmp;
1742
1743 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1744 flags |= tmp;
1745
1746 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1747 flags |= tmp;
1748 }
1749
1750 flags &= ~(0xffffUL);
1751 flags |= domain->id;
1752
1753 amd_iommu_dev_table[devid].data[1] = flags;
1754 amd_iommu_dev_table[devid].data[0] = pte_root;
1755 }
1756
1757 static void clear_dte_entry(u16 devid)
1758 {
1759 /* remove entry from the device table seen by the hardware */
1760 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1761 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1762
1763 amd_iommu_apply_erratum_63(devid);
1764 }
1765
1766 static void do_attach(struct iommu_dev_data *dev_data,
1767 struct protection_domain *domain)
1768 {
1769 struct amd_iommu *iommu;
1770 u16 alias;
1771 bool ats;
1772
1773 iommu = amd_iommu_rlookup_table[dev_data->devid];
1774 alias = dev_data->alias;
1775 ats = dev_data->ats.enabled;
1776
1777 /* Update data structures */
1778 dev_data->domain = domain;
1779 list_add(&dev_data->list, &domain->dev_list);
1780
1781 /* Do reference counting */
1782 domain->dev_iommu[iommu->index] += 1;
1783 domain->dev_cnt += 1;
1784
1785 /* Update device table */
1786 set_dte_entry(dev_data->devid, domain, ats);
1787 if (alias != dev_data->devid)
1788 set_dte_entry(alias, domain, ats);
1789
1790 device_flush_dte(dev_data);
1791 }
1792
1793 static void do_detach(struct iommu_dev_data *dev_data)
1794 {
1795 struct amd_iommu *iommu;
1796 u16 alias;
1797
1798 /*
1799 * First check if the device is still attached. It might already
1800 * be detached from its domain because the generic
1801 * iommu_detach_group code detached it and we try again here in
1802 * our alias handling.
1803 */
1804 if (!dev_data->domain)
1805 return;
1806
1807 iommu = amd_iommu_rlookup_table[dev_data->devid];
1808 alias = dev_data->alias;
1809
1810 /* decrease reference counters */
1811 dev_data->domain->dev_iommu[iommu->index] -= 1;
1812 dev_data->domain->dev_cnt -= 1;
1813
1814 /* Update data structures */
1815 dev_data->domain = NULL;
1816 list_del(&dev_data->list);
1817 clear_dte_entry(dev_data->devid);
1818 if (alias != dev_data->devid)
1819 clear_dte_entry(alias);
1820
1821 /* Flush the DTE entry */
1822 device_flush_dte(dev_data);
1823 }
1824
1825 /*
1826 * If a device is not yet associated with a domain, this function does
1827 * assigns it visible for the hardware
1828 */
1829 static int __attach_device(struct iommu_dev_data *dev_data,
1830 struct protection_domain *domain)
1831 {
1832 int ret;
1833
1834 /*
1835 * Must be called with IRQs disabled. Warn here to detect early
1836 * when its not.
1837 */
1838 WARN_ON(!irqs_disabled());
1839
1840 /* lock domain */
1841 spin_lock(&domain->lock);
1842
1843 ret = -EBUSY;
1844 if (dev_data->domain != NULL)
1845 goto out_unlock;
1846
1847 /* Attach alias group root */
1848 do_attach(dev_data, domain);
1849
1850 ret = 0;
1851
1852 out_unlock:
1853
1854 /* ready */
1855 spin_unlock(&domain->lock);
1856
1857 return ret;
1858 }
1859
1860
1861 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1862 {
1863 pci_disable_ats(pdev);
1864 pci_disable_pri(pdev);
1865 pci_disable_pasid(pdev);
1866 }
1867
1868 /* FIXME: Change generic reset-function to do the same */
1869 static int pri_reset_while_enabled(struct pci_dev *pdev)
1870 {
1871 u16 control;
1872 int pos;
1873
1874 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1875 if (!pos)
1876 return -EINVAL;
1877
1878 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1879 control |= PCI_PRI_CTRL_RESET;
1880 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1881
1882 return 0;
1883 }
1884
1885 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1886 {
1887 bool reset_enable;
1888 int reqs, ret;
1889
1890 /* FIXME: Hardcode number of outstanding requests for now */
1891 reqs = 32;
1892 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1893 reqs = 1;
1894 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1895
1896 /* Only allow access to user-accessible pages */
1897 ret = pci_enable_pasid(pdev, 0);
1898 if (ret)
1899 goto out_err;
1900
1901 /* First reset the PRI state of the device */
1902 ret = pci_reset_pri(pdev);
1903 if (ret)
1904 goto out_err;
1905
1906 /* Enable PRI */
1907 ret = pci_enable_pri(pdev, reqs);
1908 if (ret)
1909 goto out_err;
1910
1911 if (reset_enable) {
1912 ret = pri_reset_while_enabled(pdev);
1913 if (ret)
1914 goto out_err;
1915 }
1916
1917 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1918 if (ret)
1919 goto out_err;
1920
1921 return 0;
1922
1923 out_err:
1924 pci_disable_pri(pdev);
1925 pci_disable_pasid(pdev);
1926
1927 return ret;
1928 }
1929
1930 /* FIXME: Move this to PCI code */
1931 #define PCI_PRI_TLP_OFF (1 << 15)
1932
1933 static bool pci_pri_tlp_required(struct pci_dev *pdev)
1934 {
1935 u16 status;
1936 int pos;
1937
1938 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1939 if (!pos)
1940 return false;
1941
1942 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
1943
1944 return (status & PCI_PRI_TLP_OFF) ? true : false;
1945 }
1946
1947 /*
1948 * If a device is not yet associated with a domain, this function
1949 * assigns it visible for the hardware
1950 */
1951 static int attach_device(struct device *dev,
1952 struct protection_domain *domain)
1953 {
1954 struct pci_dev *pdev;
1955 struct iommu_dev_data *dev_data;
1956 unsigned long flags;
1957 int ret;
1958
1959 dev_data = get_dev_data(dev);
1960
1961 if (!dev_is_pci(dev))
1962 goto skip_ats_check;
1963
1964 pdev = to_pci_dev(dev);
1965 if (domain->flags & PD_IOMMUV2_MASK) {
1966 if (!dev_data->passthrough)
1967 return -EINVAL;
1968
1969 if (dev_data->iommu_v2) {
1970 if (pdev_iommuv2_enable(pdev) != 0)
1971 return -EINVAL;
1972
1973 dev_data->ats.enabled = true;
1974 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1975 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
1976 }
1977 } else if (amd_iommu_iotlb_sup &&
1978 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1979 dev_data->ats.enabled = true;
1980 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1981 }
1982
1983 skip_ats_check:
1984 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1985 ret = __attach_device(dev_data, domain);
1986 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1987
1988 /*
1989 * We might boot into a crash-kernel here. The crashed kernel
1990 * left the caches in the IOMMU dirty. So we have to flush
1991 * here to evict all dirty stuff.
1992 */
1993 domain_flush_tlb_pde(domain);
1994
1995 return ret;
1996 }
1997
1998 /*
1999 * Removes a device from a protection domain (unlocked)
2000 */
2001 static void __detach_device(struct iommu_dev_data *dev_data)
2002 {
2003 struct protection_domain *domain;
2004
2005 /*
2006 * Must be called with IRQs disabled. Warn here to detect early
2007 * when its not.
2008 */
2009 WARN_ON(!irqs_disabled());
2010
2011 if (WARN_ON(!dev_data->domain))
2012 return;
2013
2014 domain = dev_data->domain;
2015
2016 spin_lock(&domain->lock);
2017
2018 do_detach(dev_data);
2019
2020 spin_unlock(&domain->lock);
2021 }
2022
2023 /*
2024 * Removes a device from a protection domain (with devtable_lock held)
2025 */
2026 static void detach_device(struct device *dev)
2027 {
2028 struct protection_domain *domain;
2029 struct iommu_dev_data *dev_data;
2030 unsigned long flags;
2031
2032 dev_data = get_dev_data(dev);
2033 domain = dev_data->domain;
2034
2035 /* lock device table */
2036 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2037 __detach_device(dev_data);
2038 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2039
2040 if (!dev_is_pci(dev))
2041 return;
2042
2043 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2044 pdev_iommuv2_disable(to_pci_dev(dev));
2045 else if (dev_data->ats.enabled)
2046 pci_disable_ats(to_pci_dev(dev));
2047
2048 dev_data->ats.enabled = false;
2049 }
2050
2051 static int amd_iommu_add_device(struct device *dev)
2052 {
2053 struct iommu_dev_data *dev_data;
2054 struct iommu_domain *domain;
2055 struct amd_iommu *iommu;
2056 int ret, devid;
2057
2058 if (!check_device(dev) || get_dev_data(dev))
2059 return 0;
2060
2061 devid = get_device_id(dev);
2062 if (devid < 0)
2063 return devid;
2064
2065 iommu = amd_iommu_rlookup_table[devid];
2066
2067 ret = iommu_init_device(dev);
2068 if (ret) {
2069 if (ret != -ENOTSUPP)
2070 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2071 dev_name(dev));
2072
2073 iommu_ignore_device(dev);
2074 dev->archdata.dma_ops = &nommu_dma_ops;
2075 goto out;
2076 }
2077 init_iommu_group(dev);
2078
2079 dev_data = get_dev_data(dev);
2080
2081 BUG_ON(!dev_data);
2082
2083 if (iommu_pass_through || dev_data->iommu_v2)
2084 iommu_request_dm_for_dev(dev);
2085
2086 /* Domains are initialized for this device - have a look what we ended up with */
2087 domain = iommu_get_domain_for_dev(dev);
2088 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2089 dev_data->passthrough = true;
2090 else
2091 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2092
2093 out:
2094 iommu_completion_wait(iommu);
2095
2096 return 0;
2097 }
2098
2099 static void amd_iommu_remove_device(struct device *dev)
2100 {
2101 struct amd_iommu *iommu;
2102 int devid;
2103
2104 if (!check_device(dev))
2105 return;
2106
2107 devid = get_device_id(dev);
2108 if (devid < 0)
2109 return;
2110
2111 iommu = amd_iommu_rlookup_table[devid];
2112
2113 iommu_uninit_device(dev);
2114 iommu_completion_wait(iommu);
2115 }
2116
2117 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2118 {
2119 if (dev_is_pci(dev))
2120 return pci_device_group(dev);
2121
2122 return acpihid_device_group(dev);
2123 }
2124
2125 /*****************************************************************************
2126 *
2127 * The next functions belong to the dma_ops mapping/unmapping code.
2128 *
2129 *****************************************************************************/
2130
2131 static void __queue_flush(struct flush_queue *queue)
2132 {
2133 struct protection_domain *domain;
2134 unsigned long flags;
2135 int idx;
2136
2137 /* First flush TLB of all known domains */
2138 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2139 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2140 domain_flush_tlb(domain);
2141 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2142
2143 /* Wait until flushes have completed */
2144 domain_flush_complete(NULL);
2145
2146 for (idx = 0; idx < queue->next; ++idx) {
2147 struct flush_queue_entry *entry;
2148
2149 entry = queue->entries + idx;
2150
2151 free_iova_fast(&entry->dma_dom->iovad,
2152 entry->iova_pfn,
2153 entry->pages);
2154
2155 /* Not really necessary, just to make sure we catch any bugs */
2156 entry->dma_dom = NULL;
2157 }
2158
2159 queue->next = 0;
2160 }
2161
2162 static void queue_flush_all(void)
2163 {
2164 int cpu;
2165
2166 for_each_possible_cpu(cpu) {
2167 struct flush_queue *queue;
2168 unsigned long flags;
2169
2170 queue = per_cpu_ptr(&flush_queue, cpu);
2171 spin_lock_irqsave(&queue->lock, flags);
2172 if (queue->next > 0)
2173 __queue_flush(queue);
2174 spin_unlock_irqrestore(&queue->lock, flags);
2175 }
2176 }
2177
2178 static void queue_flush_timeout(unsigned long unsused)
2179 {
2180 atomic_set(&queue_timer_on, 0);
2181 queue_flush_all();
2182 }
2183
2184 static void queue_add(struct dma_ops_domain *dma_dom,
2185 unsigned long address, unsigned long pages)
2186 {
2187 struct flush_queue_entry *entry;
2188 struct flush_queue *queue;
2189 unsigned long flags;
2190 int idx;
2191
2192 pages = __roundup_pow_of_two(pages);
2193 address >>= PAGE_SHIFT;
2194
2195 queue = get_cpu_ptr(&flush_queue);
2196 spin_lock_irqsave(&queue->lock, flags);
2197
2198 if (queue->next == FLUSH_QUEUE_SIZE)
2199 __queue_flush(queue);
2200
2201 idx = queue->next++;
2202 entry = queue->entries + idx;
2203
2204 entry->iova_pfn = address;
2205 entry->pages = pages;
2206 entry->dma_dom = dma_dom;
2207
2208 spin_unlock_irqrestore(&queue->lock, flags);
2209
2210 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2211 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2212
2213 put_cpu_ptr(&flush_queue);
2214 }
2215
2216
2217 /*
2218 * In the dma_ops path we only have the struct device. This function
2219 * finds the corresponding IOMMU, the protection domain and the
2220 * requestor id for a given device.
2221 * If the device is not yet associated with a domain this is also done
2222 * in this function.
2223 */
2224 static struct protection_domain *get_domain(struct device *dev)
2225 {
2226 struct protection_domain *domain;
2227
2228 if (!check_device(dev))
2229 return ERR_PTR(-EINVAL);
2230
2231 domain = get_dev_data(dev)->domain;
2232 if (!dma_ops_domain(domain))
2233 return ERR_PTR(-EBUSY);
2234
2235 return domain;
2236 }
2237
2238 static void update_device_table(struct protection_domain *domain)
2239 {
2240 struct iommu_dev_data *dev_data;
2241
2242 list_for_each_entry(dev_data, &domain->dev_list, list) {
2243 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2244
2245 if (dev_data->devid == dev_data->alias)
2246 continue;
2247
2248 /* There is an alias, update device table entry for it */
2249 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2250 }
2251 }
2252
2253 static void update_domain(struct protection_domain *domain)
2254 {
2255 if (!domain->updated)
2256 return;
2257
2258 update_device_table(domain);
2259
2260 domain_flush_devices(domain);
2261 domain_flush_tlb_pde(domain);
2262
2263 domain->updated = false;
2264 }
2265
2266 static int dir2prot(enum dma_data_direction direction)
2267 {
2268 if (direction == DMA_TO_DEVICE)
2269 return IOMMU_PROT_IR;
2270 else if (direction == DMA_FROM_DEVICE)
2271 return IOMMU_PROT_IW;
2272 else if (direction == DMA_BIDIRECTIONAL)
2273 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2274 else
2275 return 0;
2276 }
2277 /*
2278 * This function contains common code for mapping of a physically
2279 * contiguous memory region into DMA address space. It is used by all
2280 * mapping functions provided with this IOMMU driver.
2281 * Must be called with the domain lock held.
2282 */
2283 static dma_addr_t __map_single(struct device *dev,
2284 struct dma_ops_domain *dma_dom,
2285 phys_addr_t paddr,
2286 size_t size,
2287 enum dma_data_direction direction,
2288 u64 dma_mask)
2289 {
2290 dma_addr_t offset = paddr & ~PAGE_MASK;
2291 dma_addr_t address, start, ret;
2292 unsigned int pages;
2293 int prot = 0;
2294 int i;
2295
2296 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2297 paddr &= PAGE_MASK;
2298
2299 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2300 if (address == DMA_ERROR_CODE)
2301 goto out;
2302
2303 prot = dir2prot(direction);
2304
2305 start = address;
2306 for (i = 0; i < pages; ++i) {
2307 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2308 PAGE_SIZE, prot, GFP_ATOMIC);
2309 if (ret)
2310 goto out_unmap;
2311
2312 paddr += PAGE_SIZE;
2313 start += PAGE_SIZE;
2314 }
2315 address += offset;
2316
2317 if (unlikely(amd_iommu_np_cache)) {
2318 domain_flush_pages(&dma_dom->domain, address, size);
2319 domain_flush_complete(&dma_dom->domain);
2320 }
2321
2322 out:
2323 return address;
2324
2325 out_unmap:
2326
2327 for (--i; i >= 0; --i) {
2328 start -= PAGE_SIZE;
2329 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2330 }
2331
2332 domain_flush_tlb(&dma_dom->domain);
2333 domain_flush_complete(&dma_dom->domain);
2334
2335 dma_ops_free_iova(dma_dom, address, pages);
2336
2337 return DMA_ERROR_CODE;
2338 }
2339
2340 /*
2341 * Does the reverse of the __map_single function. Must be called with
2342 * the domain lock held too
2343 */
2344 static void __unmap_single(struct dma_ops_domain *dma_dom,
2345 dma_addr_t dma_addr,
2346 size_t size,
2347 int dir)
2348 {
2349 dma_addr_t flush_addr;
2350 dma_addr_t i, start;
2351 unsigned int pages;
2352
2353 flush_addr = dma_addr;
2354 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2355 dma_addr &= PAGE_MASK;
2356 start = dma_addr;
2357
2358 for (i = 0; i < pages; ++i) {
2359 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2360 start += PAGE_SIZE;
2361 }
2362
2363 if (amd_iommu_unmap_flush) {
2364 dma_ops_free_iova(dma_dom, dma_addr, pages);
2365 domain_flush_tlb(&dma_dom->domain);
2366 domain_flush_complete(&dma_dom->domain);
2367 } else {
2368 queue_add(dma_dom, dma_addr, pages);
2369 }
2370 }
2371
2372 /*
2373 * The exported map_single function for dma_ops.
2374 */
2375 static dma_addr_t map_page(struct device *dev, struct page *page,
2376 unsigned long offset, size_t size,
2377 enum dma_data_direction dir,
2378 unsigned long attrs)
2379 {
2380 phys_addr_t paddr = page_to_phys(page) + offset;
2381 struct protection_domain *domain;
2382 struct dma_ops_domain *dma_dom;
2383 u64 dma_mask;
2384
2385 domain = get_domain(dev);
2386 if (PTR_ERR(domain) == -EINVAL)
2387 return (dma_addr_t)paddr;
2388 else if (IS_ERR(domain))
2389 return DMA_ERROR_CODE;
2390
2391 dma_mask = *dev->dma_mask;
2392 dma_dom = to_dma_ops_domain(domain);
2393
2394 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2395 }
2396
2397 /*
2398 * The exported unmap_single function for dma_ops.
2399 */
2400 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2401 enum dma_data_direction dir, unsigned long attrs)
2402 {
2403 struct protection_domain *domain;
2404 struct dma_ops_domain *dma_dom;
2405
2406 domain = get_domain(dev);
2407 if (IS_ERR(domain))
2408 return;
2409
2410 dma_dom = to_dma_ops_domain(domain);
2411
2412 __unmap_single(dma_dom, dma_addr, size, dir);
2413 }
2414
2415 static int sg_num_pages(struct device *dev,
2416 struct scatterlist *sglist,
2417 int nelems)
2418 {
2419 unsigned long mask, boundary_size;
2420 struct scatterlist *s;
2421 int i, npages = 0;
2422
2423 mask = dma_get_seg_boundary(dev);
2424 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2425 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2426
2427 for_each_sg(sglist, s, nelems, i) {
2428 int p, n;
2429
2430 s->dma_address = npages << PAGE_SHIFT;
2431 p = npages % boundary_size;
2432 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2433 if (p + n > boundary_size)
2434 npages += boundary_size - p;
2435 npages += n;
2436 }
2437
2438 return npages;
2439 }
2440
2441 /*
2442 * The exported map_sg function for dma_ops (handles scatter-gather
2443 * lists).
2444 */
2445 static int map_sg(struct device *dev, struct scatterlist *sglist,
2446 int nelems, enum dma_data_direction direction,
2447 unsigned long attrs)
2448 {
2449 int mapped_pages = 0, npages = 0, prot = 0, i;
2450 struct protection_domain *domain;
2451 struct dma_ops_domain *dma_dom;
2452 struct scatterlist *s;
2453 unsigned long address;
2454 u64 dma_mask;
2455
2456 domain = get_domain(dev);
2457 if (IS_ERR(domain))
2458 return 0;
2459
2460 dma_dom = to_dma_ops_domain(domain);
2461 dma_mask = *dev->dma_mask;
2462
2463 npages = sg_num_pages(dev, sglist, nelems);
2464
2465 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2466 if (address == DMA_ERROR_CODE)
2467 goto out_err;
2468
2469 prot = dir2prot(direction);
2470
2471 /* Map all sg entries */
2472 for_each_sg(sglist, s, nelems, i) {
2473 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2474
2475 for (j = 0; j < pages; ++j) {
2476 unsigned long bus_addr, phys_addr;
2477 int ret;
2478
2479 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2480 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2481 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2482 if (ret)
2483 goto out_unmap;
2484
2485 mapped_pages += 1;
2486 }
2487 }
2488
2489 /* Everything is mapped - write the right values into s->dma_address */
2490 for_each_sg(sglist, s, nelems, i) {
2491 s->dma_address += address + s->offset;
2492 s->dma_length = s->length;
2493 }
2494
2495 return nelems;
2496
2497 out_unmap:
2498 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2499 dev_name(dev), npages);
2500
2501 for_each_sg(sglist, s, nelems, i) {
2502 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2503
2504 for (j = 0; j < pages; ++j) {
2505 unsigned long bus_addr;
2506
2507 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2508 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2509
2510 if (--mapped_pages)
2511 goto out_free_iova;
2512 }
2513 }
2514
2515 out_free_iova:
2516 free_iova_fast(&dma_dom->iovad, address, npages);
2517
2518 out_err:
2519 return 0;
2520 }
2521
2522 /*
2523 * The exported map_sg function for dma_ops (handles scatter-gather
2524 * lists).
2525 */
2526 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2527 int nelems, enum dma_data_direction dir,
2528 unsigned long attrs)
2529 {
2530 struct protection_domain *domain;
2531 struct dma_ops_domain *dma_dom;
2532 unsigned long startaddr;
2533 int npages = 2;
2534
2535 domain = get_domain(dev);
2536 if (IS_ERR(domain))
2537 return;
2538
2539 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2540 dma_dom = to_dma_ops_domain(domain);
2541 npages = sg_num_pages(dev, sglist, nelems);
2542
2543 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2544 }
2545
2546 /*
2547 * The exported alloc_coherent function for dma_ops.
2548 */
2549 static void *alloc_coherent(struct device *dev, size_t size,
2550 dma_addr_t *dma_addr, gfp_t flag,
2551 unsigned long attrs)
2552 {
2553 u64 dma_mask = dev->coherent_dma_mask;
2554 struct protection_domain *domain;
2555 struct dma_ops_domain *dma_dom;
2556 struct page *page;
2557
2558 domain = get_domain(dev);
2559 if (PTR_ERR(domain) == -EINVAL) {
2560 page = alloc_pages(flag, get_order(size));
2561 *dma_addr = page_to_phys(page);
2562 return page_address(page);
2563 } else if (IS_ERR(domain))
2564 return NULL;
2565
2566 dma_dom = to_dma_ops_domain(domain);
2567 size = PAGE_ALIGN(size);
2568 dma_mask = dev->coherent_dma_mask;
2569 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2570 flag |= __GFP_ZERO;
2571
2572 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2573 if (!page) {
2574 if (!gfpflags_allow_blocking(flag))
2575 return NULL;
2576
2577 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2578 get_order(size));
2579 if (!page)
2580 return NULL;
2581 }
2582
2583 if (!dma_mask)
2584 dma_mask = *dev->dma_mask;
2585
2586 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2587 size, DMA_BIDIRECTIONAL, dma_mask);
2588
2589 if (*dma_addr == DMA_ERROR_CODE)
2590 goto out_free;
2591
2592 return page_address(page);
2593
2594 out_free:
2595
2596 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2597 __free_pages(page, get_order(size));
2598
2599 return NULL;
2600 }
2601
2602 /*
2603 * The exported free_coherent function for dma_ops.
2604 */
2605 static void free_coherent(struct device *dev, size_t size,
2606 void *virt_addr, dma_addr_t dma_addr,
2607 unsigned long attrs)
2608 {
2609 struct protection_domain *domain;
2610 struct dma_ops_domain *dma_dom;
2611 struct page *page;
2612
2613 page = virt_to_page(virt_addr);
2614 size = PAGE_ALIGN(size);
2615
2616 domain = get_domain(dev);
2617 if (IS_ERR(domain))
2618 goto free_mem;
2619
2620 dma_dom = to_dma_ops_domain(domain);
2621
2622 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2623
2624 free_mem:
2625 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2626 __free_pages(page, get_order(size));
2627 }
2628
2629 /*
2630 * This function is called by the DMA layer to find out if we can handle a
2631 * particular device. It is part of the dma_ops.
2632 */
2633 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2634 {
2635 return check_device(dev);
2636 }
2637
2638 static struct dma_map_ops amd_iommu_dma_ops = {
2639 .alloc = alloc_coherent,
2640 .free = free_coherent,
2641 .map_page = map_page,
2642 .unmap_page = unmap_page,
2643 .map_sg = map_sg,
2644 .unmap_sg = unmap_sg,
2645 .dma_supported = amd_iommu_dma_supported,
2646 };
2647
2648 static int init_reserved_iova_ranges(void)
2649 {
2650 struct pci_dev *pdev = NULL;
2651 struct iova *val;
2652
2653 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2654 IOVA_START_PFN, DMA_32BIT_PFN);
2655
2656 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2657 &reserved_rbtree_key);
2658
2659 /* MSI memory range */
2660 val = reserve_iova(&reserved_iova_ranges,
2661 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2662 if (!val) {
2663 pr_err("Reserving MSI range failed\n");
2664 return -ENOMEM;
2665 }
2666
2667 /* HT memory range */
2668 val = reserve_iova(&reserved_iova_ranges,
2669 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2670 if (!val) {
2671 pr_err("Reserving HT range failed\n");
2672 return -ENOMEM;
2673 }
2674
2675 /*
2676 * Memory used for PCI resources
2677 * FIXME: Check whether we can reserve the PCI-hole completly
2678 */
2679 for_each_pci_dev(pdev) {
2680 int i;
2681
2682 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2683 struct resource *r = &pdev->resource[i];
2684
2685 if (!(r->flags & IORESOURCE_MEM))
2686 continue;
2687
2688 val = reserve_iova(&reserved_iova_ranges,
2689 IOVA_PFN(r->start),
2690 IOVA_PFN(r->end));
2691 if (!val) {
2692 pr_err("Reserve pci-resource range failed\n");
2693 return -ENOMEM;
2694 }
2695 }
2696 }
2697
2698 return 0;
2699 }
2700
2701 int __init amd_iommu_init_api(void)
2702 {
2703 int ret, cpu, err = 0;
2704
2705 ret = iova_cache_get();
2706 if (ret)
2707 return ret;
2708
2709 ret = init_reserved_iova_ranges();
2710 if (ret)
2711 return ret;
2712
2713 for_each_possible_cpu(cpu) {
2714 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2715
2716 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2717 sizeof(*queue->entries),
2718 GFP_KERNEL);
2719 if (!queue->entries)
2720 goto out_put_iova;
2721
2722 spin_lock_init(&queue->lock);
2723 }
2724
2725 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2726 if (err)
2727 return err;
2728 #ifdef CONFIG_ARM_AMBA
2729 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2730 if (err)
2731 return err;
2732 #endif
2733 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2734 if (err)
2735 return err;
2736 return 0;
2737
2738 out_put_iova:
2739 for_each_possible_cpu(cpu) {
2740 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2741
2742 kfree(queue->entries);
2743 }
2744
2745 return -ENOMEM;
2746 }
2747
2748 int __init amd_iommu_init_dma_ops(void)
2749 {
2750 setup_timer(&queue_timer, queue_flush_timeout, 0);
2751 atomic_set(&queue_timer_on, 0);
2752
2753 swiotlb = iommu_pass_through ? 1 : 0;
2754 iommu_detected = 1;
2755
2756 /*
2757 * In case we don't initialize SWIOTLB (actually the common case
2758 * when AMD IOMMU is enabled), make sure there are global
2759 * dma_ops set as a fall-back for devices not handled by this
2760 * driver (for example non-PCI devices).
2761 */
2762 if (!swiotlb)
2763 dma_ops = &nommu_dma_ops;
2764
2765 if (amd_iommu_unmap_flush)
2766 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2767 else
2768 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2769
2770 return 0;
2771
2772 }
2773
2774 /*****************************************************************************
2775 *
2776 * The following functions belong to the exported interface of AMD IOMMU
2777 *
2778 * This interface allows access to lower level functions of the IOMMU
2779 * like protection domain handling and assignement of devices to domains
2780 * which is not possible with the dma_ops interface.
2781 *
2782 *****************************************************************************/
2783
2784 static void cleanup_domain(struct protection_domain *domain)
2785 {
2786 struct iommu_dev_data *entry;
2787 unsigned long flags;
2788
2789 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2790
2791 while (!list_empty(&domain->dev_list)) {
2792 entry = list_first_entry(&domain->dev_list,
2793 struct iommu_dev_data, list);
2794 __detach_device(entry);
2795 }
2796
2797 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2798 }
2799
2800 static void protection_domain_free(struct protection_domain *domain)
2801 {
2802 if (!domain)
2803 return;
2804
2805 del_domain_from_list(domain);
2806
2807 if (domain->id)
2808 domain_id_free(domain->id);
2809
2810 kfree(domain);
2811 }
2812
2813 static int protection_domain_init(struct protection_domain *domain)
2814 {
2815 spin_lock_init(&domain->lock);
2816 mutex_init(&domain->api_lock);
2817 domain->id = domain_id_alloc();
2818 if (!domain->id)
2819 return -ENOMEM;
2820 INIT_LIST_HEAD(&domain->dev_list);
2821
2822 return 0;
2823 }
2824
2825 static struct protection_domain *protection_domain_alloc(void)
2826 {
2827 struct protection_domain *domain;
2828
2829 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2830 if (!domain)
2831 return NULL;
2832
2833 if (protection_domain_init(domain))
2834 goto out_err;
2835
2836 add_domain_to_list(domain);
2837
2838 return domain;
2839
2840 out_err:
2841 kfree(domain);
2842
2843 return NULL;
2844 }
2845
2846 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2847 {
2848 struct protection_domain *pdomain;
2849 struct dma_ops_domain *dma_domain;
2850
2851 switch (type) {
2852 case IOMMU_DOMAIN_UNMANAGED:
2853 pdomain = protection_domain_alloc();
2854 if (!pdomain)
2855 return NULL;
2856
2857 pdomain->mode = PAGE_MODE_3_LEVEL;
2858 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2859 if (!pdomain->pt_root) {
2860 protection_domain_free(pdomain);
2861 return NULL;
2862 }
2863
2864 pdomain->domain.geometry.aperture_start = 0;
2865 pdomain->domain.geometry.aperture_end = ~0ULL;
2866 pdomain->domain.geometry.force_aperture = true;
2867
2868 break;
2869 case IOMMU_DOMAIN_DMA:
2870 dma_domain = dma_ops_domain_alloc();
2871 if (!dma_domain) {
2872 pr_err("AMD-Vi: Failed to allocate\n");
2873 return NULL;
2874 }
2875 pdomain = &dma_domain->domain;
2876 break;
2877 case IOMMU_DOMAIN_IDENTITY:
2878 pdomain = protection_domain_alloc();
2879 if (!pdomain)
2880 return NULL;
2881
2882 pdomain->mode = PAGE_MODE_NONE;
2883 break;
2884 default:
2885 return NULL;
2886 }
2887
2888 return &pdomain->domain;
2889 }
2890
2891 static void amd_iommu_domain_free(struct iommu_domain *dom)
2892 {
2893 struct protection_domain *domain;
2894 struct dma_ops_domain *dma_dom;
2895
2896 domain = to_pdomain(dom);
2897
2898 if (domain->dev_cnt > 0)
2899 cleanup_domain(domain);
2900
2901 BUG_ON(domain->dev_cnt != 0);
2902
2903 if (!dom)
2904 return;
2905
2906 switch (dom->type) {
2907 case IOMMU_DOMAIN_DMA:
2908 /*
2909 * First make sure the domain is no longer referenced from the
2910 * flush queue
2911 */
2912 queue_flush_all();
2913
2914 /* Now release the domain */
2915 dma_dom = to_dma_ops_domain(domain);
2916 dma_ops_domain_free(dma_dom);
2917 break;
2918 default:
2919 if (domain->mode != PAGE_MODE_NONE)
2920 free_pagetable(domain);
2921
2922 if (domain->flags & PD_IOMMUV2_MASK)
2923 free_gcr3_table(domain);
2924
2925 protection_domain_free(domain);
2926 break;
2927 }
2928 }
2929
2930 static void amd_iommu_detach_device(struct iommu_domain *dom,
2931 struct device *dev)
2932 {
2933 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2934 struct amd_iommu *iommu;
2935 int devid;
2936
2937 if (!check_device(dev))
2938 return;
2939
2940 devid = get_device_id(dev);
2941 if (devid < 0)
2942 return;
2943
2944 if (dev_data->domain != NULL)
2945 detach_device(dev);
2946
2947 iommu = amd_iommu_rlookup_table[devid];
2948 if (!iommu)
2949 return;
2950
2951 iommu_completion_wait(iommu);
2952 }
2953
2954 static int amd_iommu_attach_device(struct iommu_domain *dom,
2955 struct device *dev)
2956 {
2957 struct protection_domain *domain = to_pdomain(dom);
2958 struct iommu_dev_data *dev_data;
2959 struct amd_iommu *iommu;
2960 int ret;
2961
2962 if (!check_device(dev))
2963 return -EINVAL;
2964
2965 dev_data = dev->archdata.iommu;
2966
2967 iommu = amd_iommu_rlookup_table[dev_data->devid];
2968 if (!iommu)
2969 return -EINVAL;
2970
2971 if (dev_data->domain)
2972 detach_device(dev);
2973
2974 ret = attach_device(dev, domain);
2975
2976 iommu_completion_wait(iommu);
2977
2978 return ret;
2979 }
2980
2981 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2982 phys_addr_t paddr, size_t page_size, int iommu_prot)
2983 {
2984 struct protection_domain *domain = to_pdomain(dom);
2985 int prot = 0;
2986 int ret;
2987
2988 if (domain->mode == PAGE_MODE_NONE)
2989 return -EINVAL;
2990
2991 if (iommu_prot & IOMMU_READ)
2992 prot |= IOMMU_PROT_IR;
2993 if (iommu_prot & IOMMU_WRITE)
2994 prot |= IOMMU_PROT_IW;
2995
2996 mutex_lock(&domain->api_lock);
2997 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
2998 mutex_unlock(&domain->api_lock);
2999
3000 return ret;
3001 }
3002
3003 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3004 size_t page_size)
3005 {
3006 struct protection_domain *domain = to_pdomain(dom);
3007 size_t unmap_size;
3008
3009 if (domain->mode == PAGE_MODE_NONE)
3010 return -EINVAL;
3011
3012 mutex_lock(&domain->api_lock);
3013 unmap_size = iommu_unmap_page(domain, iova, page_size);
3014 mutex_unlock(&domain->api_lock);
3015
3016 domain_flush_tlb_pde(domain);
3017
3018 return unmap_size;
3019 }
3020
3021 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3022 dma_addr_t iova)
3023 {
3024 struct protection_domain *domain = to_pdomain(dom);
3025 unsigned long offset_mask, pte_pgsize;
3026 u64 *pte, __pte;
3027
3028 if (domain->mode == PAGE_MODE_NONE)
3029 return iova;
3030
3031 pte = fetch_pte(domain, iova, &pte_pgsize);
3032
3033 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3034 return 0;
3035
3036 offset_mask = pte_pgsize - 1;
3037 __pte = *pte & PM_ADDR_MASK;
3038
3039 return (__pte & ~offset_mask) | (iova & offset_mask);
3040 }
3041
3042 static bool amd_iommu_capable(enum iommu_cap cap)
3043 {
3044 switch (cap) {
3045 case IOMMU_CAP_CACHE_COHERENCY:
3046 return true;
3047 case IOMMU_CAP_INTR_REMAP:
3048 return (irq_remapping_enabled == 1);
3049 case IOMMU_CAP_NOEXEC:
3050 return false;
3051 }
3052
3053 return false;
3054 }
3055
3056 static void amd_iommu_get_dm_regions(struct device *dev,
3057 struct list_head *head)
3058 {
3059 struct unity_map_entry *entry;
3060 int devid;
3061
3062 devid = get_device_id(dev);
3063 if (devid < 0)
3064 return;
3065
3066 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3067 struct iommu_dm_region *region;
3068
3069 if (devid < entry->devid_start || devid > entry->devid_end)
3070 continue;
3071
3072 region = kzalloc(sizeof(*region), GFP_KERNEL);
3073 if (!region) {
3074 pr_err("Out of memory allocating dm-regions for %s\n",
3075 dev_name(dev));
3076 return;
3077 }
3078
3079 region->start = entry->address_start;
3080 region->length = entry->address_end - entry->address_start;
3081 if (entry->prot & IOMMU_PROT_IR)
3082 region->prot |= IOMMU_READ;
3083 if (entry->prot & IOMMU_PROT_IW)
3084 region->prot |= IOMMU_WRITE;
3085
3086 list_add_tail(&region->list, head);
3087 }
3088 }
3089
3090 static void amd_iommu_put_dm_regions(struct device *dev,
3091 struct list_head *head)
3092 {
3093 struct iommu_dm_region *entry, *next;
3094
3095 list_for_each_entry_safe(entry, next, head, list)
3096 kfree(entry);
3097 }
3098
3099 static void amd_iommu_apply_dm_region(struct device *dev,
3100 struct iommu_domain *domain,
3101 struct iommu_dm_region *region)
3102 {
3103 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3104 unsigned long start, end;
3105
3106 start = IOVA_PFN(region->start);
3107 end = IOVA_PFN(region->start + region->length);
3108
3109 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3110 }
3111
3112 static const struct iommu_ops amd_iommu_ops = {
3113 .capable = amd_iommu_capable,
3114 .domain_alloc = amd_iommu_domain_alloc,
3115 .domain_free = amd_iommu_domain_free,
3116 .attach_dev = amd_iommu_attach_device,
3117 .detach_dev = amd_iommu_detach_device,
3118 .map = amd_iommu_map,
3119 .unmap = amd_iommu_unmap,
3120 .map_sg = default_iommu_map_sg,
3121 .iova_to_phys = amd_iommu_iova_to_phys,
3122 .add_device = amd_iommu_add_device,
3123 .remove_device = amd_iommu_remove_device,
3124 .device_group = amd_iommu_device_group,
3125 .get_dm_regions = amd_iommu_get_dm_regions,
3126 .put_dm_regions = amd_iommu_put_dm_regions,
3127 .apply_dm_region = amd_iommu_apply_dm_region,
3128 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3129 };
3130
3131 /*****************************************************************************
3132 *
3133 * The next functions do a basic initialization of IOMMU for pass through
3134 * mode
3135 *
3136 * In passthrough mode the IOMMU is initialized and enabled but not used for
3137 * DMA-API translation.
3138 *
3139 *****************************************************************************/
3140
3141 /* IOMMUv2 specific functions */
3142 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3143 {
3144 return atomic_notifier_chain_register(&ppr_notifier, nb);
3145 }
3146 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3147
3148 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3149 {
3150 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3151 }
3152 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3153
3154 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3155 {
3156 struct protection_domain *domain = to_pdomain(dom);
3157 unsigned long flags;
3158
3159 spin_lock_irqsave(&domain->lock, flags);
3160
3161 /* Update data structure */
3162 domain->mode = PAGE_MODE_NONE;
3163 domain->updated = true;
3164
3165 /* Make changes visible to IOMMUs */
3166 update_domain(domain);
3167
3168 /* Page-table is not visible to IOMMU anymore, so free it */
3169 free_pagetable(domain);
3170
3171 spin_unlock_irqrestore(&domain->lock, flags);
3172 }
3173 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3174
3175 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3176 {
3177 struct protection_domain *domain = to_pdomain(dom);
3178 unsigned long flags;
3179 int levels, ret;
3180
3181 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3182 return -EINVAL;
3183
3184 /* Number of GCR3 table levels required */
3185 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3186 levels += 1;
3187
3188 if (levels > amd_iommu_max_glx_val)
3189 return -EINVAL;
3190
3191 spin_lock_irqsave(&domain->lock, flags);
3192
3193 /*
3194 * Save us all sanity checks whether devices already in the
3195 * domain support IOMMUv2. Just force that the domain has no
3196 * devices attached when it is switched into IOMMUv2 mode.
3197 */
3198 ret = -EBUSY;
3199 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3200 goto out;
3201
3202 ret = -ENOMEM;
3203 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3204 if (domain->gcr3_tbl == NULL)
3205 goto out;
3206
3207 domain->glx = levels;
3208 domain->flags |= PD_IOMMUV2_MASK;
3209 domain->updated = true;
3210
3211 update_domain(domain);
3212
3213 ret = 0;
3214
3215 out:
3216 spin_unlock_irqrestore(&domain->lock, flags);
3217
3218 return ret;
3219 }
3220 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3221
3222 static int __flush_pasid(struct protection_domain *domain, int pasid,
3223 u64 address, bool size)
3224 {
3225 struct iommu_dev_data *dev_data;
3226 struct iommu_cmd cmd;
3227 int i, ret;
3228
3229 if (!(domain->flags & PD_IOMMUV2_MASK))
3230 return -EINVAL;
3231
3232 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3233
3234 /*
3235 * IOMMU TLB needs to be flushed before Device TLB to
3236 * prevent device TLB refill from IOMMU TLB
3237 */
3238 for (i = 0; i < amd_iommus_present; ++i) {
3239 if (domain->dev_iommu[i] == 0)
3240 continue;
3241
3242 ret = iommu_queue_command(amd_iommus[i], &cmd);
3243 if (ret != 0)
3244 goto out;
3245 }
3246
3247 /* Wait until IOMMU TLB flushes are complete */
3248 domain_flush_complete(domain);
3249
3250 /* Now flush device TLBs */
3251 list_for_each_entry(dev_data, &domain->dev_list, list) {
3252 struct amd_iommu *iommu;
3253 int qdep;
3254
3255 /*
3256 There might be non-IOMMUv2 capable devices in an IOMMUv2
3257 * domain.
3258 */
3259 if (!dev_data->ats.enabled)
3260 continue;
3261
3262 qdep = dev_data->ats.qdep;
3263 iommu = amd_iommu_rlookup_table[dev_data->devid];
3264
3265 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3266 qdep, address, size);
3267
3268 ret = iommu_queue_command(iommu, &cmd);
3269 if (ret != 0)
3270 goto out;
3271 }
3272
3273 /* Wait until all device TLBs are flushed */
3274 domain_flush_complete(domain);
3275
3276 ret = 0;
3277
3278 out:
3279
3280 return ret;
3281 }
3282
3283 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3284 u64 address)
3285 {
3286 return __flush_pasid(domain, pasid, address, false);
3287 }
3288
3289 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3290 u64 address)
3291 {
3292 struct protection_domain *domain = to_pdomain(dom);
3293 unsigned long flags;
3294 int ret;
3295
3296 spin_lock_irqsave(&domain->lock, flags);
3297 ret = __amd_iommu_flush_page(domain, pasid, address);
3298 spin_unlock_irqrestore(&domain->lock, flags);
3299
3300 return ret;
3301 }
3302 EXPORT_SYMBOL(amd_iommu_flush_page);
3303
3304 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3305 {
3306 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3307 true);
3308 }
3309
3310 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3311 {
3312 struct protection_domain *domain = to_pdomain(dom);
3313 unsigned long flags;
3314 int ret;
3315
3316 spin_lock_irqsave(&domain->lock, flags);
3317 ret = __amd_iommu_flush_tlb(domain, pasid);
3318 spin_unlock_irqrestore(&domain->lock, flags);
3319
3320 return ret;
3321 }
3322 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3323
3324 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3325 {
3326 int index;
3327 u64 *pte;
3328
3329 while (true) {
3330
3331 index = (pasid >> (9 * level)) & 0x1ff;
3332 pte = &root[index];
3333
3334 if (level == 0)
3335 break;
3336
3337 if (!(*pte & GCR3_VALID)) {
3338 if (!alloc)
3339 return NULL;
3340
3341 root = (void *)get_zeroed_page(GFP_ATOMIC);
3342 if (root == NULL)
3343 return NULL;
3344
3345 *pte = __pa(root) | GCR3_VALID;
3346 }
3347
3348 root = __va(*pte & PAGE_MASK);
3349
3350 level -= 1;
3351 }
3352
3353 return pte;
3354 }
3355
3356 static int __set_gcr3(struct protection_domain *domain, int pasid,
3357 unsigned long cr3)
3358 {
3359 u64 *pte;
3360
3361 if (domain->mode != PAGE_MODE_NONE)
3362 return -EINVAL;
3363
3364 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3365 if (pte == NULL)
3366 return -ENOMEM;
3367
3368 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3369
3370 return __amd_iommu_flush_tlb(domain, pasid);
3371 }
3372
3373 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3374 {
3375 u64 *pte;
3376
3377 if (domain->mode != PAGE_MODE_NONE)
3378 return -EINVAL;
3379
3380 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3381 if (pte == NULL)
3382 return 0;
3383
3384 *pte = 0;
3385
3386 return __amd_iommu_flush_tlb(domain, pasid);
3387 }
3388
3389 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3390 unsigned long cr3)
3391 {
3392 struct protection_domain *domain = to_pdomain(dom);
3393 unsigned long flags;
3394 int ret;
3395
3396 spin_lock_irqsave(&domain->lock, flags);
3397 ret = __set_gcr3(domain, pasid, cr3);
3398 spin_unlock_irqrestore(&domain->lock, flags);
3399
3400 return ret;
3401 }
3402 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3403
3404 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3405 {
3406 struct protection_domain *domain = to_pdomain(dom);
3407 unsigned long flags;
3408 int ret;
3409
3410 spin_lock_irqsave(&domain->lock, flags);
3411 ret = __clear_gcr3(domain, pasid);
3412 spin_unlock_irqrestore(&domain->lock, flags);
3413
3414 return ret;
3415 }
3416 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3417
3418 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3419 int status, int tag)
3420 {
3421 struct iommu_dev_data *dev_data;
3422 struct amd_iommu *iommu;
3423 struct iommu_cmd cmd;
3424
3425 dev_data = get_dev_data(&pdev->dev);
3426 iommu = amd_iommu_rlookup_table[dev_data->devid];
3427
3428 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3429 tag, dev_data->pri_tlp);
3430
3431 return iommu_queue_command(iommu, &cmd);
3432 }
3433 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3434
3435 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3436 {
3437 struct protection_domain *pdomain;
3438
3439 pdomain = get_domain(&pdev->dev);
3440 if (IS_ERR(pdomain))
3441 return NULL;
3442
3443 /* Only return IOMMUv2 domains */
3444 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3445 return NULL;
3446
3447 return &pdomain->domain;
3448 }
3449 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3450
3451 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3452 {
3453 struct iommu_dev_data *dev_data;
3454
3455 if (!amd_iommu_v2_supported())
3456 return;
3457
3458 dev_data = get_dev_data(&pdev->dev);
3459 dev_data->errata |= (1 << erratum);
3460 }
3461 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3462
3463 int amd_iommu_device_info(struct pci_dev *pdev,
3464 struct amd_iommu_device_info *info)
3465 {
3466 int max_pasids;
3467 int pos;
3468
3469 if (pdev == NULL || info == NULL)
3470 return -EINVAL;
3471
3472 if (!amd_iommu_v2_supported())
3473 return -EINVAL;
3474
3475 memset(info, 0, sizeof(*info));
3476
3477 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3478 if (pos)
3479 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3480
3481 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3482 if (pos)
3483 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3484
3485 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3486 if (pos) {
3487 int features;
3488
3489 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3490 max_pasids = min(max_pasids, (1 << 20));
3491
3492 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3493 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3494
3495 features = pci_pasid_features(pdev);
3496 if (features & PCI_PASID_CAP_EXEC)
3497 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3498 if (features & PCI_PASID_CAP_PRIV)
3499 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3500 }
3501
3502 return 0;
3503 }
3504 EXPORT_SYMBOL(amd_iommu_device_info);
3505
3506 #ifdef CONFIG_IRQ_REMAP
3507
3508 /*****************************************************************************
3509 *
3510 * Interrupt Remapping Implementation
3511 *
3512 *****************************************************************************/
3513
3514 union irte {
3515 u32 val;
3516 struct {
3517 u32 valid : 1,
3518 no_fault : 1,
3519 int_type : 3,
3520 rq_eoi : 1,
3521 dm : 1,
3522 rsvd_1 : 1,
3523 destination : 8,
3524 vector : 8,
3525 rsvd_2 : 8;
3526 } fields;
3527 };
3528
3529 struct irq_2_irte {
3530 u16 devid; /* Device ID for IRTE table */
3531 u16 index; /* Index into IRTE table*/
3532 };
3533
3534 struct amd_ir_data {
3535 struct irq_2_irte irq_2_irte;
3536 union irte irte_entry;
3537 union {
3538 struct msi_msg msi_entry;
3539 };
3540 };
3541
3542 static struct irq_chip amd_ir_chip;
3543
3544 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3545 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3546 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3547 #define DTE_IRQ_REMAP_ENABLE 1ULL
3548
3549 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3550 {
3551 u64 dte;
3552
3553 dte = amd_iommu_dev_table[devid].data[2];
3554 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3555 dte |= virt_to_phys(table->table);
3556 dte |= DTE_IRQ_REMAP_INTCTL;
3557 dte |= DTE_IRQ_TABLE_LEN;
3558 dte |= DTE_IRQ_REMAP_ENABLE;
3559
3560 amd_iommu_dev_table[devid].data[2] = dte;
3561 }
3562
3563 #define IRTE_ALLOCATED (~1U)
3564
3565 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3566 {
3567 struct irq_remap_table *table = NULL;
3568 struct amd_iommu *iommu;
3569 unsigned long flags;
3570 u16 alias;
3571
3572 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3573
3574 iommu = amd_iommu_rlookup_table[devid];
3575 if (!iommu)
3576 goto out_unlock;
3577
3578 table = irq_lookup_table[devid];
3579 if (table)
3580 goto out;
3581
3582 alias = amd_iommu_alias_table[devid];
3583 table = irq_lookup_table[alias];
3584 if (table) {
3585 irq_lookup_table[devid] = table;
3586 set_dte_irq_entry(devid, table);
3587 iommu_flush_dte(iommu, devid);
3588 goto out;
3589 }
3590
3591 /* Nothing there yet, allocate new irq remapping table */
3592 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3593 if (!table)
3594 goto out;
3595
3596 /* Initialize table spin-lock */
3597 spin_lock_init(&table->lock);
3598
3599 if (ioapic)
3600 /* Keep the first 32 indexes free for IOAPIC interrupts */
3601 table->min_index = 32;
3602
3603 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3604 if (!table->table) {
3605 kfree(table);
3606 table = NULL;
3607 goto out;
3608 }
3609
3610 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3611
3612 if (ioapic) {
3613 int i;
3614
3615 for (i = 0; i < 32; ++i)
3616 table->table[i] = IRTE_ALLOCATED;
3617 }
3618
3619 irq_lookup_table[devid] = table;
3620 set_dte_irq_entry(devid, table);
3621 iommu_flush_dte(iommu, devid);
3622 if (devid != alias) {
3623 irq_lookup_table[alias] = table;
3624 set_dte_irq_entry(alias, table);
3625 iommu_flush_dte(iommu, alias);
3626 }
3627
3628 out:
3629 iommu_completion_wait(iommu);
3630
3631 out_unlock:
3632 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3633
3634 return table;
3635 }
3636
3637 static int alloc_irq_index(u16 devid, int count)
3638 {
3639 struct irq_remap_table *table;
3640 unsigned long flags;
3641 int index, c;
3642
3643 table = get_irq_table(devid, false);
3644 if (!table)
3645 return -ENODEV;
3646
3647 spin_lock_irqsave(&table->lock, flags);
3648
3649 /* Scan table for free entries */
3650 for (c = 0, index = table->min_index;
3651 index < MAX_IRQS_PER_TABLE;
3652 ++index) {
3653 if (table->table[index] == 0)
3654 c += 1;
3655 else
3656 c = 0;
3657
3658 if (c == count) {
3659 for (; c != 0; --c)
3660 table->table[index - c + 1] = IRTE_ALLOCATED;
3661
3662 index -= count - 1;
3663 goto out;
3664 }
3665 }
3666
3667 index = -ENOSPC;
3668
3669 out:
3670 spin_unlock_irqrestore(&table->lock, flags);
3671
3672 return index;
3673 }
3674
3675 static int modify_irte(u16 devid, int index, union irte irte)
3676 {
3677 struct irq_remap_table *table;
3678 struct amd_iommu *iommu;
3679 unsigned long flags;
3680
3681 iommu = amd_iommu_rlookup_table[devid];
3682 if (iommu == NULL)
3683 return -EINVAL;
3684
3685 table = get_irq_table(devid, false);
3686 if (!table)
3687 return -ENOMEM;
3688
3689 spin_lock_irqsave(&table->lock, flags);
3690 table->table[index] = irte.val;
3691 spin_unlock_irqrestore(&table->lock, flags);
3692
3693 iommu_flush_irt(iommu, devid);
3694 iommu_completion_wait(iommu);
3695
3696 return 0;
3697 }
3698
3699 static void free_irte(u16 devid, int index)
3700 {
3701 struct irq_remap_table *table;
3702 struct amd_iommu *iommu;
3703 unsigned long flags;
3704
3705 iommu = amd_iommu_rlookup_table[devid];
3706 if (iommu == NULL)
3707 return;
3708
3709 table = get_irq_table(devid, false);
3710 if (!table)
3711 return;
3712
3713 spin_lock_irqsave(&table->lock, flags);
3714 table->table[index] = 0;
3715 spin_unlock_irqrestore(&table->lock, flags);
3716
3717 iommu_flush_irt(iommu, devid);
3718 iommu_completion_wait(iommu);
3719 }
3720
3721 static int get_devid(struct irq_alloc_info *info)
3722 {
3723 int devid = -1;
3724
3725 switch (info->type) {
3726 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3727 devid = get_ioapic_devid(info->ioapic_id);
3728 break;
3729 case X86_IRQ_ALLOC_TYPE_HPET:
3730 devid = get_hpet_devid(info->hpet_id);
3731 break;
3732 case X86_IRQ_ALLOC_TYPE_MSI:
3733 case X86_IRQ_ALLOC_TYPE_MSIX:
3734 devid = get_device_id(&info->msi_dev->dev);
3735 break;
3736 default:
3737 BUG_ON(1);
3738 break;
3739 }
3740
3741 return devid;
3742 }
3743
3744 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3745 {
3746 struct amd_iommu *iommu;
3747 int devid;
3748
3749 if (!info)
3750 return NULL;
3751
3752 devid = get_devid(info);
3753 if (devid >= 0) {
3754 iommu = amd_iommu_rlookup_table[devid];
3755 if (iommu)
3756 return iommu->ir_domain;
3757 }
3758
3759 return NULL;
3760 }
3761
3762 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3763 {
3764 struct amd_iommu *iommu;
3765 int devid;
3766
3767 if (!info)
3768 return NULL;
3769
3770 switch (info->type) {
3771 case X86_IRQ_ALLOC_TYPE_MSI:
3772 case X86_IRQ_ALLOC_TYPE_MSIX:
3773 devid = get_device_id(&info->msi_dev->dev);
3774 if (devid < 0)
3775 return NULL;
3776
3777 iommu = amd_iommu_rlookup_table[devid];
3778 if (iommu)
3779 return iommu->msi_domain;
3780 break;
3781 default:
3782 break;
3783 }
3784
3785 return NULL;
3786 }
3787
3788 struct irq_remap_ops amd_iommu_irq_ops = {
3789 .prepare = amd_iommu_prepare,
3790 .enable = amd_iommu_enable,
3791 .disable = amd_iommu_disable,
3792 .reenable = amd_iommu_reenable,
3793 .enable_faulting = amd_iommu_enable_faulting,
3794 .get_ir_irq_domain = get_ir_irq_domain,
3795 .get_irq_domain = get_irq_domain,
3796 };
3797
3798 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3799 struct irq_cfg *irq_cfg,
3800 struct irq_alloc_info *info,
3801 int devid, int index, int sub_handle)
3802 {
3803 struct irq_2_irte *irte_info = &data->irq_2_irte;
3804 struct msi_msg *msg = &data->msi_entry;
3805 union irte *irte = &data->irte_entry;
3806 struct IO_APIC_route_entry *entry;
3807
3808 data->irq_2_irte.devid = devid;
3809 data->irq_2_irte.index = index + sub_handle;
3810
3811 /* Setup IRTE for IOMMU */
3812 irte->val = 0;
3813 irte->fields.vector = irq_cfg->vector;
3814 irte->fields.int_type = apic->irq_delivery_mode;
3815 irte->fields.destination = irq_cfg->dest_apicid;
3816 irte->fields.dm = apic->irq_dest_mode;
3817 irte->fields.valid = 1;
3818
3819 switch (info->type) {
3820 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3821 /* Setup IOAPIC entry */
3822 entry = info->ioapic_entry;
3823 info->ioapic_entry = NULL;
3824 memset(entry, 0, sizeof(*entry));
3825 entry->vector = index;
3826 entry->mask = 0;
3827 entry->trigger = info->ioapic_trigger;
3828 entry->polarity = info->ioapic_polarity;
3829 /* Mask level triggered irqs. */
3830 if (info->ioapic_trigger)
3831 entry->mask = 1;
3832 break;
3833
3834 case X86_IRQ_ALLOC_TYPE_HPET:
3835 case X86_IRQ_ALLOC_TYPE_MSI:
3836 case X86_IRQ_ALLOC_TYPE_MSIX:
3837 msg->address_hi = MSI_ADDR_BASE_HI;
3838 msg->address_lo = MSI_ADDR_BASE_LO;
3839 msg->data = irte_info->index;
3840 break;
3841
3842 default:
3843 BUG_ON(1);
3844 break;
3845 }
3846 }
3847
3848 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3849 unsigned int nr_irqs, void *arg)
3850 {
3851 struct irq_alloc_info *info = arg;
3852 struct irq_data *irq_data;
3853 struct amd_ir_data *data;
3854 struct irq_cfg *cfg;
3855 int i, ret, devid;
3856 int index = -1;
3857
3858 if (!info)
3859 return -EINVAL;
3860 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3861 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3862 return -EINVAL;
3863
3864 /*
3865 * With IRQ remapping enabled, don't need contiguous CPU vectors
3866 * to support multiple MSI interrupts.
3867 */
3868 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3869 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3870
3871 devid = get_devid(info);
3872 if (devid < 0)
3873 return -EINVAL;
3874
3875 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3876 if (ret < 0)
3877 return ret;
3878
3879 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3880 if (get_irq_table(devid, true))
3881 index = info->ioapic_pin;
3882 else
3883 ret = -ENOMEM;
3884 } else {
3885 index = alloc_irq_index(devid, nr_irqs);
3886 }
3887 if (index < 0) {
3888 pr_warn("Failed to allocate IRTE\n");
3889 goto out_free_parent;
3890 }
3891
3892 for (i = 0; i < nr_irqs; i++) {
3893 irq_data = irq_domain_get_irq_data(domain, virq + i);
3894 cfg = irqd_cfg(irq_data);
3895 if (!irq_data || !cfg) {
3896 ret = -EINVAL;
3897 goto out_free_data;
3898 }
3899
3900 ret = -ENOMEM;
3901 data = kzalloc(sizeof(*data), GFP_KERNEL);
3902 if (!data)
3903 goto out_free_data;
3904
3905 irq_data->hwirq = (devid << 16) + i;
3906 irq_data->chip_data = data;
3907 irq_data->chip = &amd_ir_chip;
3908 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3909 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3910 }
3911
3912 return 0;
3913
3914 out_free_data:
3915 for (i--; i >= 0; i--) {
3916 irq_data = irq_domain_get_irq_data(domain, virq + i);
3917 if (irq_data)
3918 kfree(irq_data->chip_data);
3919 }
3920 for (i = 0; i < nr_irqs; i++)
3921 free_irte(devid, index + i);
3922 out_free_parent:
3923 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3924 return ret;
3925 }
3926
3927 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3928 unsigned int nr_irqs)
3929 {
3930 struct irq_2_irte *irte_info;
3931 struct irq_data *irq_data;
3932 struct amd_ir_data *data;
3933 int i;
3934
3935 for (i = 0; i < nr_irqs; i++) {
3936 irq_data = irq_domain_get_irq_data(domain, virq + i);
3937 if (irq_data && irq_data->chip_data) {
3938 data = irq_data->chip_data;
3939 irte_info = &data->irq_2_irte;
3940 free_irte(irte_info->devid, irte_info->index);
3941 kfree(data);
3942 }
3943 }
3944 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3945 }
3946
3947 static void irq_remapping_activate(struct irq_domain *domain,
3948 struct irq_data *irq_data)
3949 {
3950 struct amd_ir_data *data = irq_data->chip_data;
3951 struct irq_2_irte *irte_info = &data->irq_2_irte;
3952
3953 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
3954 }
3955
3956 static void irq_remapping_deactivate(struct irq_domain *domain,
3957 struct irq_data *irq_data)
3958 {
3959 struct amd_ir_data *data = irq_data->chip_data;
3960 struct irq_2_irte *irte_info = &data->irq_2_irte;
3961 union irte entry;
3962
3963 entry.val = 0;
3964 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
3965 }
3966
3967 static struct irq_domain_ops amd_ir_domain_ops = {
3968 .alloc = irq_remapping_alloc,
3969 .free = irq_remapping_free,
3970 .activate = irq_remapping_activate,
3971 .deactivate = irq_remapping_deactivate,
3972 };
3973
3974 static int amd_ir_set_affinity(struct irq_data *data,
3975 const struct cpumask *mask, bool force)
3976 {
3977 struct amd_ir_data *ir_data = data->chip_data;
3978 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3979 struct irq_cfg *cfg = irqd_cfg(data);
3980 struct irq_data *parent = data->parent_data;
3981 int ret;
3982
3983 ret = parent->chip->irq_set_affinity(parent, mask, force);
3984 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3985 return ret;
3986
3987 /*
3988 * Atomically updates the IRTE with the new destination, vector
3989 * and flushes the interrupt entry cache.
3990 */
3991 ir_data->irte_entry.fields.vector = cfg->vector;
3992 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
3993 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
3994
3995 /*
3996 * After this point, all the interrupts will start arriving
3997 * at the new destination. So, time to cleanup the previous
3998 * vector allocation.
3999 */
4000 send_cleanup_vector(cfg);
4001
4002 return IRQ_SET_MASK_OK_DONE;
4003 }
4004
4005 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4006 {
4007 struct amd_ir_data *ir_data = irq_data->chip_data;
4008
4009 *msg = ir_data->msi_entry;
4010 }
4011
4012 static struct irq_chip amd_ir_chip = {
4013 .irq_ack = ir_ack_apic_edge,
4014 .irq_set_affinity = amd_ir_set_affinity,
4015 .irq_compose_msi_msg = ir_compose_msi_msg,
4016 };
4017
4018 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4019 {
4020 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4021 if (!iommu->ir_domain)
4022 return -ENOMEM;
4023
4024 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4025 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4026
4027 return 0;
4028 }
4029 #endif
Linux with added FPC-III support