2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/serial_8250.h>
15 #include <linux/serial_reg.h>
16 #include <linux/dmaengine.h>
18 struct uart_8250_dma
{
19 int (*tx_dma
)(struct uart_8250_port
*p
);
20 int (*rx_dma
)(struct uart_8250_port
*p
);
24 /* Parameter to the filter function */
28 struct dma_slave_config rxconf
;
29 struct dma_slave_config txconf
;
31 struct dma_chan
*rxchan
;
32 struct dma_chan
*txchan
;
37 dma_cookie_t rx_cookie
;
38 dma_cookie_t tx_cookie
;
45 unsigned char tx_running
;
47 unsigned char rx_running
;
50 struct old_serial_port
{
52 unsigned int baud_base
;
56 unsigned char io_type
;
57 unsigned char __iomem
*iomem_base
;
58 unsigned short iomem_reg_shift
;
61 struct serial8250_config
{
63 unsigned short fifo_size
;
64 unsigned short tx_loadsz
;
66 unsigned char rxtrig_bytes
[UART_FCR_R_TRIG_MAX_STATE
];
70 #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
71 #define UART_CAP_EFR (1 << 9) /* UART has EFR */
72 #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
73 #define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
74 #define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
75 #define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
76 #define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */
77 #define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */
79 #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
80 #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
81 #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
82 #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
83 #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
86 #ifdef CONFIG_SERIAL_8250_SHARE_IRQ
87 #define SERIAL8250_SHARE_IRQS 1
89 #define SERIAL8250_SHARE_IRQS 0
92 #define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \
97 .iotype = UPIO_PORT, \
98 .flags = UPF_BOOT_AUTOCONF | (_flags), \
101 #define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)
104 static inline int serial_in(struct uart_8250_port
*up
, int offset
)
106 return up
->port
.serial_in(&up
->port
, offset
);
109 static inline void serial_out(struct uart_8250_port
*up
, int offset
, int value
)
111 up
->port
.serial_out(&up
->port
, offset
, value
);
114 void serial8250_clear_and_reinit_fifos(struct uart_8250_port
*p
);
116 static inline int serial_dl_read(struct uart_8250_port
*up
)
118 return up
->dl_read(up
);
121 static inline void serial_dl_write(struct uart_8250_port
*up
, int value
)
123 up
->dl_write(up
, value
);
126 struct uart_8250_port
*serial8250_get_port(int line
);
127 void serial8250_rpm_get(struct uart_8250_port
*p
);
128 void serial8250_rpm_put(struct uart_8250_port
*p
);
129 int serial8250_em485_init(struct uart_8250_port
*p
);
130 void serial8250_em485_destroy(struct uart_8250_port
*p
);
132 static inline void serial8250_out_MCR(struct uart_8250_port
*up
, int value
)
134 serial_out(up
, UART_MCR
, value
);
137 static inline int serial8250_in_MCR(struct uart_8250_port
*up
)
139 return serial_in(up
, UART_MCR
);
142 #if defined(__alpha__) && !defined(CONFIG_PCI)
144 * Digital did something really horribly wrong with the OUT1 and OUT2
145 * lines on at least some ALPHA's. The failure mode is that if either
146 * is cleared, the machine locks up with endless interrupts.
148 #define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
150 #define ALPHA_KLUDGE_MCR 0
153 #ifdef CONFIG_SERIAL_8250_PNP
154 int serial8250_pnp_init(void);
155 void serial8250_pnp_exit(void);
157 static inline int serial8250_pnp_init(void) { return 0; }
158 static inline void serial8250_pnp_exit(void) { }
161 #ifdef CONFIG_SERIAL_8250_FINTEK
162 int fintek_8250_probe(struct uart_8250_port
*uart
);
164 static inline int fintek_8250_probe(struct uart_8250_port
*uart
) { return 0; }
167 #ifdef CONFIG_ARCH_OMAP1
168 static inline int is_omap1_8250(struct uart_8250_port
*pt
)
172 switch (pt
->port
.mapbase
) {
173 case OMAP1_UART1_BASE
:
174 case OMAP1_UART2_BASE
:
175 case OMAP1_UART3_BASE
:
186 static inline int is_omap1510_8250(struct uart_8250_port
*pt
)
188 if (!cpu_is_omap1510())
191 return is_omap1_8250(pt
);
194 static inline int is_omap1_8250(struct uart_8250_port
*pt
)
198 static inline int is_omap1510_8250(struct uart_8250_port
*pt
)
204 #ifdef CONFIG_SERIAL_8250_DMA
205 extern int serial8250_tx_dma(struct uart_8250_port
*);
206 extern int serial8250_rx_dma(struct uart_8250_port
*);
207 extern void serial8250_rx_dma_flush(struct uart_8250_port
*);
208 extern int serial8250_request_dma(struct uart_8250_port
*);
209 extern void serial8250_release_dma(struct uart_8250_port
*);
211 static inline int serial8250_tx_dma(struct uart_8250_port
*p
)
215 static inline int serial8250_rx_dma(struct uart_8250_port
*p
)
219 static inline void serial8250_rx_dma_flush(struct uart_8250_port
*p
) { }
220 static inline int serial8250_request_dma(struct uart_8250_port
*p
)
224 static inline void serial8250_release_dma(struct uart_8250_port
*p
) { }
227 static inline int ns16550a_goto_highspeed(struct uart_8250_port
*up
)
229 unsigned char status
;
231 status
= serial_in(up
, 0x04); /* EXCR2 */
232 #define PRESL(x) ((x) & 0x30)
233 if (PRESL(status
) == 0x10) {
234 /* already in high speed mode */
237 status
&= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
238 status
|= 0x10; /* 1.625 divisor for baud_base --> 921600 */
239 serial_out(up
, 0x04, status
);
244 static inline int serial_index(struct uart_port
*port
)
246 return port
->minor
- 64;