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USB: serial: option: add support for Telit ME910 PID 0x1101
[linux/fpc-iii.git] / drivers / tty / serial / mvebu-uart.c
bloba100e98259d7e86579554e9b4c768b49f6ef9383
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ***************************************************************************
4 * Marvell Armada-3700 Serial Driver
5 * Author: Wilson Ding <dingwei@marvell.com>
6 * Copyright (C) 2015 Marvell International Ltd.
7 * ***************************************************************************
8 */
9
10 #include <linux/clk.h>
11 #include <linux/console.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28
29 /* Register Map */
30 #define UART_STD_RBR 0x00
31 #define UART_EXT_RBR 0x18
32
33 #define UART_STD_TSH 0x04
34 #define UART_EXT_TSH 0x1C
35
36 #define UART_STD_CTRL1 0x08
37 #define UART_EXT_CTRL1 0x04
38 #define CTRL_SOFT_RST BIT(31)
39 #define CTRL_TXFIFO_RST BIT(15)
40 #define CTRL_RXFIFO_RST BIT(14)
41 #define CTRL_SND_BRK_SEQ BIT(11)
42 #define CTRL_BRK_DET_INT BIT(3)
43 #define CTRL_FRM_ERR_INT BIT(2)
44 #define CTRL_PAR_ERR_INT BIT(1)
45 #define CTRL_OVR_ERR_INT BIT(0)
46 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
47 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
48
49 #define UART_STD_CTRL2 UART_STD_CTRL1
50 #define UART_EXT_CTRL2 0x20
51 #define CTRL_STD_TX_RDY_INT BIT(5)
52 #define CTRL_EXT_TX_RDY_INT BIT(6)
53 #define CTRL_STD_RX_RDY_INT BIT(4)
54 #define CTRL_EXT_RX_RDY_INT BIT(5)
55
56 #define UART_STAT 0x0C
57 #define STAT_TX_FIFO_EMP BIT(13)
58 #define STAT_TX_FIFO_FUL BIT(11)
59 #define STAT_TX_EMP BIT(6)
60 #define STAT_STD_TX_RDY BIT(5)
61 #define STAT_EXT_TX_RDY BIT(15)
62 #define STAT_STD_RX_RDY BIT(4)
63 #define STAT_EXT_RX_RDY BIT(14)
64 #define STAT_BRK_DET BIT(3)
65 #define STAT_FRM_ERR BIT(2)
66 #define STAT_PAR_ERR BIT(1)
67 #define STAT_OVR_ERR BIT(0)
68 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR | STAT_FRM_ERR\
69 | STAT_PAR_ERR | STAT_OVR_ERR)
70
71 #define UART_BRDV 0x10
72 #define BRDV_BAUD_MASK 0x3FF
73
74 #define MVEBU_NR_UARTS 2
75
76 #define MVEBU_UART_TYPE "mvebu-uart"
77 #define DRIVER_NAME "mvebu_serial"
78
79 enum {
80 /* Either there is only one summed IRQ... */
81 UART_IRQ_SUM = 0,
82 /* ...or there are two separate IRQ for RX and TX */
83 UART_RX_IRQ = 0,
84 UART_TX_IRQ,
85 UART_IRQ_COUNT
86 };
87
88 /* Diverging register offsets */
89 struct uart_regs_layout {
90 unsigned int rbr;
91 unsigned int tsh;
92 unsigned int ctrl;
93 unsigned int intr;
94 };
95
96 /* Diverging flags */
97 struct uart_flags {
98 unsigned int ctrl_tx_rdy_int;
99 unsigned int ctrl_rx_rdy_int;
100 unsigned int stat_tx_rdy;
101 unsigned int stat_rx_rdy;
102 };
103
104 /* Driver data, a structure for each UART port */
105 struct mvebu_uart_driver_data {
106 bool is_ext;
107 struct uart_regs_layout regs;
108 struct uart_flags flags;
109 };
110
111 /* MVEBU UART driver structure */
112 struct mvebu_uart {
113 struct uart_port *port;
114 struct clk *clk;
115 int irq[UART_IRQ_COUNT];
116 unsigned char __iomem *nb;
117 struct mvebu_uart_driver_data *data;
118 };
119
120 static struct mvebu_uart *to_mvuart(struct uart_port *port)
121 {
122 return (struct mvebu_uart *)port->private_data;
123 }
124
125 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
126
127 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
128 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
129 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
130 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
131
132 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
133 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
134 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
135 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
136
137 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
138
139 /* Core UART Driver Operations */
140 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
141 {
142 unsigned long flags;
143 unsigned int st;
144
145 spin_lock_irqsave(&port->lock, flags);
146 st = readl(port->membase + UART_STAT);
147 spin_unlock_irqrestore(&port->lock, flags);
148
149 return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
150 }
151
152 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
153 {
154 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
155 }
156
157 static void mvebu_uart_set_mctrl(struct uart_port *port,
158 unsigned int mctrl)
159 {
160 /*
161 * Even if we do not support configuring the modem control lines, this
162 * function must be proided to the serial core
163 */
164 }
165
166 static void mvebu_uart_stop_tx(struct uart_port *port)
167 {
168 unsigned int ctl = readl(port->membase + UART_INTR(port));
169
170 ctl &= ~CTRL_TX_RDY_INT(port);
171 writel(ctl, port->membase + UART_INTR(port));
172 }
173
174 static void mvebu_uart_start_tx(struct uart_port *port)
175 {
176 unsigned int ctl;
177 struct circ_buf *xmit = &port->state->xmit;
178
179 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
180 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
181 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
182 port->icount.tx++;
183 }
184
185 ctl = readl(port->membase + UART_INTR(port));
186 ctl |= CTRL_TX_RDY_INT(port);
187 writel(ctl, port->membase + UART_INTR(port));
188 }
189
190 static void mvebu_uart_stop_rx(struct uart_port *port)
191 {
192 unsigned int ctl;
193
194 ctl = readl(port->membase + UART_CTRL(port));
195 ctl &= ~CTRL_BRK_INT;
196 writel(ctl, port->membase + UART_CTRL(port));
197
198 ctl = readl(port->membase + UART_INTR(port));
199 ctl &= ~CTRL_RX_RDY_INT(port);
200 writel(ctl, port->membase + UART_INTR(port));
201 }
202
203 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
204 {
205 unsigned int ctl;
206 unsigned long flags;
207
208 spin_lock_irqsave(&port->lock, flags);
209 ctl = readl(port->membase + UART_CTRL(port));
210 if (brk == -1)
211 ctl |= CTRL_SND_BRK_SEQ;
212 else
213 ctl &= ~CTRL_SND_BRK_SEQ;
214 writel(ctl, port->membase + UART_CTRL(port));
215 spin_unlock_irqrestore(&port->lock, flags);
216 }
217
218 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
219 {
220 struct tty_port *tport = &port->state->port;
221 unsigned char ch = 0;
222 char flag = 0;
223
224 do {
225 if (status & STAT_RX_RDY(port)) {
226 ch = readl(port->membase + UART_RBR(port));
227 ch &= 0xff;
228 flag = TTY_NORMAL;
229 port->icount.rx++;
230
231 if (status & STAT_PAR_ERR)
232 port->icount.parity++;
233 }
234
235 if (status & STAT_BRK_DET) {
236 port->icount.brk++;
237 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
238 if (uart_handle_break(port))
239 goto ignore_char;
240 }
241
242 if (status & STAT_OVR_ERR)
243 port->icount.overrun++;
244
245 if (status & STAT_FRM_ERR)
246 port->icount.frame++;
247
248 if (uart_handle_sysrq_char(port, ch))
249 goto ignore_char;
250
251 if (status & port->ignore_status_mask & STAT_PAR_ERR)
252 status &= ~STAT_RX_RDY(port);
253
254 status &= port->read_status_mask;
255
256 if (status & STAT_PAR_ERR)
257 flag = TTY_PARITY;
258
259 status &= ~port->ignore_status_mask;
260
261 if (status & STAT_RX_RDY(port))
262 tty_insert_flip_char(tport, ch, flag);
263
264 if (status & STAT_BRK_DET)
265 tty_insert_flip_char(tport, 0, TTY_BREAK);
266
267 if (status & STAT_FRM_ERR)
268 tty_insert_flip_char(tport, 0, TTY_FRAME);
269
270 if (status & STAT_OVR_ERR)
271 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
272
273 ignore_char:
274 status = readl(port->membase + UART_STAT);
275 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
276
277 tty_flip_buffer_push(tport);
278 }
279
280 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
281 {
282 struct circ_buf *xmit = &port->state->xmit;
283 unsigned int count;
284 unsigned int st;
285
286 if (port->x_char) {
287 writel(port->x_char, port->membase + UART_TSH(port));
288 port->icount.tx++;
289 port->x_char = 0;
290 return;
291 }
292
293 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
294 mvebu_uart_stop_tx(port);
295 return;
296 }
297
298 for (count = 0; count < port->fifosize; count++) {
299 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
300 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
301 port->icount.tx++;
302
303 if (uart_circ_empty(xmit))
304 break;
305
306 st = readl(port->membase + UART_STAT);
307 if (st & STAT_TX_FIFO_FUL)
308 break;
309 }
310
311 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
312 uart_write_wakeup(port);
313
314 if (uart_circ_empty(xmit))
315 mvebu_uart_stop_tx(port);
316 }
317
318 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
319 {
320 struct uart_port *port = (struct uart_port *)dev_id;
321 unsigned int st = readl(port->membase + UART_STAT);
322
323 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
324 STAT_BRK_DET))
325 mvebu_uart_rx_chars(port, st);
326
327 if (st & STAT_TX_RDY(port))
328 mvebu_uart_tx_chars(port, st);
329
330 return IRQ_HANDLED;
331 }
332
333 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
334 {
335 struct uart_port *port = (struct uart_port *)dev_id;
336 unsigned int st = readl(port->membase + UART_STAT);
337
338 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
339 STAT_BRK_DET))
340 mvebu_uart_rx_chars(port, st);
341
342 return IRQ_HANDLED;
343 }
344
345 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
346 {
347 struct uart_port *port = (struct uart_port *)dev_id;
348 unsigned int st = readl(port->membase + UART_STAT);
349
350 if (st & STAT_TX_RDY(port))
351 mvebu_uart_tx_chars(port, st);
352
353 return IRQ_HANDLED;
354 }
355
356 static int mvebu_uart_startup(struct uart_port *port)
357 {
358 struct mvebu_uart *mvuart = to_mvuart(port);
359 unsigned int ctl;
360 int ret;
361
362 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
363 port->membase + UART_CTRL(port));
364 udelay(1);
365
366 /* Clear the error bits of state register before IRQ request */
367 ret = readl(port->membase + UART_STAT);
368 ret |= STAT_BRK_ERR;
369 writel(ret, port->membase + UART_STAT);
370
371 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
372
373 ctl = readl(port->membase + UART_INTR(port));
374 ctl |= CTRL_RX_RDY_INT(port);
375 writel(ctl, port->membase + UART_INTR(port));
376
377 if (!mvuart->irq[UART_TX_IRQ]) {
378 /* Old bindings with just one interrupt (UART0 only) */
379 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
380 mvebu_uart_isr, port->irqflags,
381 dev_name(port->dev), port);
382 if (ret) {
383 dev_err(port->dev, "unable to request IRQ %d\n",
384 mvuart->irq[UART_IRQ_SUM]);
385 return ret;
386 }
387 } else {
388 /* New bindings with an IRQ for RX and TX (both UART) */
389 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
390 mvebu_uart_rx_isr, port->irqflags,
391 dev_name(port->dev), port);
392 if (ret) {
393 dev_err(port->dev, "unable to request IRQ %d\n",
394 mvuart->irq[UART_RX_IRQ]);
395 return ret;
396 }
397
398 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
399 mvebu_uart_tx_isr, port->irqflags,
400 dev_name(port->dev),
401 port);
402 if (ret) {
403 dev_err(port->dev, "unable to request IRQ %d\n",
404 mvuart->irq[UART_TX_IRQ]);
405 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
406 port);
407 return ret;
408 }
409 }
410
411 return 0;
412 }
413
414 static void mvebu_uart_shutdown(struct uart_port *port)
415 {
416 struct mvebu_uart *mvuart = to_mvuart(port);
417
418 writel(0, port->membase + UART_INTR(port));
419
420 if (!mvuart->irq[UART_TX_IRQ]) {
421 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
422 } else {
423 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
424 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
425 }
426 }
427
428 static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
429 {
430 struct mvebu_uart *mvuart = to_mvuart(port);
431 unsigned int baud_rate_div;
432 u32 brdv;
433
434 if (IS_ERR(mvuart->clk))
435 return -PTR_ERR(mvuart->clk);
436
437 /*
438 * The UART clock is divided by the value of the divisor to generate
439 * UCLK_OUT clock, which is 16 times faster than the baudrate.
440 * This prescaler can achieve all standard baudrates until 230400.
441 * Higher baudrates could be achieved for the extended UART by using the
442 * programmable oversampling stack (also called fractional divisor).
443 */
444 baud_rate_div = DIV_ROUND_UP(port->uartclk, baud * 16);
445 brdv = readl(port->membase + UART_BRDV);
446 brdv &= ~BRDV_BAUD_MASK;
447 brdv |= baud_rate_div;
448 writel(brdv, port->membase + UART_BRDV);
449
450 return 0;
451 }
452
453 static void mvebu_uart_set_termios(struct uart_port *port,
454 struct ktermios *termios,
455 struct ktermios *old)
456 {
457 unsigned long flags;
458 unsigned int baud;
459
460 spin_lock_irqsave(&port->lock, flags);
461
462 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
463 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
464
465 if (termios->c_iflag & INPCK)
466 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
467
468 port->ignore_status_mask = 0;
469 if (termios->c_iflag & IGNPAR)
470 port->ignore_status_mask |=
471 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
472
473 if ((termios->c_cflag & CREAD) == 0)
474 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
475
476 /*
477 * Maximum achievable frequency with simple baudrate divisor is 230400.
478 * Since the error per bit frame would be of more than 15%, achieving
479 * higher frequencies would require to implement the fractional divisor
480 * feature.
481 */
482 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
483 if (mvebu_uart_baud_rate_set(port, baud)) {
484 /* No clock available, baudrate cannot be changed */
485 if (old)
486 baud = uart_get_baud_rate(port, old, NULL, 0, 230400);
487 } else {
488 tty_termios_encode_baud_rate(termios, baud, baud);
489 uart_update_timeout(port, termios->c_cflag, baud);
490 }
491
492 /* Only the following flag changes are supported */
493 if (old) {
494 termios->c_iflag &= INPCK | IGNPAR;
495 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
496 termios->c_cflag &= CREAD | CBAUD;
497 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
498 termios->c_lflag = old->c_lflag;
499 }
500
501 spin_unlock_irqrestore(&port->lock, flags);
502 }
503
504 static const char *mvebu_uart_type(struct uart_port *port)
505 {
506 return MVEBU_UART_TYPE;
507 }
508
509 static void mvebu_uart_release_port(struct uart_port *port)
510 {
511 /* Nothing to do here */
512 }
513
514 static int mvebu_uart_request_port(struct uart_port *port)
515 {
516 return 0;
517 }
518
519 #ifdef CONFIG_CONSOLE_POLL
520 static int mvebu_uart_get_poll_char(struct uart_port *port)
521 {
522 unsigned int st = readl(port->membase + UART_STAT);
523
524 if (!(st & STAT_RX_RDY(port)))
525 return NO_POLL_CHAR;
526
527 return readl(port->membase + UART_RBR(port));
528 }
529
530 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
531 {
532 unsigned int st;
533
534 for (;;) {
535 st = readl(port->membase + UART_STAT);
536
537 if (!(st & STAT_TX_FIFO_FUL))
538 break;
539
540 udelay(1);
541 }
542
543 writel(c, port->membase + UART_TSH(port));
544 }
545 #endif
546
547 static const struct uart_ops mvebu_uart_ops = {
548 .tx_empty = mvebu_uart_tx_empty,
549 .set_mctrl = mvebu_uart_set_mctrl,
550 .get_mctrl = mvebu_uart_get_mctrl,
551 .stop_tx = mvebu_uart_stop_tx,
552 .start_tx = mvebu_uart_start_tx,
553 .stop_rx = mvebu_uart_stop_rx,
554 .break_ctl = mvebu_uart_break_ctl,
555 .startup = mvebu_uart_startup,
556 .shutdown = mvebu_uart_shutdown,
557 .set_termios = mvebu_uart_set_termios,
558 .type = mvebu_uart_type,
559 .release_port = mvebu_uart_release_port,
560 .request_port = mvebu_uart_request_port,
561 #ifdef CONFIG_CONSOLE_POLL
562 .poll_get_char = mvebu_uart_get_poll_char,
563 .poll_put_char = mvebu_uart_put_poll_char,
564 #endif
565 };
566
567 /* Console Driver Operations */
568
569 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
570 /* Early Console */
571 static void mvebu_uart_putc(struct uart_port *port, int c)
572 {
573 unsigned int st;
574
575 for (;;) {
576 st = readl(port->membase + UART_STAT);
577 if (!(st & STAT_TX_FIFO_FUL))
578 break;
579 }
580
581 /* At early stage, DT is not parsed yet, only use UART0 */
582 writel(c, port->membase + UART_STD_TSH);
583
584 for (;;) {
585 st = readl(port->membase + UART_STAT);
586 if (st & STAT_TX_FIFO_EMP)
587 break;
588 }
589 }
590
591 static void mvebu_uart_putc_early_write(struct console *con,
592 const char *s,
593 unsigned n)
594 {
595 struct earlycon_device *dev = con->data;
596
597 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
598 }
599
600 static int __init
601 mvebu_uart_early_console_setup(struct earlycon_device *device,
602 const char *opt)
603 {
604 if (!device->port.membase)
605 return -ENODEV;
606
607 device->con->write = mvebu_uart_putc_early_write;
608
609 return 0;
610 }
611
612 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
613 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
614 mvebu_uart_early_console_setup);
615
616 static void wait_for_xmitr(struct uart_port *port)
617 {
618 u32 val;
619
620 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
621 (val & STAT_TX_EMP), 1, 10000);
622 }
623
624 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
625 {
626 wait_for_xmitr(port);
627 writel(ch, port->membase + UART_TSH(port));
628 }
629
630 static void mvebu_uart_console_write(struct console *co, const char *s,
631 unsigned int count)
632 {
633 struct uart_port *port = &mvebu_uart_ports[co->index];
634 unsigned long flags;
635 unsigned int ier, intr, ctl;
636 int locked = 1;
637
638 if (oops_in_progress)
639 locked = spin_trylock_irqsave(&port->lock, flags);
640 else
641 spin_lock_irqsave(&port->lock, flags);
642
643 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
644 intr = readl(port->membase + UART_INTR(port)) &
645 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
646 writel(0, port->membase + UART_CTRL(port));
647 writel(0, port->membase + UART_INTR(port));
648
649 uart_console_write(port, s, count, mvebu_uart_console_putchar);
650
651 wait_for_xmitr(port);
652
653 if (ier)
654 writel(ier, port->membase + UART_CTRL(port));
655
656 if (intr) {
657 ctl = intr | readl(port->membase + UART_INTR(port));
658 writel(ctl, port->membase + UART_INTR(port));
659 }
660
661 if (locked)
662 spin_unlock_irqrestore(&port->lock, flags);
663 }
664
665 static int mvebu_uart_console_setup(struct console *co, char *options)
666 {
667 struct uart_port *port;
668 int baud = 9600;
669 int bits = 8;
670 int parity = 'n';
671 int flow = 'n';
672
673 if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
674 return -EINVAL;
675
676 port = &mvebu_uart_ports[co->index];
677
678 if (!port->mapbase || !port->membase) {
679 pr_debug("console on ttyMV%i not present\n", co->index);
680 return -ENODEV;
681 }
682
683 if (options)
684 uart_parse_options(options, &baud, &parity, &bits, &flow);
685
686 return uart_set_options(port, co, baud, parity, bits, flow);
687 }
688
689 static struct uart_driver mvebu_uart_driver;
690
691 static struct console mvebu_uart_console = {
692 .name = "ttyMV",
693 .write = mvebu_uart_console_write,
694 .device = uart_console_device,
695 .setup = mvebu_uart_console_setup,
696 .flags = CON_PRINTBUFFER,
697 .index = -1,
698 .data = &mvebu_uart_driver,
699 };
700
701 static int __init mvebu_uart_console_init(void)
702 {
703 register_console(&mvebu_uart_console);
704 return 0;
705 }
706
707 console_initcall(mvebu_uart_console_init);
708
709
710 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
711
712 static struct uart_driver mvebu_uart_driver = {
713 .owner = THIS_MODULE,
714 .driver_name = DRIVER_NAME,
715 .dev_name = "ttyMV",
716 .nr = MVEBU_NR_UARTS,
717 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
718 .cons = &mvebu_uart_console,
719 #endif
720 };
721
722 static const struct of_device_id mvebu_uart_of_match[];
723
724 /* Counter to keep track of each UART port id when not using CONFIG_OF */
725 static int uart_num_counter;
726
727 static int mvebu_uart_probe(struct platform_device *pdev)
728 {
729 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
730 const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
731 &pdev->dev);
732 struct uart_port *port;
733 struct mvebu_uart *mvuart;
734 int ret, id, irq;
735
736 if (!reg) {
737 dev_err(&pdev->dev, "no registers defined\n");
738 return -EINVAL;
739 }
740
741 /* Assume that all UART ports have a DT alias or none has */
742 id = of_alias_get_id(pdev->dev.of_node, "serial");
743 if (!pdev->dev.of_node || id < 0)
744 pdev->id = uart_num_counter++;
745 else
746 pdev->id = id;
747
748 if (pdev->id >= MVEBU_NR_UARTS) {
749 dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
750 MVEBU_NR_UARTS);
751 return -EINVAL;
752 }
753
754 port = &mvebu_uart_ports[pdev->id];
755
756 spin_lock_init(&port->lock);
757
758 port->dev = &pdev->dev;
759 port->type = PORT_MVEBU;
760 port->ops = &mvebu_uart_ops;
761 port->regshift = 0;
762
763 port->fifosize = 32;
764 port->iotype = UPIO_MEM32;
765 port->flags = UPF_FIXED_PORT;
766 port->line = pdev->id;
767
768 /*
769 * IRQ number is not stored in this structure because we may have two of
770 * them per port (RX and TX). Instead, use the driver UART structure
771 * array so called ->irq[].
772 */
773 port->irq = 0;
774 port->irqflags = 0;
775 port->mapbase = reg->start;
776
777 port->membase = devm_ioremap_resource(&pdev->dev, reg);
778 if (IS_ERR(port->membase))
779 return -PTR_ERR(port->membase);
780
781 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
782 GFP_KERNEL);
783 if (!mvuart)
784 return -ENOMEM;
785
786 /* Get controller data depending on the compatible string */
787 mvuart->data = (struct mvebu_uart_driver_data *)match->data;
788 mvuart->port = port;
789
790 port->private_data = mvuart;
791 platform_set_drvdata(pdev, mvuart);
792
793 /* Get fixed clock frequency */
794 mvuart->clk = devm_clk_get(&pdev->dev, NULL);
795 if (IS_ERR(mvuart->clk)) {
796 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
797 return PTR_ERR(mvuart->clk);
798
799 if (IS_EXTENDED(port)) {
800 dev_err(&pdev->dev, "unable to get UART clock\n");
801 return PTR_ERR(mvuart->clk);
802 }
803 } else {
804 if (!clk_prepare_enable(mvuart->clk))
805 port->uartclk = clk_get_rate(mvuart->clk);
806 }
807
808 /* Manage interrupts */
809 if (platform_irq_count(pdev) == 1) {
810 /* Old bindings: no name on the single unamed UART0 IRQ */
811 irq = platform_get_irq(pdev, 0);
812 if (irq < 0) {
813 dev_err(&pdev->dev, "unable to get UART IRQ\n");
814 return irq;
815 }
816
817 mvuart->irq[UART_IRQ_SUM] = irq;
818 } else {
819 /*
820 * New bindings: named interrupts (RX, TX) for both UARTS,
821 * only make use of uart-rx and uart-tx interrupts, do not use
822 * uart-sum of UART0 port.
823 */
824 irq = platform_get_irq_byname(pdev, "uart-rx");
825 if (irq < 0) {
826 dev_err(&pdev->dev, "unable to get 'uart-rx' IRQ\n");
827 return irq;
828 }
829
830 mvuart->irq[UART_RX_IRQ] = irq;
831
832 irq = platform_get_irq_byname(pdev, "uart-tx");
833 if (irq < 0) {
834 dev_err(&pdev->dev, "unable to get 'uart-tx' IRQ\n");
835 return irq;
836 }
837
838 mvuart->irq[UART_TX_IRQ] = irq;
839 }
840
841 /* UART Soft Reset*/
842 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
843 udelay(1);
844 writel(0, port->membase + UART_CTRL(port));
845
846 ret = uart_add_one_port(&mvebu_uart_driver, port);
847 if (ret)
848 return ret;
849 return 0;
850 }
851
852 static struct mvebu_uart_driver_data uart_std_driver_data = {
853 .is_ext = false,
854 .regs.rbr = UART_STD_RBR,
855 .regs.tsh = UART_STD_TSH,
856 .regs.ctrl = UART_STD_CTRL1,
857 .regs.intr = UART_STD_CTRL2,
858 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
859 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
860 .flags.stat_tx_rdy = STAT_STD_TX_RDY,
861 .flags.stat_rx_rdy = STAT_STD_RX_RDY,
862 };
863
864 static struct mvebu_uart_driver_data uart_ext_driver_data = {
865 .is_ext = true,
866 .regs.rbr = UART_EXT_RBR,
867 .regs.tsh = UART_EXT_TSH,
868 .regs.ctrl = UART_EXT_CTRL1,
869 .regs.intr = UART_EXT_CTRL2,
870 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
871 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
872 .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
873 .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
874 };
875
876 /* Match table for of_platform binding */
877 static const struct of_device_id mvebu_uart_of_match[] = {
878 {
879 .compatible = "marvell,armada-3700-uart",
880 .data = (void *)&uart_std_driver_data,
881 },
882 {
883 .compatible = "marvell,armada-3700-uart-ext",
884 .data = (void *)&uart_ext_driver_data,
885 },
886 {}
887 };
888
889 static struct platform_driver mvebu_uart_platform_driver = {
890 .probe = mvebu_uart_probe,
891 .driver = {
892 .name = "mvebu-uart",
893 .of_match_table = of_match_ptr(mvebu_uart_of_match),
894 .suppress_bind_attrs = true,
895 },
896 };
897
898 static int __init mvebu_uart_init(void)
899 {
900 int ret;
901
902 ret = uart_register_driver(&mvebu_uart_driver);
903 if (ret)
904 return ret;
905
906 ret = platform_driver_register(&mvebu_uart_platform_driver);
907 if (ret)
908 uart_unregister_driver(&mvebu_uart_driver);
909
910 return ret;
911 }
912 arch_initcall(mvebu_uart_init);
Linux with added FPC-III support