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USB: serial: option: add support for Telit ME910 PID 0x1101
[linux/fpc-iii.git] / drivers / tty / serial / pic32_uart.c
blobfd80d999308d49772497c3230fa939907e221aa8
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_gpio.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/console.h>
21 #include <linux/clk.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/serial_core.h>
25 #include <linux/delay.h>
26
27 #include <asm/mach-pic32/pic32.h>
28 #include "pic32_uart.h"
29
30 /* UART name and device definitions */
31 #define PIC32_DEV_NAME "pic32-uart"
32 #define PIC32_MAX_UARTS 6
33 #define PIC32_SDEV_NAME "ttyPIC"
34
35 /* pic32_sport pointer for console use */
36 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
37
38 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
39 {
40 /* wait for tx empty, otherwise chars will be lost or corrupted */
41 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
42 udelay(1);
43 }
44
45 static inline int pic32_enable_clock(struct pic32_sport *sport)
46 {
47 int ret = clk_prepare_enable(sport->clk);
48
49 if (ret)
50 return ret;
51
52 sport->ref_clk++;
53 return 0;
54 }
55
56 static inline void pic32_disable_clock(struct pic32_sport *sport)
57 {
58 sport->ref_clk--;
59 clk_disable_unprepare(sport->clk);
60 }
61
62 /* serial core request to check if uart tx buffer is empty */
63 static unsigned int pic32_uart_tx_empty(struct uart_port *port)
64 {
65 struct pic32_sport *sport = to_pic32_sport(port);
66 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
67
68 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
69 }
70
71 /* serial core request to set UART outputs */
72 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
73 {
74 struct pic32_sport *sport = to_pic32_sport(port);
75
76 /* set loopback mode */
77 if (mctrl & TIOCM_LOOP)
78 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
79 PIC32_UART_MODE_LPBK);
80 else
81 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
82 PIC32_UART_MODE_LPBK);
83 }
84
85 /* get the state of CTS input pin for this port */
86 static unsigned int get_cts_state(struct pic32_sport *sport)
87 {
88 /* read and invert UxCTS */
89 if (gpio_is_valid(sport->cts_gpio))
90 return !gpio_get_value(sport->cts_gpio);
91
92 return 1;
93 }
94
95 /* serial core request to return the state of misc UART input pins */
96 static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
97 {
98 struct pic32_sport *sport = to_pic32_sport(port);
99 unsigned int mctrl = 0;
100
101 if (!sport->hw_flow_ctrl)
102 mctrl |= TIOCM_CTS;
103 else if (get_cts_state(sport))
104 mctrl |= TIOCM_CTS;
105
106 /* DSR and CD are not supported in PIC32, so return 1
107 * RI is not supported in PIC32, so return 0
108 */
109 mctrl |= TIOCM_CD;
110 mctrl |= TIOCM_DSR;
111
112 return mctrl;
113 }
114
115 /* stop tx and start tx are not called in pairs, therefore a flag indicates
116 * the status of irq to control the irq-depth.
117 */
118 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
119 {
120 if (en && !tx_irq_enabled(sport)) {
121 enable_irq(sport->irq_tx);
122 tx_irq_enabled(sport) = 1;
123 } else if (!en && tx_irq_enabled(sport)) {
124 /* use disable_irq_nosync() and not disable_irq() to avoid self
125 * imposed deadlock by not waiting for irq handler to end,
126 * since this callback is called from interrupt context.
127 */
128 disable_irq_nosync(sport->irq_tx);
129 tx_irq_enabled(sport) = 0;
130 }
131 }
132
133 /* serial core request to disable tx ASAP (used for flow control) */
134 static void pic32_uart_stop_tx(struct uart_port *port)
135 {
136 struct pic32_sport *sport = to_pic32_sport(port);
137
138 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
139 return;
140
141 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
142 return;
143
144 /* wait for tx empty */
145 pic32_wait_deplete_txbuf(sport);
146
147 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
148 PIC32_UART_STA_UTXEN);
149 pic32_uart_irqtxen(sport, 0);
150 }
151
152 /* serial core request to (re)enable tx */
153 static void pic32_uart_start_tx(struct uart_port *port)
154 {
155 struct pic32_sport *sport = to_pic32_sport(port);
156
157 pic32_uart_irqtxen(sport, 1);
158 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
159 PIC32_UART_STA_UTXEN);
160 }
161
162 /* serial core request to stop rx, called before port shutdown */
163 static void pic32_uart_stop_rx(struct uart_port *port)
164 {
165 struct pic32_sport *sport = to_pic32_sport(port);
166
167 /* disable rx interrupts */
168 disable_irq(sport->irq_rx);
169
170 /* receiver Enable bit OFF */
171 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
172 PIC32_UART_STA_URXEN);
173 }
174
175 /* serial core request to start/stop emitting break char */
176 static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
177 {
178 struct pic32_sport *sport = to_pic32_sport(port);
179 unsigned long flags;
180
181 spin_lock_irqsave(&port->lock, flags);
182
183 if (ctl)
184 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
185 PIC32_UART_STA_UTXBRK);
186 else
187 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
188 PIC32_UART_STA_UTXBRK);
189
190 spin_unlock_irqrestore(&port->lock, flags);
191 }
192
193 /* get port type in string format */
194 static const char *pic32_uart_type(struct uart_port *port)
195 {
196 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
197 }
198
199 /* read all chars in rx fifo and send them to core */
200 static void pic32_uart_do_rx(struct uart_port *port)
201 {
202 struct pic32_sport *sport = to_pic32_sport(port);
203 struct tty_port *tty;
204 unsigned int max_count;
205
206 /* limit number of char read in interrupt, should not be
207 * higher than fifo size anyway since we're much faster than
208 * serial port
209 */
210 max_count = PIC32_UART_RX_FIFO_DEPTH;
211
212 spin_lock(&port->lock);
213
214 tty = &port->state->port;
215
216 do {
217 u32 sta_reg, c;
218 char flag;
219
220 /* get overrun/fifo empty information from status register */
221 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
222 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
223
224 /* fifo reset is required to clear interrupt */
225 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
226 PIC32_UART_STA_OERR);
227
228 port->icount.overrun++;
229 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
230 }
231
232 /* Can at least one more character can be read? */
233 if (!(sta_reg & PIC32_UART_STA_URXDA))
234 break;
235
236 /* read the character and increment the rx counter */
237 c = pic32_uart_readl(sport, PIC32_UART_RX);
238
239 port->icount.rx++;
240 flag = TTY_NORMAL;
241 c &= 0xff;
242
243 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
244 (sta_reg & PIC32_UART_STA_FERR))) {
245
246 /* do stats first */
247 if (sta_reg & PIC32_UART_STA_PERR)
248 port->icount.parity++;
249 if (sta_reg & PIC32_UART_STA_FERR)
250 port->icount.frame++;
251
252 /* update flag wrt read_status_mask */
253 sta_reg &= port->read_status_mask;
254
255 if (sta_reg & PIC32_UART_STA_FERR)
256 flag = TTY_FRAME;
257 if (sta_reg & PIC32_UART_STA_PERR)
258 flag = TTY_PARITY;
259 }
260
261 if (uart_handle_sysrq_char(port, c))
262 continue;
263
264 if ((sta_reg & port->ignore_status_mask) == 0)
265 tty_insert_flip_char(tty, c, flag);
266
267 } while (--max_count);
268
269 spin_unlock(&port->lock);
270
271 tty_flip_buffer_push(tty);
272 }
273
274 /* fill tx fifo with chars to send, stop when fifo is about to be full
275 * or when all chars have been sent.
276 */
277 static void pic32_uart_do_tx(struct uart_port *port)
278 {
279 struct pic32_sport *sport = to_pic32_sport(port);
280 struct circ_buf *xmit = &port->state->xmit;
281 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
282
283 if (port->x_char) {
284 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
285 port->icount.tx++;
286 port->x_char = 0;
287 return;
288 }
289
290 if (uart_tx_stopped(port)) {
291 pic32_uart_stop_tx(port);
292 return;
293 }
294
295 if (uart_circ_empty(xmit))
296 goto txq_empty;
297
298 /* keep stuffing chars into uart tx buffer
299 * 1) until uart fifo is full
300 * or
301 * 2) until the circ buffer is empty
302 * (all chars have been sent)
303 * or
304 * 3) until the max count is reached
305 * (prevents lingering here for too long in certain cases)
306 */
307 while (!(PIC32_UART_STA_UTXBF &
308 pic32_uart_readl(sport, PIC32_UART_STA))) {
309 unsigned int c = xmit->buf[xmit->tail];
310
311 pic32_uart_writel(sport, PIC32_UART_TX, c);
312
313 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
314 port->icount.tx++;
315 if (uart_circ_empty(xmit))
316 break;
317 if (--max_count == 0)
318 break;
319 }
320
321 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
322 uart_write_wakeup(port);
323
324 if (uart_circ_empty(xmit))
325 goto txq_empty;
326
327 return;
328
329 txq_empty:
330 pic32_uart_irqtxen(sport, 0);
331 }
332
333 /* RX interrupt handler */
334 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
335 {
336 struct uart_port *port = dev_id;
337
338 pic32_uart_do_rx(port);
339
340 return IRQ_HANDLED;
341 }
342
343 /* TX interrupt handler */
344 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
345 {
346 struct uart_port *port = dev_id;
347 unsigned long flags;
348
349 spin_lock_irqsave(&port->lock, flags);
350 pic32_uart_do_tx(port);
351 spin_unlock_irqrestore(&port->lock, flags);
352
353 return IRQ_HANDLED;
354 }
355
356 /* FAULT interrupt handler */
357 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
358 {
359 /* do nothing: pic32_uart_do_rx() handles faults. */
360 return IRQ_HANDLED;
361 }
362
363 /* enable rx & tx operation on uart */
364 static void pic32_uart_en_and_unmask(struct uart_port *port)
365 {
366 struct pic32_sport *sport = to_pic32_sport(port);
367
368 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
369 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
370 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
371 PIC32_UART_MODE_ON);
372 }
373
374 /* disable rx & tx operation on uart */
375 static void pic32_uart_dsbl_and_mask(struct uart_port *port)
376 {
377 struct pic32_sport *sport = to_pic32_sport(port);
378
379 /* wait for tx empty, otherwise chars will be lost or corrupted */
380 pic32_wait_deplete_txbuf(sport);
381
382 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
383 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
384 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
385 PIC32_UART_MODE_ON);
386 }
387
388 /* serial core request to initialize uart and start rx operation */
389 static int pic32_uart_startup(struct uart_port *port)
390 {
391 struct pic32_sport *sport = to_pic32_sport(port);
392 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
393 unsigned long flags;
394 int ret;
395
396 local_irq_save(flags);
397
398 ret = pic32_enable_clock(sport);
399 if (ret) {
400 local_irq_restore(flags);
401 goto out_done;
402 }
403
404 /* clear status and mode registers */
405 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
406 pic32_uart_writel(sport, PIC32_UART_STA, 0);
407
408 /* disable uart and mask all interrupts */
409 pic32_uart_dsbl_and_mask(port);
410
411 /* set default baud */
412 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
413
414 local_irq_restore(flags);
415
416 /* Each UART of a PIC32 has three interrupts therefore,
417 * we setup driver to register the 3 irqs for the device.
418 *
419 * For each irq request_irq() is called with interrupt disabled.
420 * And the irq is enabled as soon as we are ready to handle them.
421 */
422 tx_irq_enabled(sport) = 0;
423
424 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
425 pic32_uart_type(port),
426 sport->idx);
427 if (!sport->irq_fault_name) {
428 dev_err(port->dev, "%s: kasprintf err!", __func__);
429 ret = -ENOMEM;
430 goto out_done;
431 }
432 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
433 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
434 sport->irqflags_fault, sport->irq_fault_name, port);
435 if (ret) {
436 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
437 __func__, sport->irq_fault, ret,
438 pic32_uart_type(port));
439 goto out_f;
440 }
441
442 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
443 pic32_uart_type(port),
444 sport->idx);
445 if (!sport->irq_rx_name) {
446 dev_err(port->dev, "%s: kasprintf err!", __func__);
447 ret = -ENOMEM;
448 goto out_f;
449 }
450 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
451 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
452 sport->irqflags_rx, sport->irq_rx_name, port);
453 if (ret) {
454 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
455 __func__, sport->irq_rx, ret,
456 pic32_uart_type(port));
457 goto out_r;
458 }
459
460 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
461 pic32_uart_type(port),
462 sport->idx);
463 if (!sport->irq_tx_name) {
464 dev_err(port->dev, "%s: kasprintf err!", __func__);
465 ret = -ENOMEM;
466 goto out_r;
467 }
468 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
469 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
470 sport->irqflags_tx, sport->irq_tx_name, port);
471 if (ret) {
472 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
473 __func__, sport->irq_tx, ret,
474 pic32_uart_type(port));
475 goto out_t;
476 }
477
478 local_irq_save(flags);
479
480 /* set rx interrupt on first receive */
481 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
482 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
483
484 /* set interrupt on empty */
485 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
486 PIC32_UART_STA_UTXISEL1);
487
488 /* enable all interrupts and eanable uart */
489 pic32_uart_en_and_unmask(port);
490
491 enable_irq(sport->irq_rx);
492
493 return 0;
494
495 out_t:
496 kfree(sport->irq_tx_name);
497 free_irq(sport->irq_tx, port);
498 out_r:
499 kfree(sport->irq_rx_name);
500 free_irq(sport->irq_rx, port);
501 out_f:
502 kfree(sport->irq_fault_name);
503 free_irq(sport->irq_fault, port);
504 out_done:
505 return ret;
506 }
507
508 /* serial core request to flush & disable uart */
509 static void pic32_uart_shutdown(struct uart_port *port)
510 {
511 struct pic32_sport *sport = to_pic32_sport(port);
512 unsigned long flags;
513
514 /* disable uart */
515 spin_lock_irqsave(&port->lock, flags);
516 pic32_uart_dsbl_and_mask(port);
517 spin_unlock_irqrestore(&port->lock, flags);
518 pic32_disable_clock(sport);
519
520 /* free all 3 interrupts for this UART */
521 free_irq(sport->irq_fault, port);
522 free_irq(sport->irq_tx, port);
523 free_irq(sport->irq_rx, port);
524 }
525
526 /* serial core request to change current uart setting */
527 static void pic32_uart_set_termios(struct uart_port *port,
528 struct ktermios *new,
529 struct ktermios *old)
530 {
531 struct pic32_sport *sport = to_pic32_sport(port);
532 unsigned int baud;
533 unsigned int quot;
534 unsigned long flags;
535
536 spin_lock_irqsave(&port->lock, flags);
537
538 /* disable uart and mask all interrupts while changing speed */
539 pic32_uart_dsbl_and_mask(port);
540
541 /* stop bit options */
542 if (new->c_cflag & CSTOPB)
543 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
544 PIC32_UART_MODE_STSEL);
545 else
546 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
547 PIC32_UART_MODE_STSEL);
548
549 /* parity options */
550 if (new->c_cflag & PARENB) {
551 if (new->c_cflag & PARODD) {
552 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
553 PIC32_UART_MODE_PDSEL1);
554 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
555 PIC32_UART_MODE_PDSEL0);
556 } else {
557 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
558 PIC32_UART_MODE_PDSEL0);
559 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
560 PIC32_UART_MODE_PDSEL1);
561 }
562 } else {
563 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
564 PIC32_UART_MODE_PDSEL1 |
565 PIC32_UART_MODE_PDSEL0);
566 }
567 /* if hw flow ctrl, then the pins must be specified in device tree */
568 if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
569 /* enable hardware flow control */
570 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
571 PIC32_UART_MODE_UEN1);
572 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
573 PIC32_UART_MODE_UEN0);
574 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
575 PIC32_UART_MODE_RTSMD);
576 } else {
577 /* disable hardware flow control */
578 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
579 PIC32_UART_MODE_UEN1);
580 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
581 PIC32_UART_MODE_UEN0);
582 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
583 PIC32_UART_MODE_RTSMD);
584 }
585
586 /* Always 8-bit */
587 new->c_cflag |= CS8;
588
589 /* Mark/Space parity is not supported */
590 new->c_cflag &= ~CMSPAR;
591
592 /* update baud */
593 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
594 quot = uart_get_divisor(port, baud) - 1;
595 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
596 uart_update_timeout(port, new->c_cflag, baud);
597
598 if (tty_termios_baud_rate(new))
599 tty_termios_encode_baud_rate(new, baud, baud);
600
601 /* enable uart */
602 pic32_uart_en_and_unmask(port);
603
604 spin_unlock_irqrestore(&port->lock, flags);
605 }
606
607 /* serial core request to claim uart iomem */
608 static int pic32_uart_request_port(struct uart_port *port)
609 {
610 struct platform_device *pdev = to_platform_device(port->dev);
611 struct resource *res_mem;
612
613 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
614 if (unlikely(!res_mem))
615 return -EINVAL;
616
617 if (!request_mem_region(port->mapbase, resource_size(res_mem),
618 "pic32_uart_mem"))
619 return -EBUSY;
620
621 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
622 resource_size(res_mem));
623 if (!port->membase) {
624 dev_err(port->dev, "Unable to map registers\n");
625 release_mem_region(port->mapbase, resource_size(res_mem));
626 return -ENOMEM;
627 }
628
629 return 0;
630 }
631
632 /* serial core request to release uart iomem */
633 static void pic32_uart_release_port(struct uart_port *port)
634 {
635 struct platform_device *pdev = to_platform_device(port->dev);
636 struct resource *res_mem;
637 unsigned int res_size;
638
639 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 if (unlikely(!res_mem))
641 return;
642 res_size = resource_size(res_mem);
643
644 release_mem_region(port->mapbase, res_size);
645 }
646
647 /* serial core request to do any port required auto-configuration */
648 static void pic32_uart_config_port(struct uart_port *port, int flags)
649 {
650 if (flags & UART_CONFIG_TYPE) {
651 if (pic32_uart_request_port(port))
652 return;
653 port->type = PORT_PIC32;
654 }
655 }
656
657 /* serial core request to check that port information in serinfo are suitable */
658 static int pic32_uart_verify_port(struct uart_port *port,
659 struct serial_struct *serinfo)
660 {
661 if (port->type != PORT_PIC32)
662 return -EINVAL;
663 if (port->irq != serinfo->irq)
664 return -EINVAL;
665 if (port->iotype != serinfo->io_type)
666 return -EINVAL;
667 if (port->mapbase != (unsigned long)serinfo->iomem_base)
668 return -EINVAL;
669
670 return 0;
671 }
672
673 /* serial core callbacks */
674 static const struct uart_ops pic32_uart_ops = {
675 .tx_empty = pic32_uart_tx_empty,
676 .get_mctrl = pic32_uart_get_mctrl,
677 .set_mctrl = pic32_uart_set_mctrl,
678 .start_tx = pic32_uart_start_tx,
679 .stop_tx = pic32_uart_stop_tx,
680 .stop_rx = pic32_uart_stop_rx,
681 .break_ctl = pic32_uart_break_ctl,
682 .startup = pic32_uart_startup,
683 .shutdown = pic32_uart_shutdown,
684 .set_termios = pic32_uart_set_termios,
685 .type = pic32_uart_type,
686 .release_port = pic32_uart_release_port,
687 .request_port = pic32_uart_request_port,
688 .config_port = pic32_uart_config_port,
689 .verify_port = pic32_uart_verify_port,
690 };
691
692 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
693 /* output given char */
694 static void pic32_console_putchar(struct uart_port *port, int ch)
695 {
696 struct pic32_sport *sport = to_pic32_sport(port);
697
698 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
699 return;
700
701 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
702 return;
703
704 /* wait for tx empty */
705 pic32_wait_deplete_txbuf(sport);
706
707 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
708 }
709
710 /* console core request to output given string */
711 static void pic32_console_write(struct console *co, const char *s,
712 unsigned int count)
713 {
714 struct pic32_sport *sport = pic32_sports[co->index];
715 struct uart_port *port = pic32_get_port(sport);
716
717 /* call uart helper to deal with \r\n */
718 uart_console_write(port, s, count, pic32_console_putchar);
719 }
720
721 /* console core request to setup given console, find matching uart
722 * port and setup it.
723 */
724 static int pic32_console_setup(struct console *co, char *options)
725 {
726 struct pic32_sport *sport;
727 struct uart_port *port = NULL;
728 int baud = 115200;
729 int bits = 8;
730 int parity = 'n';
731 int flow = 'n';
732 int ret = 0;
733
734 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
735 return -ENODEV;
736
737 sport = pic32_sports[co->index];
738 if (!sport)
739 return -ENODEV;
740 port = pic32_get_port(sport);
741
742 ret = pic32_enable_clock(sport);
743 if (ret)
744 return ret;
745
746 if (options)
747 uart_parse_options(options, &baud, &parity, &bits, &flow);
748
749 return uart_set_options(port, co, baud, parity, bits, flow);
750 }
751
752 static struct uart_driver pic32_uart_driver;
753 static struct console pic32_console = {
754 .name = PIC32_SDEV_NAME,
755 .write = pic32_console_write,
756 .device = uart_console_device,
757 .setup = pic32_console_setup,
758 .flags = CON_PRINTBUFFER,
759 .index = -1,
760 .data = &pic32_uart_driver,
761 };
762 #define PIC32_SCONSOLE (&pic32_console)
763
764 static int __init pic32_console_init(void)
765 {
766 register_console(&pic32_console);
767 return 0;
768 }
769 console_initcall(pic32_console_init);
770
771 static inline bool is_pic32_console_port(struct uart_port *port)
772 {
773 return port->cons && port->cons->index == port->line;
774 }
775
776 /*
777 * Late console initialization.
778 */
779 static int __init pic32_late_console_init(void)
780 {
781 if (!(pic32_console.flags & CON_ENABLED))
782 register_console(&pic32_console);
783
784 return 0;
785 }
786
787 core_initcall(pic32_late_console_init);
788
789 #else
790 #define PIC32_SCONSOLE NULL
791 #endif
792
793 static struct uart_driver pic32_uart_driver = {
794 .owner = THIS_MODULE,
795 .driver_name = PIC32_DEV_NAME,
796 .dev_name = PIC32_SDEV_NAME,
797 .nr = PIC32_MAX_UARTS,
798 .cons = PIC32_SCONSOLE,
799 };
800
801 static int pic32_uart_probe(struct platform_device *pdev)
802 {
803 struct device_node *np = pdev->dev.of_node;
804 struct pic32_sport *sport;
805 int uart_idx = 0;
806 struct resource *res_mem;
807 struct uart_port *port;
808 int ret;
809
810 uart_idx = of_alias_get_id(np, "serial");
811 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
812 return -EINVAL;
813
814 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815 if (!res_mem)
816 return -EINVAL;
817
818 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
819 if (!sport)
820 return -ENOMEM;
821
822 sport->idx = uart_idx;
823 sport->irq_fault = irq_of_parse_and_map(np, 0);
824 sport->irqflags_fault = IRQF_NO_THREAD;
825 sport->irq_rx = irq_of_parse_and_map(np, 1);
826 sport->irqflags_rx = IRQF_NO_THREAD;
827 sport->irq_tx = irq_of_parse_and_map(np, 2);
828 sport->irqflags_tx = IRQF_NO_THREAD;
829 sport->clk = devm_clk_get(&pdev->dev, NULL);
830 sport->cts_gpio = -EINVAL;
831 sport->dev = &pdev->dev;
832
833 /* Hardware flow control: gpios
834 * !Note: Basically, CTS is needed for reading the status.
835 */
836 sport->hw_flow_ctrl = false;
837 sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
838 if (gpio_is_valid(sport->cts_gpio)) {
839 sport->hw_flow_ctrl = true;
840
841 ret = devm_gpio_request(sport->dev,
842 sport->cts_gpio, "CTS");
843 if (ret) {
844 dev_err(&pdev->dev,
845 "error requesting CTS GPIO\n");
846 goto err;
847 }
848
849 ret = gpio_direction_input(sport->cts_gpio);
850 if (ret) {
851 dev_err(&pdev->dev, "error setting CTS GPIO\n");
852 goto err;
853 }
854 }
855
856 pic32_sports[uart_idx] = sport;
857 port = &sport->port;
858 memset(port, 0, sizeof(*port));
859 port->iotype = UPIO_MEM;
860 port->mapbase = res_mem->start;
861 port->ops = &pic32_uart_ops;
862 port->flags = UPF_BOOT_AUTOCONF;
863 port->dev = &pdev->dev;
864 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
865 port->uartclk = clk_get_rate(sport->clk);
866 port->line = uart_idx;
867
868 ret = uart_add_one_port(&pic32_uart_driver, port);
869 if (ret) {
870 port->membase = NULL;
871 dev_err(port->dev, "%s: uart add port error!\n", __func__);
872 goto err;
873 }
874
875 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
876 if (is_pic32_console_port(port) &&
877 (pic32_console.flags & CON_ENABLED)) {
878 /* The peripheral clock has been enabled by console_setup,
879 * so disable it till the port is used.
880 */
881 pic32_disable_clock(sport);
882 }
883 #endif
884
885 platform_set_drvdata(pdev, port);
886
887 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
888 __func__, uart_idx);
889
890 return 0;
891 err:
892 /* automatic unroll of sport and gpios */
893 return ret;
894 }
895
896 static int pic32_uart_remove(struct platform_device *pdev)
897 {
898 struct uart_port *port = platform_get_drvdata(pdev);
899 struct pic32_sport *sport = to_pic32_sport(port);
900
901 uart_remove_one_port(&pic32_uart_driver, port);
902 pic32_disable_clock(sport);
903 platform_set_drvdata(pdev, NULL);
904 pic32_sports[sport->idx] = NULL;
905
906 /* automatic unroll of sport and gpios */
907 return 0;
908 }
909
910 static const struct of_device_id pic32_serial_dt_ids[] = {
911 { .compatible = "microchip,pic32mzda-uart" },
912 { /* sentinel */ }
913 };
914 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
915
916 static struct platform_driver pic32_uart_platform_driver = {
917 .probe = pic32_uart_probe,
918 .remove = pic32_uart_remove,
919 .driver = {
920 .name = PIC32_DEV_NAME,
921 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
922 },
923 };
924
925 static int __init pic32_uart_init(void)
926 {
927 int ret;
928
929 ret = uart_register_driver(&pic32_uart_driver);
930 if (ret) {
931 pr_err("failed to register %s:%d\n",
932 pic32_uart_driver.driver_name, ret);
933 return ret;
934 }
935
936 ret = platform_driver_register(&pic32_uart_platform_driver);
937 if (ret) {
938 pr_err("fail to register pic32 uart\n");
939 uart_unregister_driver(&pic32_uart_driver);
940 }
941
942 return ret;
943 }
944 arch_initcall(pic32_uart_init);
945
946 static void __exit pic32_uart_exit(void)
947 {
948 #ifdef CONFIG_SERIAL_PIC32_CONSOLE
949 unregister_console(&pic32_console);
950 #endif
951 platform_driver_unregister(&pic32_uart_platform_driver);
952 uart_unregister_driver(&pic32_uart_driver);
953 }
954 module_exit(pic32_uart_exit);
955
956 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
957 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
958 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support