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Linux 2.6.21-rc3
[linux/fpc-iii.git] / drivers / spi / pxa2xx_spi.c
blob9f2c887ffa0466cf8d30105ed1ee6d5860fa29f4
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/errno.h>
30 #include <linux/delay.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34 #include <asm/hardware.h>
35 #include <asm/delay.h>
36 #include <asm/dma.h>
37
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/pxa-regs.h>
40 #include <asm/arch/pxa2xx_spi.h>
41
42 MODULE_AUTHOR("Stephen Street");
43 MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");
44 MODULE_LICENSE("GPL");
45
46 #define MAX_BUSES 3
47
48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
50 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
51
52 /* for testing SSCR1 changes that require SSP restart, basically
53 * everything except the service and interrupt enables */
54 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
55 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
56 | SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
57 | SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \
58 | SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59
60 #define DEFINE_SSP_REG(reg, off) \
61 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
62 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
63
64 DEFINE_SSP_REG(SSCR0, 0x00)
65 DEFINE_SSP_REG(SSCR1, 0x04)
66 DEFINE_SSP_REG(SSSR, 0x08)
67 DEFINE_SSP_REG(SSITR, 0x0c)
68 DEFINE_SSP_REG(SSDR, 0x10)
69 DEFINE_SSP_REG(SSTO, 0x28)
70 DEFINE_SSP_REG(SSPSP, 0x2c)
71
72 #define START_STATE ((void*)0)
73 #define RUNNING_STATE ((void*)1)
74 #define DONE_STATE ((void*)2)
75 #define ERROR_STATE ((void*)-1)
76
77 #define QUEUE_RUNNING 0
78 #define QUEUE_STOPPED 1
79
80 struct driver_data {
81 /* Driver model hookup */
82 struct platform_device *pdev;
83
84 /* SPI framework hookup */
85 enum pxa_ssp_type ssp_type;
86 struct spi_master *master;
87
88 /* PXA hookup */
89 struct pxa2xx_spi_master *master_info;
90
91 /* DMA setup stuff */
92 int rx_channel;
93 int tx_channel;
94 u32 *null_dma_buf;
95
96 /* SSP register addresses */
97 void *ioaddr;
98 u32 ssdr_physical;
99
100 /* SSP masks*/
101 u32 dma_cr1;
102 u32 int_cr1;
103 u32 clear_sr;
104 u32 mask_sr;
105
106 /* Driver message queue */
107 struct workqueue_struct *workqueue;
108 struct work_struct pump_messages;
109 spinlock_t lock;
110 struct list_head queue;
111 int busy;
112 int run;
113
114 /* Message Transfer pump */
115 struct tasklet_struct pump_transfers;
116
117 /* Current message transfer state info */
118 struct spi_message* cur_msg;
119 struct spi_transfer* cur_transfer;
120 struct chip_data *cur_chip;
121 size_t len;
122 void *tx;
123 void *tx_end;
124 void *rx;
125 void *rx_end;
126 int dma_mapped;
127 dma_addr_t rx_dma;
128 dma_addr_t tx_dma;
129 size_t rx_map_len;
130 size_t tx_map_len;
131 u8 n_bytes;
132 u32 dma_width;
133 int cs_change;
134 int (*write)(struct driver_data *drv_data);
135 int (*read)(struct driver_data *drv_data);
136 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
137 void (*cs_control)(u32 command);
138 };
139
140 struct chip_data {
141 u32 cr0;
142 u32 cr1;
143 u32 psp;
144 u32 timeout;
145 u8 n_bytes;
146 u32 dma_width;
147 u32 dma_burst_size;
148 u32 threshold;
149 u32 dma_threshold;
150 u8 enable_dma;
151 u8 bits_per_word;
152 u32 speed_hz;
153 int (*write)(struct driver_data *drv_data);
154 int (*read)(struct driver_data *drv_data);
155 void (*cs_control)(u32 command);
156 };
157
158 static void pump_messages(struct work_struct *work);
159
160 static int flush(struct driver_data *drv_data)
161 {
162 unsigned long limit = loops_per_jiffy << 1;
163
164 void *reg = drv_data->ioaddr;
165
166 do {
167 while (read_SSSR(reg) & SSSR_RNE) {
168 read_SSDR(reg);
169 }
170 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
171 write_SSSR(SSSR_ROR, reg);
172
173 return limit;
174 }
175
176 static void null_cs_control(u32 command)
177 {
178 }
179
180 static int null_writer(struct driver_data *drv_data)
181 {
182 void *reg = drv_data->ioaddr;
183 u8 n_bytes = drv_data->n_bytes;
184
185 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
186 || (drv_data->tx == drv_data->tx_end))
187 return 0;
188
189 write_SSDR(0, reg);
190 drv_data->tx += n_bytes;
191
192 return 1;
193 }
194
195 static int null_reader(struct driver_data *drv_data)
196 {
197 void *reg = drv_data->ioaddr;
198 u8 n_bytes = drv_data->n_bytes;
199
200 while ((read_SSSR(reg) & SSSR_RNE)
201 && (drv_data->rx < drv_data->rx_end)) {
202 read_SSDR(reg);
203 drv_data->rx += n_bytes;
204 }
205
206 return drv_data->rx == drv_data->rx_end;
207 }
208
209 static int u8_writer(struct driver_data *drv_data)
210 {
211 void *reg = drv_data->ioaddr;
212
213 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
214 || (drv_data->tx == drv_data->tx_end))
215 return 0;
216
217 write_SSDR(*(u8 *)(drv_data->tx), reg);
218 ++drv_data->tx;
219
220 return 1;
221 }
222
223 static int u8_reader(struct driver_data *drv_data)
224 {
225 void *reg = drv_data->ioaddr;
226
227 while ((read_SSSR(reg) & SSSR_RNE)
228 && (drv_data->rx < drv_data->rx_end)) {
229 *(u8 *)(drv_data->rx) = read_SSDR(reg);
230 ++drv_data->rx;
231 }
232
233 return drv_data->rx == drv_data->rx_end;
234 }
235
236 static int u16_writer(struct driver_data *drv_data)
237 {
238 void *reg = drv_data->ioaddr;
239
240 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
241 || (drv_data->tx == drv_data->tx_end))
242 return 0;
243
244 write_SSDR(*(u16 *)(drv_data->tx), reg);
245 drv_data->tx += 2;
246
247 return 1;
248 }
249
250 static int u16_reader(struct driver_data *drv_data)
251 {
252 void *reg = drv_data->ioaddr;
253
254 while ((read_SSSR(reg) & SSSR_RNE)
255 && (drv_data->rx < drv_data->rx_end)) {
256 *(u16 *)(drv_data->rx) = read_SSDR(reg);
257 drv_data->rx += 2;
258 }
259
260 return drv_data->rx == drv_data->rx_end;
261 }
262
263 static int u32_writer(struct driver_data *drv_data)
264 {
265 void *reg = drv_data->ioaddr;
266
267 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
268 || (drv_data->tx == drv_data->tx_end))
269 return 0;
270
271 write_SSDR(*(u32 *)(drv_data->tx), reg);
272 drv_data->tx += 4;
273
274 return 1;
275 }
276
277 static int u32_reader(struct driver_data *drv_data)
278 {
279 void *reg = drv_data->ioaddr;
280
281 while ((read_SSSR(reg) & SSSR_RNE)
282 && (drv_data->rx < drv_data->rx_end)) {
283 *(u32 *)(drv_data->rx) = read_SSDR(reg);
284 drv_data->rx += 4;
285 }
286
287 return drv_data->rx == drv_data->rx_end;
288 }
289
290 static void *next_transfer(struct driver_data *drv_data)
291 {
292 struct spi_message *msg = drv_data->cur_msg;
293 struct spi_transfer *trans = drv_data->cur_transfer;
294
295 /* Move to next transfer */
296 if (trans->transfer_list.next != &msg->transfers) {
297 drv_data->cur_transfer =
298 list_entry(trans->transfer_list.next,
299 struct spi_transfer,
300 transfer_list);
301 return RUNNING_STATE;
302 } else
303 return DONE_STATE;
304 }
305
306 static int map_dma_buffers(struct driver_data *drv_data)
307 {
308 struct spi_message *msg = drv_data->cur_msg;
309 struct device *dev = &msg->spi->dev;
310
311 if (!drv_data->cur_chip->enable_dma)
312 return 0;
313
314 if (msg->is_dma_mapped)
315 return drv_data->rx_dma && drv_data->tx_dma;
316
317 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
318 return 0;
319
320 /* Modify setup if rx buffer is null */
321 if (drv_data->rx == NULL) {
322 *drv_data->null_dma_buf = 0;
323 drv_data->rx = drv_data->null_dma_buf;
324 drv_data->rx_map_len = 4;
325 } else
326 drv_data->rx_map_len = drv_data->len;
327
328
329 /* Modify setup if tx buffer is null */
330 if (drv_data->tx == NULL) {
331 *drv_data->null_dma_buf = 0;
332 drv_data->tx = drv_data->null_dma_buf;
333 drv_data->tx_map_len = 4;
334 } else
335 drv_data->tx_map_len = drv_data->len;
336
337 /* Stream map the rx buffer */
338 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
339 drv_data->rx_map_len,
340 DMA_FROM_DEVICE);
341 if (dma_mapping_error(drv_data->rx_dma))
342 return 0;
343
344 /* Stream map the tx buffer */
345 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
346 drv_data->tx_map_len,
347 DMA_TO_DEVICE);
348
349 if (dma_mapping_error(drv_data->tx_dma)) {
350 dma_unmap_single(dev, drv_data->rx_dma,
351 drv_data->rx_map_len, DMA_FROM_DEVICE);
352 return 0;
353 }
354
355 return 1;
356 }
357
358 static void unmap_dma_buffers(struct driver_data *drv_data)
359 {
360 struct device *dev;
361
362 if (!drv_data->dma_mapped)
363 return;
364
365 if (!drv_data->cur_msg->is_dma_mapped) {
366 dev = &drv_data->cur_msg->spi->dev;
367 dma_unmap_single(dev, drv_data->rx_dma,
368 drv_data->rx_map_len, DMA_FROM_DEVICE);
369 dma_unmap_single(dev, drv_data->tx_dma,
370 drv_data->tx_map_len, DMA_TO_DEVICE);
371 }
372
373 drv_data->dma_mapped = 0;
374 }
375
376 /* caller already set message->status; dma and pio irqs are blocked */
377 static void giveback(struct driver_data *drv_data)
378 {
379 struct spi_transfer* last_transfer;
380 unsigned long flags;
381 struct spi_message *msg;
382
383 spin_lock_irqsave(&drv_data->lock, flags);
384 msg = drv_data->cur_msg;
385 drv_data->cur_msg = NULL;
386 drv_data->cur_transfer = NULL;
387 drv_data->cur_chip = NULL;
388 queue_work(drv_data->workqueue, &drv_data->pump_messages);
389 spin_unlock_irqrestore(&drv_data->lock, flags);
390
391 last_transfer = list_entry(msg->transfers.prev,
392 struct spi_transfer,
393 transfer_list);
394
395 if (!last_transfer->cs_change)
396 drv_data->cs_control(PXA2XX_CS_DEASSERT);
397
398 msg->state = NULL;
399 if (msg->complete)
400 msg->complete(msg->context);
401 }
402
403 static int wait_ssp_rx_stall(void *ioaddr)
404 {
405 unsigned long limit = loops_per_jiffy << 1;
406
407 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
408 cpu_relax();
409
410 return limit;
411 }
412
413 static int wait_dma_channel_stop(int channel)
414 {
415 unsigned long limit = loops_per_jiffy << 1;
416
417 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
418 cpu_relax();
419
420 return limit;
421 }
422
423 void dma_error_stop(struct driver_data *drv_data, const char *msg)
424 {
425 void *reg = drv_data->ioaddr;
426
427 /* Stop and reset */
428 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
429 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
430 write_SSSR(drv_data->clear_sr, reg);
431 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
432 if (drv_data->ssp_type != PXA25x_SSP)
433 write_SSTO(0, reg);
434 flush(drv_data);
435 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
436
437 unmap_dma_buffers(drv_data);
438
439 dev_err(&drv_data->pdev->dev, "%s\n", msg);
440
441 drv_data->cur_msg->state = ERROR_STATE;
442 tasklet_schedule(&drv_data->pump_transfers);
443 }
444
445 static void dma_transfer_complete(struct driver_data *drv_data)
446 {
447 void *reg = drv_data->ioaddr;
448 struct spi_message *msg = drv_data->cur_msg;
449
450 /* Clear and disable interrupts on SSP and DMA channels*/
451 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
452 write_SSSR(drv_data->clear_sr, reg);
453 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
454 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
455
456 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
457 dev_err(&drv_data->pdev->dev,
458 "dma_handler: dma rx channel stop failed\n");
459
460 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
461 dev_err(&drv_data->pdev->dev,
462 "dma_transfer: ssp rx stall failed\n");
463
464 unmap_dma_buffers(drv_data);
465
466 /* update the buffer pointer for the amount completed in dma */
467 drv_data->rx += drv_data->len -
468 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
469
470 /* read trailing data from fifo, it does not matter how many
471 * bytes are in the fifo just read until buffer is full
472 * or fifo is empty, which ever occurs first */
473 drv_data->read(drv_data);
474
475 /* return count of what was actually read */
476 msg->actual_length += drv_data->len -
477 (drv_data->rx_end - drv_data->rx);
478
479 /* Release chip select if requested, transfer delays are
480 * handled in pump_transfers */
481 if (drv_data->cs_change)
482 drv_data->cs_control(PXA2XX_CS_DEASSERT);
483
484 /* Move to next transfer */
485 msg->state = next_transfer(drv_data);
486
487 /* Schedule transfer tasklet */
488 tasklet_schedule(&drv_data->pump_transfers);
489 }
490
491 static void dma_handler(int channel, void *data)
492 {
493 struct driver_data *drv_data = data;
494 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
495
496 if (irq_status & DCSR_BUSERR) {
497
498 if (channel == drv_data->tx_channel)
499 dma_error_stop(drv_data,
500 "dma_handler: "
501 "bad bus address on tx channel");
502 else
503 dma_error_stop(drv_data,
504 "dma_handler: "
505 "bad bus address on rx channel");
506 return;
507 }
508
509 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
510 if ((channel == drv_data->tx_channel)
511 && (irq_status & DCSR_ENDINTR)
512 && (drv_data->ssp_type == PXA25x_SSP)) {
513
514 /* Wait for rx to stall */
515 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
516 dev_err(&drv_data->pdev->dev,
517 "dma_handler: ssp rx stall failed\n");
518
519 /* finish this transfer, start the next */
520 dma_transfer_complete(drv_data);
521 }
522 }
523
524 static irqreturn_t dma_transfer(struct driver_data *drv_data)
525 {
526 u32 irq_status;
527 void *reg = drv_data->ioaddr;
528
529 irq_status = read_SSSR(reg) & drv_data->mask_sr;
530 if (irq_status & SSSR_ROR) {
531 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
532 return IRQ_HANDLED;
533 }
534
535 /* Check for false positive timeout */
536 if ((irq_status & SSSR_TINT)
537 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
538 write_SSSR(SSSR_TINT, reg);
539 return IRQ_HANDLED;
540 }
541
542 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
543
544 /* Clear and disable timeout interrupt, do the rest in
545 * dma_transfer_complete */
546 if (drv_data->ssp_type != PXA25x_SSP)
547 write_SSTO(0, reg);
548
549 /* finish this transfer, start the next */
550 dma_transfer_complete(drv_data);
551
552 return IRQ_HANDLED;
553 }
554
555 /* Opps problem detected */
556 return IRQ_NONE;
557 }
558
559 static void int_error_stop(struct driver_data *drv_data, const char* msg)
560 {
561 void *reg = drv_data->ioaddr;
562
563 /* Stop and reset SSP */
564 write_SSSR(drv_data->clear_sr, reg);
565 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
566 if (drv_data->ssp_type != PXA25x_SSP)
567 write_SSTO(0, reg);
568 flush(drv_data);
569 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
570
571 dev_err(&drv_data->pdev->dev, "%s\n", msg);
572
573 drv_data->cur_msg->state = ERROR_STATE;
574 tasklet_schedule(&drv_data->pump_transfers);
575 }
576
577 static void int_transfer_complete(struct driver_data *drv_data)
578 {
579 void *reg = drv_data->ioaddr;
580
581 /* Stop SSP */
582 write_SSSR(drv_data->clear_sr, reg);
583 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
584 if (drv_data->ssp_type != PXA25x_SSP)
585 write_SSTO(0, reg);
586
587 /* Update total byte transfered return count actual bytes read */
588 drv_data->cur_msg->actual_length += drv_data->len -
589 (drv_data->rx_end - drv_data->rx);
590
591 /* Release chip select if requested, transfer delays are
592 * handled in pump_transfers */
593 if (drv_data->cs_change)
594 drv_data->cs_control(PXA2XX_CS_DEASSERT);
595
596 /* Move to next transfer */
597 drv_data->cur_msg->state = next_transfer(drv_data);
598
599 /* Schedule transfer tasklet */
600 tasklet_schedule(&drv_data->pump_transfers);
601 }
602
603 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
604 {
605 void *reg = drv_data->ioaddr;
606
607 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
608 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
609
610 u32 irq_status = read_SSSR(reg) & irq_mask;
611
612 if (irq_status & SSSR_ROR) {
613 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
614 return IRQ_HANDLED;
615 }
616
617 if (irq_status & SSSR_TINT) {
618 write_SSSR(SSSR_TINT, reg);
619 if (drv_data->read(drv_data)) {
620 int_transfer_complete(drv_data);
621 return IRQ_HANDLED;
622 }
623 }
624
625 /* Drain rx fifo, Fill tx fifo and prevent overruns */
626 do {
627 if (drv_data->read(drv_data)) {
628 int_transfer_complete(drv_data);
629 return IRQ_HANDLED;
630 }
631 } while (drv_data->write(drv_data));
632
633 if (drv_data->read(drv_data)) {
634 int_transfer_complete(drv_data);
635 return IRQ_HANDLED;
636 }
637
638 if (drv_data->tx == drv_data->tx_end) {
639 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
640 /* PXA25x_SSP has no timeout, read trailing bytes */
641 if (drv_data->ssp_type == PXA25x_SSP) {
642 if (!wait_ssp_rx_stall(reg))
643 {
644 int_error_stop(drv_data, "interrupt_transfer: "
645 "rx stall failed");
646 return IRQ_HANDLED;
647 }
648 if (!drv_data->read(drv_data))
649 {
650 int_error_stop(drv_data,
651 "interrupt_transfer: "
652 "trailing byte read failed");
653 return IRQ_HANDLED;
654 }
655 int_transfer_complete(drv_data);
656 }
657 }
658
659 /* We did something */
660 return IRQ_HANDLED;
661 }
662
663 static irqreturn_t ssp_int(int irq, void *dev_id)
664 {
665 struct driver_data *drv_data = dev_id;
666 void *reg = drv_data->ioaddr;
667
668 if (!drv_data->cur_msg) {
669
670 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
671 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
672 if (drv_data->ssp_type != PXA25x_SSP)
673 write_SSTO(0, reg);
674 write_SSSR(drv_data->clear_sr, reg);
675
676 dev_err(&drv_data->pdev->dev, "bad message state "
677 "in interrupt handler\n");
678
679 /* Never fail */
680 return IRQ_HANDLED;
681 }
682
683 return drv_data->transfer_handler(drv_data);
684 }
685
686 int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
687 u8 bits_per_word, u32 *burst_code,
688 u32 *threshold)
689 {
690 struct pxa2xx_spi_chip *chip_info =
691 (struct pxa2xx_spi_chip *)spi->controller_data;
692 int bytes_per_word;
693 int burst_bytes;
694 int thresh_words;
695 int req_burst_size;
696 int retval = 0;
697
698 /* Set the threshold (in registers) to equal the same amount of data
699 * as represented by burst size (in bytes). The computation below
700 * is (burst_size rounded up to nearest 8 byte, word or long word)
701 * divided by (bytes/register); the tx threshold is the inverse of
702 * the rx, so that there will always be enough data in the rx fifo
703 * to satisfy a burst, and there will always be enough space in the
704 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
705 * there is not enough space), there must always remain enough empty
706 * space in the rx fifo for any data loaded to the tx fifo.
707 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
708 * will be 8, or half the fifo;
709 * The threshold can only be set to 2, 4 or 8, but not 16, because
710 * to burst 16 to the tx fifo, the fifo would have to be empty;
711 * however, the minimum fifo trigger level is 1, and the tx will
712 * request service when the fifo is at this level, with only 15 spaces.
713 */
714
715 /* find bytes/word */
716 if (bits_per_word <= 8)
717 bytes_per_word = 1;
718 else if (bits_per_word <= 16)
719 bytes_per_word = 2;
720 else
721 bytes_per_word = 4;
722
723 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
724 if (chip_info)
725 req_burst_size = chip_info->dma_burst_size;
726 else {
727 switch (chip->dma_burst_size) {
728 default:
729 /* if the default burst size is not set,
730 * do it now */
731 chip->dma_burst_size = DCMD_BURST8;
732 case DCMD_BURST8:
733 req_burst_size = 8;
734 break;
735 case DCMD_BURST16:
736 req_burst_size = 16;
737 break;
738 case DCMD_BURST32:
739 req_burst_size = 32;
740 break;
741 }
742 }
743 if (req_burst_size <= 8) {
744 *burst_code = DCMD_BURST8;
745 burst_bytes = 8;
746 } else if (req_burst_size <= 16) {
747 if (bytes_per_word == 1) {
748 /* don't burst more than 1/2 the fifo */
749 *burst_code = DCMD_BURST8;
750 burst_bytes = 8;
751 retval = 1;
752 } else {
753 *burst_code = DCMD_BURST16;
754 burst_bytes = 16;
755 }
756 } else {
757 if (bytes_per_word == 1) {
758 /* don't burst more than 1/2 the fifo */
759 *burst_code = DCMD_BURST8;
760 burst_bytes = 8;
761 retval = 1;
762 } else if (bytes_per_word == 2) {
763 /* don't burst more than 1/2 the fifo */
764 *burst_code = DCMD_BURST16;
765 burst_bytes = 16;
766 retval = 1;
767 } else {
768 *burst_code = DCMD_BURST32;
769 burst_bytes = 32;
770 }
771 }
772
773 thresh_words = burst_bytes / bytes_per_word;
774
775 /* thresh_words will be between 2 and 8 */
776 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
777 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
778
779 return retval;
780 }
781
782 static void pump_transfers(unsigned long data)
783 {
784 struct driver_data *drv_data = (struct driver_data *)data;
785 struct spi_message *message = NULL;
786 struct spi_transfer *transfer = NULL;
787 struct spi_transfer *previous = NULL;
788 struct chip_data *chip = NULL;
789 void *reg = drv_data->ioaddr;
790 u32 clk_div = 0;
791 u8 bits = 0;
792 u32 speed = 0;
793 u32 cr0;
794 u32 cr1;
795 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
796 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
797
798 /* Get current state information */
799 message = drv_data->cur_msg;
800 transfer = drv_data->cur_transfer;
801 chip = drv_data->cur_chip;
802
803 /* Handle for abort */
804 if (message->state == ERROR_STATE) {
805 message->status = -EIO;
806 giveback(drv_data);
807 return;
808 }
809
810 /* Handle end of message */
811 if (message->state == DONE_STATE) {
812 message->status = 0;
813 giveback(drv_data);
814 return;
815 }
816
817 /* Delay if requested at end of transfer*/
818 if (message->state == RUNNING_STATE) {
819 previous = list_entry(transfer->transfer_list.prev,
820 struct spi_transfer,
821 transfer_list);
822 if (previous->delay_usecs)
823 udelay(previous->delay_usecs);
824 }
825
826 /* Check transfer length */
827 if (transfer->len > 8191)
828 {
829 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
830 "length greater than 8191\n");
831 message->status = -EINVAL;
832 giveback(drv_data);
833 return;
834 }
835
836 /* Setup the transfer state based on the type of transfer */
837 if (flush(drv_data) == 0) {
838 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
839 message->status = -EIO;
840 giveback(drv_data);
841 return;
842 }
843 drv_data->n_bytes = chip->n_bytes;
844 drv_data->dma_width = chip->dma_width;
845 drv_data->cs_control = chip->cs_control;
846 drv_data->tx = (void *)transfer->tx_buf;
847 drv_data->tx_end = drv_data->tx + transfer->len;
848 drv_data->rx = transfer->rx_buf;
849 drv_data->rx_end = drv_data->rx + transfer->len;
850 drv_data->rx_dma = transfer->rx_dma;
851 drv_data->tx_dma = transfer->tx_dma;
852 drv_data->len = transfer->len & DCMD_LENGTH;
853 drv_data->write = drv_data->tx ? chip->write : null_writer;
854 drv_data->read = drv_data->rx ? chip->read : null_reader;
855 drv_data->cs_change = transfer->cs_change;
856
857 /* Change speed and bit per word on a per transfer */
858 cr0 = chip->cr0;
859 if (transfer->speed_hz || transfer->bits_per_word) {
860
861 bits = chip->bits_per_word;
862 speed = chip->speed_hz;
863
864 if (transfer->speed_hz)
865 speed = transfer->speed_hz;
866
867 if (transfer->bits_per_word)
868 bits = transfer->bits_per_word;
869
870 if (reg == SSP1_VIRT)
871 clk_div = SSP1_SerClkDiv(speed);
872 else if (reg == SSP2_VIRT)
873 clk_div = SSP2_SerClkDiv(speed);
874 else if (reg == SSP3_VIRT)
875 clk_div = SSP3_SerClkDiv(speed);
876
877 if (bits <= 8) {
878 drv_data->n_bytes = 1;
879 drv_data->dma_width = DCMD_WIDTH1;
880 drv_data->read = drv_data->read != null_reader ?
881 u8_reader : null_reader;
882 drv_data->write = drv_data->write != null_writer ?
883 u8_writer : null_writer;
884 } else if (bits <= 16) {
885 drv_data->n_bytes = 2;
886 drv_data->dma_width = DCMD_WIDTH2;
887 drv_data->read = drv_data->read != null_reader ?
888 u16_reader : null_reader;
889 drv_data->write = drv_data->write != null_writer ?
890 u16_writer : null_writer;
891 } else if (bits <= 32) {
892 drv_data->n_bytes = 4;
893 drv_data->dma_width = DCMD_WIDTH4;
894 drv_data->read = drv_data->read != null_reader ?
895 u32_reader : null_reader;
896 drv_data->write = drv_data->write != null_writer ?
897 u32_writer : null_writer;
898 }
899 /* if bits/word is changed in dma mode, then must check the
900 * thresholds and burst also */
901 if (chip->enable_dma) {
902 if (set_dma_burst_and_threshold(chip, message->spi,
903 bits, &dma_burst,
904 &dma_thresh))
905 if (printk_ratelimit())
906 dev_warn(&message->spi->dev,
907 "pump_transfer: "
908 "DMA burst size reduced to "
909 "match bits_per_word\n");
910 }
911
912 cr0 = clk_div
913 | SSCR0_Motorola
914 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
915 | SSCR0_SSE
916 | (bits > 16 ? SSCR0_EDSS : 0);
917 }
918
919 message->state = RUNNING_STATE;
920
921 /* Try to map dma buffer and do a dma transfer if successful */
922 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
923
924 /* Ensure we have the correct interrupt handler */
925 drv_data->transfer_handler = dma_transfer;
926
927 /* Setup rx DMA Channel */
928 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
929 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
930 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
931 if (drv_data->rx == drv_data->null_dma_buf)
932 /* No target address increment */
933 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
934 | drv_data->dma_width
935 | dma_burst
936 | drv_data->len;
937 else
938 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
939 | DCMD_FLOWSRC
940 | drv_data->dma_width
941 | dma_burst
942 | drv_data->len;
943
944 /* Setup tx DMA Channel */
945 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
946 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
947 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
948 if (drv_data->tx == drv_data->null_dma_buf)
949 /* No source address increment */
950 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
951 | drv_data->dma_width
952 | dma_burst
953 | drv_data->len;
954 else
955 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
956 | DCMD_FLOWTRG
957 | drv_data->dma_width
958 | dma_burst
959 | drv_data->len;
960
961 /* Enable dma end irqs on SSP to detect end of transfer */
962 if (drv_data->ssp_type == PXA25x_SSP)
963 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
964
965 /* Fix me, need to handle cs polarity */
966 drv_data->cs_control(PXA2XX_CS_ASSERT);
967
968 /* Clear status and start DMA engine */
969 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
970 write_SSSR(drv_data->clear_sr, reg);
971 DCSR(drv_data->rx_channel) |= DCSR_RUN;
972 DCSR(drv_data->tx_channel) |= DCSR_RUN;
973 } else {
974 /* Ensure we have the correct interrupt handler */
975 drv_data->transfer_handler = interrupt_transfer;
976
977 /* Fix me, need to handle cs polarity */
978 drv_data->cs_control(PXA2XX_CS_ASSERT);
979
980 /* Clear status */
981 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
982 write_SSSR(drv_data->clear_sr, reg);
983 }
984
985 /* see if we need to reload the config registers */
986 if ((read_SSCR0(reg) != cr0)
987 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
988 (cr1 & SSCR1_CHANGE_MASK)) {
989
990 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
991 if (drv_data->ssp_type != PXA25x_SSP)
992 write_SSTO(chip->timeout, reg);
993 write_SSCR1(cr1, reg);
994 write_SSCR0(cr0, reg);
995 } else {
996 if (drv_data->ssp_type != PXA25x_SSP)
997 write_SSTO(chip->timeout, reg);
998 write_SSCR1(cr1, reg);
999 }
1000 }
1001
1002 static void pump_messages(struct work_struct *work)
1003 {
1004 struct driver_data *drv_data =
1005 container_of(work, struct driver_data, pump_messages);
1006 unsigned long flags;
1007
1008 /* Lock queue and check for queue work */
1009 spin_lock_irqsave(&drv_data->lock, flags);
1010 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1011 drv_data->busy = 0;
1012 spin_unlock_irqrestore(&drv_data->lock, flags);
1013 return;
1014 }
1015
1016 /* Make sure we are not already running a message */
1017 if (drv_data->cur_msg) {
1018 spin_unlock_irqrestore(&drv_data->lock, flags);
1019 return;
1020 }
1021
1022 /* Extract head of queue */
1023 drv_data->cur_msg = list_entry(drv_data->queue.next,
1024 struct spi_message, queue);
1025 list_del_init(&drv_data->cur_msg->queue);
1026
1027 /* Initial message state*/
1028 drv_data->cur_msg->state = START_STATE;
1029 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1030 struct spi_transfer,
1031 transfer_list);
1032
1033 /* prepare to setup the SSP, in pump_transfers, using the per
1034 * chip configuration */
1035 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1036
1037 /* Mark as busy and launch transfers */
1038 tasklet_schedule(&drv_data->pump_transfers);
1039
1040 drv_data->busy = 1;
1041 spin_unlock_irqrestore(&drv_data->lock, flags);
1042 }
1043
1044 static int transfer(struct spi_device *spi, struct spi_message *msg)
1045 {
1046 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1047 unsigned long flags;
1048
1049 spin_lock_irqsave(&drv_data->lock, flags);
1050
1051 if (drv_data->run == QUEUE_STOPPED) {
1052 spin_unlock_irqrestore(&drv_data->lock, flags);
1053 return -ESHUTDOWN;
1054 }
1055
1056 msg->actual_length = 0;
1057 msg->status = -EINPROGRESS;
1058 msg->state = START_STATE;
1059
1060 list_add_tail(&msg->queue, &drv_data->queue);
1061
1062 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1063 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1064
1065 spin_unlock_irqrestore(&drv_data->lock, flags);
1066
1067 return 0;
1068 }
1069
1070 static int setup(struct spi_device *spi)
1071 {
1072 struct pxa2xx_spi_chip *chip_info = NULL;
1073 struct chip_data *chip;
1074 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1075 unsigned int clk_div;
1076
1077 if (!spi->bits_per_word)
1078 spi->bits_per_word = 8;
1079
1080 if (drv_data->ssp_type != PXA25x_SSP
1081 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1082 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1083 "b/w not 4-32 for type non-PXA25x_SSP\n",
1084 drv_data->ssp_type, spi->bits_per_word);
1085 return -EINVAL;
1086 }
1087 else if (drv_data->ssp_type == PXA25x_SSP
1088 && (spi->bits_per_word < 4
1089 || spi->bits_per_word > 16)) {
1090 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1091 "b/w not 4-16 for type PXA25x_SSP\n",
1092 drv_data->ssp_type, spi->bits_per_word);
1093 return -EINVAL;
1094 }
1095
1096 /* Only alloc on first setup */
1097 chip = spi_get_ctldata(spi);
1098 if (!chip) {
1099 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1100 if (!chip) {
1101 dev_err(&spi->dev,
1102 "failed setup: can't allocate chip data\n");
1103 return -ENOMEM;
1104 }
1105
1106 chip->cs_control = null_cs_control;
1107 chip->enable_dma = 0;
1108 chip->timeout = 1000;
1109 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1110 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1111 DCMD_BURST8 : 0;
1112 }
1113
1114 /* protocol drivers may change the chip settings, so...
1115 * if chip_info exists, use it */
1116 chip_info = spi->controller_data;
1117
1118 /* chip_info isn't always needed */
1119 chip->cr1 = 0;
1120 if (chip_info) {
1121 if (chip_info->cs_control)
1122 chip->cs_control = chip_info->cs_control;
1123
1124 chip->timeout = chip_info->timeout;
1125
1126 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1127 SSCR1_RFT) |
1128 (SSCR1_TxTresh(chip_info->tx_threshold) &
1129 SSCR1_TFT);
1130
1131 chip->enable_dma = chip_info->dma_burst_size != 0
1132 && drv_data->master_info->enable_dma;
1133 chip->dma_threshold = 0;
1134
1135 if (chip_info->enable_loopback)
1136 chip->cr1 = SSCR1_LBM;
1137 }
1138
1139 /* set dma burst and threshold outside of chip_info path so that if
1140 * chip_info goes away after setting chip->enable_dma, the
1141 * burst and threshold can still respond to changes in bits_per_word */
1142 if (chip->enable_dma) {
1143 /* set up legal burst and threshold for dma */
1144 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1145 &chip->dma_burst_size,
1146 &chip->dma_threshold)) {
1147 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1148 "to match bits_per_word\n");
1149 }
1150 }
1151
1152 if (drv_data->ioaddr == SSP1_VIRT)
1153 clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
1154 else if (drv_data->ioaddr == SSP2_VIRT)
1155 clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
1156 else if (drv_data->ioaddr == SSP3_VIRT)
1157 clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
1158 else
1159 {
1160 dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n",
1161 drv_data->ioaddr);
1162 return -ENODEV;
1163 }
1164 chip->speed_hz = spi->max_speed_hz;
1165
1166 chip->cr0 = clk_div
1167 | SSCR0_Motorola
1168 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1169 spi->bits_per_word - 16 : spi->bits_per_word)
1170 | SSCR0_SSE
1171 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1172 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1173 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1174 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1175
1176 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1177 if (drv_data->ssp_type != PXA25x_SSP)
1178 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1179 spi->bits_per_word,
1180 (CLOCK_SPEED_HZ)
1181 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1182 spi->mode & 0x3);
1183 else
1184 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1185 spi->bits_per_word,
1186 (CLOCK_SPEED_HZ/2)
1187 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1188 spi->mode & 0x3);
1189
1190 if (spi->bits_per_word <= 8) {
1191 chip->n_bytes = 1;
1192 chip->dma_width = DCMD_WIDTH1;
1193 chip->read = u8_reader;
1194 chip->write = u8_writer;
1195 } else if (spi->bits_per_word <= 16) {
1196 chip->n_bytes = 2;
1197 chip->dma_width = DCMD_WIDTH2;
1198 chip->read = u16_reader;
1199 chip->write = u16_writer;
1200 } else if (spi->bits_per_word <= 32) {
1201 chip->cr0 |= SSCR0_EDSS;
1202 chip->n_bytes = 4;
1203 chip->dma_width = DCMD_WIDTH4;
1204 chip->read = u32_reader;
1205 chip->write = u32_writer;
1206 } else {
1207 dev_err(&spi->dev, "invalid wordsize\n");
1208 return -ENODEV;
1209 }
1210 chip->bits_per_word = spi->bits_per_word;
1211
1212 spi_set_ctldata(spi, chip);
1213
1214 return 0;
1215 }
1216
1217 static void cleanup(struct spi_device *spi)
1218 {
1219 struct chip_data *chip = spi_get_ctldata(spi);
1220
1221 kfree(chip);
1222 }
1223
1224 static int init_queue(struct driver_data *drv_data)
1225 {
1226 INIT_LIST_HEAD(&drv_data->queue);
1227 spin_lock_init(&drv_data->lock);
1228
1229 drv_data->run = QUEUE_STOPPED;
1230 drv_data->busy = 0;
1231
1232 tasklet_init(&drv_data->pump_transfers,
1233 pump_transfers, (unsigned long)drv_data);
1234
1235 INIT_WORK(&drv_data->pump_messages, pump_messages);
1236 drv_data->workqueue = create_singlethread_workqueue(
1237 drv_data->master->cdev.dev->bus_id);
1238 if (drv_data->workqueue == NULL)
1239 return -EBUSY;
1240
1241 return 0;
1242 }
1243
1244 static int start_queue(struct driver_data *drv_data)
1245 {
1246 unsigned long flags;
1247
1248 spin_lock_irqsave(&drv_data->lock, flags);
1249
1250 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1251 spin_unlock_irqrestore(&drv_data->lock, flags);
1252 return -EBUSY;
1253 }
1254
1255 drv_data->run = QUEUE_RUNNING;
1256 drv_data->cur_msg = NULL;
1257 drv_data->cur_transfer = NULL;
1258 drv_data->cur_chip = NULL;
1259 spin_unlock_irqrestore(&drv_data->lock, flags);
1260
1261 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1262
1263 return 0;
1264 }
1265
1266 static int stop_queue(struct driver_data *drv_data)
1267 {
1268 unsigned long flags;
1269 unsigned limit = 500;
1270 int status = 0;
1271
1272 spin_lock_irqsave(&drv_data->lock, flags);
1273
1274 /* This is a bit lame, but is optimized for the common execution path.
1275 * A wait_queue on the drv_data->busy could be used, but then the common
1276 * execution path (pump_messages) would be required to call wake_up or
1277 * friends on every SPI message. Do this instead */
1278 drv_data->run = QUEUE_STOPPED;
1279 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1280 spin_unlock_irqrestore(&drv_data->lock, flags);
1281 msleep(10);
1282 spin_lock_irqsave(&drv_data->lock, flags);
1283 }
1284
1285 if (!list_empty(&drv_data->queue) || drv_data->busy)
1286 status = -EBUSY;
1287
1288 spin_unlock_irqrestore(&drv_data->lock, flags);
1289
1290 return status;
1291 }
1292
1293 static int destroy_queue(struct driver_data *drv_data)
1294 {
1295 int status;
1296
1297 status = stop_queue(drv_data);
1298 /* we are unloading the module or failing to load (only two calls
1299 * to this routine), and neither call can handle a return value.
1300 * However, destroy_workqueue calls flush_workqueue, and that will
1301 * block until all work is done. If the reason that stop_queue
1302 * timed out is that the work will never finish, then it does no
1303 * good to call destroy_workqueue, so return anyway. */
1304 if (status != 0)
1305 return status;
1306
1307 destroy_workqueue(drv_data->workqueue);
1308
1309 return 0;
1310 }
1311
1312 static int pxa2xx_spi_probe(struct platform_device *pdev)
1313 {
1314 struct device *dev = &pdev->dev;
1315 struct pxa2xx_spi_master *platform_info;
1316 struct spi_master *master;
1317 struct driver_data *drv_data = 0;
1318 struct resource *memory_resource;
1319 int irq;
1320 int status = 0;
1321
1322 platform_info = dev->platform_data;
1323
1324 if (platform_info->ssp_type == SSP_UNDEFINED) {
1325 dev_err(&pdev->dev, "undefined SSP\n");
1326 return -ENODEV;
1327 }
1328
1329 /* Allocate master with space for drv_data and null dma buffer */
1330 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1331 if (!master) {
1332 dev_err(&pdev->dev, "can not alloc spi_master\n");
1333 return -ENOMEM;
1334 }
1335 drv_data = spi_master_get_devdata(master);
1336 drv_data->master = master;
1337 drv_data->master_info = platform_info;
1338 drv_data->pdev = pdev;
1339
1340 master->bus_num = pdev->id;
1341 master->num_chipselect = platform_info->num_chipselect;
1342 master->cleanup = cleanup;
1343 master->setup = setup;
1344 master->transfer = transfer;
1345
1346 drv_data->ssp_type = platform_info->ssp_type;
1347 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1348 sizeof(struct driver_data)), 8);
1349
1350 /* Setup register addresses */
1351 memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352 if (!memory_resource) {
1353 dev_err(&pdev->dev, "memory resources not defined\n");
1354 status = -ENODEV;
1355 goto out_error_master_alloc;
1356 }
1357
1358 drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));
1359 drv_data->ssdr_physical = memory_resource->start + 0x00000010;
1360 if (platform_info->ssp_type == PXA25x_SSP) {
1361 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1362 drv_data->dma_cr1 = 0;
1363 drv_data->clear_sr = SSSR_ROR;
1364 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1365 } else {
1366 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1367 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1368 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1369 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1370 }
1371
1372 /* Attach to IRQ */
1373 irq = platform_get_irq(pdev, 0);
1374 if (irq < 0) {
1375 dev_err(&pdev->dev, "irq resource not defined\n");
1376 status = -ENODEV;
1377 goto out_error_master_alloc;
1378 }
1379
1380 status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);
1381 if (status < 0) {
1382 dev_err(&pdev->dev, "can not get IRQ\n");
1383 goto out_error_master_alloc;
1384 }
1385
1386 /* Setup DMA if requested */
1387 drv_data->tx_channel = -1;
1388 drv_data->rx_channel = -1;
1389 if (platform_info->enable_dma) {
1390
1391 /* Get two DMA channels (rx and tx) */
1392 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1393 DMA_PRIO_HIGH,
1394 dma_handler,
1395 drv_data);
1396 if (drv_data->rx_channel < 0) {
1397 dev_err(dev, "problem (%d) requesting rx channel\n",
1398 drv_data->rx_channel);
1399 status = -ENODEV;
1400 goto out_error_irq_alloc;
1401 }
1402 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1403 DMA_PRIO_MEDIUM,
1404 dma_handler,
1405 drv_data);
1406 if (drv_data->tx_channel < 0) {
1407 dev_err(dev, "problem (%d) requesting tx channel\n",
1408 drv_data->tx_channel);
1409 status = -ENODEV;
1410 goto out_error_dma_alloc;
1411 }
1412
1413 if (drv_data->ioaddr == SSP1_VIRT) {
1414 DRCMRRXSSDR = DRCMR_MAPVLD
1415 | drv_data->rx_channel;
1416 DRCMRTXSSDR = DRCMR_MAPVLD
1417 | drv_data->tx_channel;
1418 } else if (drv_data->ioaddr == SSP2_VIRT) {
1419 DRCMRRXSS2DR = DRCMR_MAPVLD
1420 | drv_data->rx_channel;
1421 DRCMRTXSS2DR = DRCMR_MAPVLD
1422 | drv_data->tx_channel;
1423 } else if (drv_data->ioaddr == SSP3_VIRT) {
1424 DRCMRRXSS3DR = DRCMR_MAPVLD
1425 | drv_data->rx_channel;
1426 DRCMRTXSS3DR = DRCMR_MAPVLD
1427 | drv_data->tx_channel;
1428 } else {
1429 dev_err(dev, "bad SSP type\n");
1430 goto out_error_dma_alloc;
1431 }
1432 }
1433
1434 /* Enable SOC clock */
1435 pxa_set_cken(platform_info->clock_enable, 1);
1436
1437 /* Load default SSP configuration */
1438 write_SSCR0(0, drv_data->ioaddr);
1439 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1440 write_SSCR0(SSCR0_SerClkDiv(2)
1441 | SSCR0_Motorola
1442 | SSCR0_DataSize(8),
1443 drv_data->ioaddr);
1444 if (drv_data->ssp_type != PXA25x_SSP)
1445 write_SSTO(0, drv_data->ioaddr);
1446 write_SSPSP(0, drv_data->ioaddr);
1447
1448 /* Initial and start queue */
1449 status = init_queue(drv_data);
1450 if (status != 0) {
1451 dev_err(&pdev->dev, "problem initializing queue\n");
1452 goto out_error_clock_enabled;
1453 }
1454 status = start_queue(drv_data);
1455 if (status != 0) {
1456 dev_err(&pdev->dev, "problem starting queue\n");
1457 goto out_error_clock_enabled;
1458 }
1459
1460 /* Register with the SPI framework */
1461 platform_set_drvdata(pdev, drv_data);
1462 status = spi_register_master(master);
1463 if (status != 0) {
1464 dev_err(&pdev->dev, "problem registering spi master\n");
1465 goto out_error_queue_alloc;
1466 }
1467
1468 return status;
1469
1470 out_error_queue_alloc:
1471 destroy_queue(drv_data);
1472
1473 out_error_clock_enabled:
1474 pxa_set_cken(platform_info->clock_enable, 0);
1475
1476 out_error_dma_alloc:
1477 if (drv_data->tx_channel != -1)
1478 pxa_free_dma(drv_data->tx_channel);
1479 if (drv_data->rx_channel != -1)
1480 pxa_free_dma(drv_data->rx_channel);
1481
1482 out_error_irq_alloc:
1483 free_irq(irq, drv_data);
1484
1485 out_error_master_alloc:
1486 spi_master_put(master);
1487 return status;
1488 }
1489
1490 static int pxa2xx_spi_remove(struct platform_device *pdev)
1491 {
1492 struct driver_data *drv_data = platform_get_drvdata(pdev);
1493 int irq;
1494 int status = 0;
1495
1496 if (!drv_data)
1497 return 0;
1498
1499 /* Remove the queue */
1500 status = destroy_queue(drv_data);
1501 if (status != 0)
1502 /* the kernel does not check the return status of this
1503 * this routine (mod->exit, within the kernel). Therefore
1504 * nothing is gained by returning from here, the module is
1505 * going away regardless, and we should not leave any more
1506 * resources allocated than necessary. We cannot free the
1507 * message memory in drv_data->queue, but we can release the
1508 * resources below. I think the kernel should honor -EBUSY
1509 * returns but... */
1510 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1511 "complete, message memory not freed\n");
1512
1513 /* Disable the SSP at the peripheral and SOC level */
1514 write_SSCR0(0, drv_data->ioaddr);
1515 pxa_set_cken(drv_data->master_info->clock_enable, 0);
1516
1517 /* Release DMA */
1518 if (drv_data->master_info->enable_dma) {
1519 if (drv_data->ioaddr == SSP1_VIRT) {
1520 DRCMRRXSSDR = 0;
1521 DRCMRTXSSDR = 0;
1522 } else if (drv_data->ioaddr == SSP2_VIRT) {
1523 DRCMRRXSS2DR = 0;
1524 DRCMRTXSS2DR = 0;
1525 } else if (drv_data->ioaddr == SSP3_VIRT) {
1526 DRCMRRXSS3DR = 0;
1527 DRCMRTXSS3DR = 0;
1528 }
1529 pxa_free_dma(drv_data->tx_channel);
1530 pxa_free_dma(drv_data->rx_channel);
1531 }
1532
1533 /* Release IRQ */
1534 irq = platform_get_irq(pdev, 0);
1535 if (irq >= 0)
1536 free_irq(irq, drv_data);
1537
1538 /* Disconnect from the SPI framework */
1539 spi_unregister_master(drv_data->master);
1540
1541 /* Prevent double remove */
1542 platform_set_drvdata(pdev, NULL);
1543
1544 return 0;
1545 }
1546
1547 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1548 {
1549 int status = 0;
1550
1551 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1552 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1553 }
1554
1555 #ifdef CONFIG_PM
1556 static int suspend_devices(struct device *dev, void *pm_message)
1557 {
1558 pm_message_t *state = pm_message;
1559
1560 if (dev->power.power_state.event != state->event) {
1561 dev_warn(dev, "pm state does not match request\n");
1562 return -1;
1563 }
1564
1565 return 0;
1566 }
1567
1568 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1569 {
1570 struct driver_data *drv_data = platform_get_drvdata(pdev);
1571 int status = 0;
1572
1573 /* Check all childern for current power state */
1574 if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
1575 dev_warn(&pdev->dev, "suspend aborted\n");
1576 return -1;
1577 }
1578
1579 status = stop_queue(drv_data);
1580 if (status != 0)
1581 return status;
1582 write_SSCR0(0, drv_data->ioaddr);
1583 pxa_set_cken(drv_data->master_info->clock_enable, 0);
1584
1585 return 0;
1586 }
1587
1588 static int pxa2xx_spi_resume(struct platform_device *pdev)
1589 {
1590 struct driver_data *drv_data = platform_get_drvdata(pdev);
1591 int status = 0;
1592
1593 /* Enable the SSP clock */
1594 pxa_set_cken(drv_data->master_info->clock_enable, 1);
1595
1596 /* Start the queue running */
1597 status = start_queue(drv_data);
1598 if (status != 0) {
1599 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1600 return status;
1601 }
1602
1603 return 0;
1604 }
1605 #else
1606 #define pxa2xx_spi_suspend NULL
1607 #define pxa2xx_spi_resume NULL
1608 #endif /* CONFIG_PM */
1609
1610 static struct platform_driver driver = {
1611 .driver = {
1612 .name = "pxa2xx-spi",
1613 .bus = &platform_bus_type,
1614 .owner = THIS_MODULE,
1615 },
1616 .probe = pxa2xx_spi_probe,
1617 .remove = __devexit_p(pxa2xx_spi_remove),
1618 .shutdown = pxa2xx_spi_shutdown,
1619 .suspend = pxa2xx_spi_suspend,
1620 .resume = pxa2xx_spi_resume,
1621 };
1622
1623 static int __init pxa2xx_spi_init(void)
1624 {
1625 platform_driver_register(&driver);
1626
1627 return 0;
1628 }
1629 module_init(pxa2xx_spi_init);
1630
1631 static void __exit pxa2xx_spi_exit(void)
1632 {
1633 platform_driver_unregister(&driver);
1634 }
1635 module_exit(pxa2xx_spi_exit);
Linux with added FPC-III support