?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 2.6.21-rc3
[linux/fpc-iii.git] / drivers / video / aty / aty128fb.c
blobe86d7e0c98254eaa3af3370e52d789b437a765c8
1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43 /*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/kernel.h>
52 #include <linux/errno.h>
53 #include <linux/string.h>
54 #include <linux/mm.h>
55 #include <linux/slab.h>
56 #include <linux/vmalloc.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <asm/uaccess.h>
60 #include <linux/fb.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/ioport.h>
64 #include <linux/console.h>
65 #include <linux/backlight.h>
66 #include <asm/io.h>
67
68 #ifdef CONFIG_PPC_PMAC
69 #include <asm/machdep.h>
70 #include <asm/pmac_feature.h>
71 #include <asm/prom.h>
72 #include <asm/pci-bridge.h>
73 #include "../macmodes.h"
74 #endif
75
76 #ifdef CONFIG_PMAC_BACKLIGHT
77 #include <asm/backlight.h>
78 #endif
79
80 #ifdef CONFIG_BOOTX_TEXT
81 #include <asm/btext.h>
82 #endif /* CONFIG_BOOTX_TEXT */
83
84 #ifdef CONFIG_MTRR
85 #include <asm/mtrr.h>
86 #endif
87
88 #include <video/aty128.h>
89
90 /* Debug flag */
91 #undef DEBUG
92
93 #ifdef DEBUG
94 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
95 #else
96 #define DBG(fmt, args...)
97 #endif
98
99 #ifndef CONFIG_PPC_PMAC
100 /* default mode */
101 static struct fb_var_screeninfo default_var __devinitdata = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107 };
108
109 #else /* CONFIG_PPC_PMAC */
110 /* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112 static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119 };
120 #endif /* CONFIG_PPC_PMAC */
121
122 /* default modedb mode */
123 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124 static struct fb_videomode defaultmode __devinitdata = {
125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137 };
138
139 /* Chip generations */
140 enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149 };
150
151 /* Must match above enum */
152 static const char *r128_family[] __devinitdata = {
153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161 };
162
163 /*
164 * PCI driver prototypes
165 */
166 static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168 static void aty128_remove(struct pci_dev *pdev);
169 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170 static int aty128_pci_resume(struct pci_dev *pdev);
171 static int aty128_do_resume(struct pci_dev *pdev);
172
173 /* supported Rage128 chipsets */
174 static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270 };
271
272 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274 static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = __devexit_p(aty128_remove),
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281 };
282
283 /* packed BIOS settings */
284 #ifndef CONFIG_PPC
285 typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308 } __attribute__ ((packed)) PLL_BLOCK;
309 #endif /* !CONFIG_PPC */
310
311 /* onboard memory information */
312 struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324 };
325
326 /* various memory configurations */
327 static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329 static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331 static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333 static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
335
336 static struct fb_fix_screeninfo aty128fb_fix __devinitdata = {
337 .id = "ATY Rage128",
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
340 .xpanstep = 8,
341 .ypanstep = 1,
342 .mmio_len = 0x2000,
343 .accel = FB_ACCEL_ATI_RAGE128,
344 };
345
346 static char *mode_option __devinitdata = NULL;
347
348 #ifdef CONFIG_PPC_PMAC
349 static int default_vmode __devinitdata = VMODE_1024_768_60;
350 static int default_cmode __devinitdata = CMODE_8;
351 #endif
352
353 static int default_crt_on __devinitdata = 0;
354 static int default_lcd_on __devinitdata = 1;
355
356 #ifdef CONFIG_MTRR
357 static int mtrr = 1;
358 #endif
359
360 #ifdef CONFIG_PMAC_BACKLIGHT
361 static int backlight __devinitdata = 1;
362 #else
363 static int backlight __devinitdata = 0;
364 #endif
365
366 /* PLL constants */
367 struct aty128_constants {
368 u32 ref_clk;
369 u32 ppll_min;
370 u32 ppll_max;
371 u32 ref_divider;
372 u32 xclk;
373 u32 fifo_width;
374 u32 fifo_depth;
375 };
376
377 struct aty128_crtc {
378 u32 gen_cntl;
379 u32 h_total, h_sync_strt_wid;
380 u32 v_total, v_sync_strt_wid;
381 u32 pitch;
382 u32 offset, offset_cntl;
383 u32 xoffset, yoffset;
384 u32 vxres, vyres;
385 u32 depth, bpp;
386 };
387
388 struct aty128_pll {
389 u32 post_divider;
390 u32 feedback_divider;
391 u32 vclk;
392 };
393
394 struct aty128_ddafifo {
395 u32 dda_config;
396 u32 dda_on_off;
397 };
398
399 /* register values for a specific mode */
400 struct aty128fb_par {
401 struct aty128_crtc crtc;
402 struct aty128_pll pll;
403 struct aty128_ddafifo fifo_reg;
404 u32 accel_flags;
405 struct aty128_constants constants; /* PLL and others */
406 void __iomem *regbase; /* remapped mmio */
407 u32 vram_size; /* onboard video ram */
408 int chip_gen;
409 const struct aty128_meminfo *mem; /* onboard mem info */
410 #ifdef CONFIG_MTRR
411 struct { int vram; int vram_valid; } mtrr;
412 #endif
413 int blitter_may_be_busy;
414 int fifo_slots; /* free slots in FIFO (64 max) */
415
416 int pm_reg;
417 int crt_on, lcd_on;
418 struct pci_dev *pdev;
419 struct fb_info *next;
420 int asleep;
421 int lock_blank;
422
423 u8 red[32]; /* see aty128fb_setcolreg */
424 u8 green[64];
425 u8 blue[32];
426 u32 pseudo_palette[16]; /* used for TRUECOLOR */
427 };
428
429
430 #define round_div(n, d) ((n+(d/2))/d)
431
432 static int aty128fb_check_var(struct fb_var_screeninfo *var,
433 struct fb_info *info);
434 static int aty128fb_set_par(struct fb_info *info);
435 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
436 u_int transp, struct fb_info *info);
437 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
438 struct fb_info *fb);
439 static int aty128fb_blank(int blank, struct fb_info *fb);
440 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
441 static int aty128fb_sync(struct fb_info *info);
442
443 /*
444 * Internal routines
445 */
446
447 static int aty128_encode_var(struct fb_var_screeninfo *var,
448 const struct aty128fb_par *par);
449 static int aty128_decode_var(struct fb_var_screeninfo *var,
450 struct aty128fb_par *par);
451 #if 0
452 static void __devinit aty128_get_pllinfo(struct aty128fb_par *par,
453 void __iomem *bios);
454 static void __devinit __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
455 #endif
456 static void aty128_timings(struct aty128fb_par *par);
457 static void aty128_init_engine(struct aty128fb_par *par);
458 static void aty128_reset_engine(const struct aty128fb_par *par);
459 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
460 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
461 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
462 static void wait_for_idle(struct aty128fb_par *par);
463 static u32 depth_to_dst(u32 depth);
464
465 #ifdef CONFIG_FB_ATY128_BACKLIGHT
466 static void aty128_bl_set_power(struct fb_info *info, int power);
467 #endif
468
469 #define BIOS_IN8(v) (readb(bios + (v)))
470 #define BIOS_IN16(v) (readb(bios + (v)) | \
471 (readb(bios + (v) + 1) << 8))
472 #define BIOS_IN32(v) (readb(bios + (v)) | \
473 (readb(bios + (v) + 1) << 8) | \
474 (readb(bios + (v) + 2) << 16) | \
475 (readb(bios + (v) + 3) << 24))
476
477
478 static struct fb_ops aty128fb_ops = {
479 .owner = THIS_MODULE,
480 .fb_check_var = aty128fb_check_var,
481 .fb_set_par = aty128fb_set_par,
482 .fb_setcolreg = aty128fb_setcolreg,
483 .fb_pan_display = aty128fb_pan_display,
484 .fb_blank = aty128fb_blank,
485 .fb_ioctl = aty128fb_ioctl,
486 .fb_sync = aty128fb_sync,
487 .fb_fillrect = cfb_fillrect,
488 .fb_copyarea = cfb_copyarea,
489 .fb_imageblit = cfb_imageblit,
490 };
491
492 /*
493 * Functions to read from/write to the mmio registers
494 * - endian conversions may possibly be avoided by
495 * using the other register aperture. TODO.
496 */
497 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
498 const struct aty128fb_par *par)
499 {
500 return readl (par->regbase + regindex);
501 }
502
503 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
504 const struct aty128fb_par *par)
505 {
506 writel (val, par->regbase + regindex);
507 }
508
509 static inline u8 _aty_ld_8(unsigned int regindex,
510 const struct aty128fb_par *par)
511 {
512 return readb (par->regbase + regindex);
513 }
514
515 static inline void _aty_st_8(unsigned int regindex, u8 val,
516 const struct aty128fb_par *par)
517 {
518 writeb (val, par->regbase + regindex);
519 }
520
521 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
522 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
523 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
524 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
525
526 /*
527 * Functions to read from/write to the pll registers
528 */
529
530 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
531 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
532
533
534 static u32 _aty_ld_pll(unsigned int pll_index,
535 const struct aty128fb_par *par)
536 {
537 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
538 return aty_ld_le32(CLOCK_CNTL_DATA);
539 }
540
541
542 static void _aty_st_pll(unsigned int pll_index, u32 val,
543 const struct aty128fb_par *par)
544 {
545 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
546 aty_st_le32(CLOCK_CNTL_DATA, val);
547 }
548
549
550 /* return true when the PLL has completed an atomic update */
551 static int aty_pll_readupdate(const struct aty128fb_par *par)
552 {
553 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
554 }
555
556
557 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
558 {
559 unsigned long timeout = jiffies + HZ/100; // should be more than enough
560 int reset = 1;
561
562 while (time_before(jiffies, timeout))
563 if (aty_pll_readupdate(par)) {
564 reset = 0;
565 break;
566 }
567
568 if (reset) /* reset engine?? */
569 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
570 }
571
572
573 /* tell PLL to update */
574 static void aty_pll_writeupdate(const struct aty128fb_par *par)
575 {
576 aty_pll_wait_readupdate(par);
577
578 aty_st_pll(PPLL_REF_DIV,
579 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
580 }
581
582
583 /* write to the scratch register to test r/w functionality */
584 static int __devinit register_test(const struct aty128fb_par *par)
585 {
586 u32 val;
587 int flag = 0;
588
589 val = aty_ld_le32(BIOS_0_SCRATCH);
590
591 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
592 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
593 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
594
595 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
596 flag = 1;
597 }
598
599 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
600 return flag;
601 }
602
603
604 /*
605 * Accelerator engine functions
606 */
607 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
608 {
609 int i;
610
611 for (;;) {
612 for (i = 0; i < 2000000; i++) {
613 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
614 if (par->fifo_slots >= entries)
615 return;
616 }
617 aty128_reset_engine(par);
618 }
619 }
620
621
622 static void wait_for_idle(struct aty128fb_par *par)
623 {
624 int i;
625
626 do_wait_for_fifo(64, par);
627
628 for (;;) {
629 for (i = 0; i < 2000000; i++) {
630 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
631 aty128_flush_pixel_cache(par);
632 par->blitter_may_be_busy = 0;
633 return;
634 }
635 }
636 aty128_reset_engine(par);
637 }
638 }
639
640
641 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
642 {
643 if (par->fifo_slots < entries)
644 do_wait_for_fifo(64, par);
645 par->fifo_slots -= entries;
646 }
647
648
649 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
650 {
651 int i;
652 u32 tmp;
653
654 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
655 tmp &= ~(0x00ff);
656 tmp |= 0x00ff;
657 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
658
659 for (i = 0; i < 2000000; i++)
660 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
661 break;
662 }
663
664
665 static void aty128_reset_engine(const struct aty128fb_par *par)
666 {
667 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
668
669 aty128_flush_pixel_cache(par);
670
671 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
672 mclk_cntl = aty_ld_pll(MCLK_CNTL);
673
674 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
675
676 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
677 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
678 aty_ld_le32(GEN_RESET_CNTL);
679 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
680 aty_ld_le32(GEN_RESET_CNTL);
681
682 aty_st_pll(MCLK_CNTL, mclk_cntl);
683 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
684 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
685
686 /* use old pio mode */
687 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
688
689 DBG("engine reset");
690 }
691
692
693 static void aty128_init_engine(struct aty128fb_par *par)
694 {
695 u32 pitch_value;
696
697 wait_for_idle(par);
698
699 /* 3D scaler not spoken here */
700 wait_for_fifo(1, par);
701 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
702
703 aty128_reset_engine(par);
704
705 pitch_value = par->crtc.pitch;
706 if (par->crtc.bpp == 24) {
707 pitch_value = pitch_value * 3;
708 }
709
710 wait_for_fifo(4, par);
711 /* setup engine offset registers */
712 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
713
714 /* setup engine pitch registers */
715 aty_st_le32(DEFAULT_PITCH, pitch_value);
716
717 /* set the default scissor register to max dimensions */
718 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
719
720 /* set the drawing controls registers */
721 aty_st_le32(DP_GUI_MASTER_CNTL,
722 GMC_SRC_PITCH_OFFSET_DEFAULT |
723 GMC_DST_PITCH_OFFSET_DEFAULT |
724 GMC_SRC_CLIP_DEFAULT |
725 GMC_DST_CLIP_DEFAULT |
726 GMC_BRUSH_SOLIDCOLOR |
727 (depth_to_dst(par->crtc.depth) << 8) |
728 GMC_SRC_DSTCOLOR |
729 GMC_BYTE_ORDER_MSB_TO_LSB |
730 GMC_DP_CONVERSION_TEMP_6500 |
731 ROP3_PATCOPY |
732 GMC_DP_SRC_RECT |
733 GMC_3D_FCN_EN_CLR |
734 GMC_DST_CLR_CMP_FCN_CLEAR |
735 GMC_AUX_CLIP_CLEAR |
736 GMC_WRITE_MASK_SET);
737
738 wait_for_fifo(8, par);
739 /* clear the line drawing registers */
740 aty_st_le32(DST_BRES_ERR, 0);
741 aty_st_le32(DST_BRES_INC, 0);
742 aty_st_le32(DST_BRES_DEC, 0);
743
744 /* set brush color registers */
745 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
746 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
747
748 /* set source color registers */
749 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
750 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
751
752 /* default write mask */
753 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
754
755 /* Wait for all the writes to be completed before returning */
756 wait_for_idle(par);
757 }
758
759
760 /* convert depth values to their register representation */
761 static u32 depth_to_dst(u32 depth)
762 {
763 if (depth <= 8)
764 return DST_8BPP;
765 else if (depth <= 15)
766 return DST_15BPP;
767 else if (depth == 16)
768 return DST_16BPP;
769 else if (depth <= 24)
770 return DST_24BPP;
771 else if (depth <= 32)
772 return DST_32BPP;
773
774 return -EINVAL;
775 }
776
777 /*
778 * PLL informations retreival
779 */
780
781
782 #ifndef __sparc__
783 static void __iomem * __devinit aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
784 {
785 u16 dptr;
786 u8 rom_type;
787 void __iomem *bios;
788 size_t rom_size;
789
790 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
791 unsigned int temp;
792 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
793 temp &= 0x00ffffffu;
794 temp |= 0x04 << 24;
795 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
796 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
797
798 bios = pci_map_rom(dev, &rom_size);
799
800 if (!bios) {
801 printk(KERN_ERR "aty128fb: ROM failed to map\n");
802 return NULL;
803 }
804
805 /* Very simple test to make sure it appeared */
806 if (BIOS_IN16(0) != 0xaa55) {
807 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
808 " be 0xaa55\n", BIOS_IN16(0));
809 goto failed;
810 }
811
812 /* Look for the PCI data to check the ROM type */
813 dptr = BIOS_IN16(0x18);
814
815 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
816 * for now, until I've verified this works everywhere. The goal here is more
817 * to phase out Open Firmware images.
818 *
819 * Currently, we only look at the first PCI data, we could iteratre and deal with
820 * them all, and we should use fb_bios_start relative to start of image and not
821 * relative start of ROM, but so far, I never found a dual-image ATI card
822 *
823 * typedef struct {
824 * u32 signature; + 0x00
825 * u16 vendor; + 0x04
826 * u16 device; + 0x06
827 * u16 reserved_1; + 0x08
828 * u16 dlen; + 0x0a
829 * u8 drevision; + 0x0c
830 * u8 class_hi; + 0x0d
831 * u16 class_lo; + 0x0e
832 * u16 ilen; + 0x10
833 * u16 irevision; + 0x12
834 * u8 type; + 0x14
835 * u8 indicator; + 0x15
836 * u16 reserved_2; + 0x16
837 * } pci_data_t;
838 */
839 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
840 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
841 BIOS_IN32(dptr));
842 goto anyway;
843 }
844 rom_type = BIOS_IN8(dptr + 0x14);
845 switch(rom_type) {
846 case 0:
847 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
848 break;
849 case 1:
850 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
851 goto failed;
852 case 2:
853 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
854 goto failed;
855 default:
856 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
857 goto failed;
858 }
859 anyway:
860 return bios;
861
862 failed:
863 pci_unmap_rom(dev, bios);
864 return NULL;
865 }
866
867 static void __devinit aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
868 {
869 unsigned int bios_hdr;
870 unsigned int bios_pll;
871
872 bios_hdr = BIOS_IN16(0x48);
873 bios_pll = BIOS_IN16(bios_hdr + 0x30);
874
875 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
876 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
877 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
878 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
879 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
880
881 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
882 par->constants.ppll_max, par->constants.ppll_min,
883 par->constants.xclk, par->constants.ref_divider,
884 par->constants.ref_clk);
885
886 }
887
888 #ifdef CONFIG_X86
889 static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
890 {
891 /* I simplified this code as we used to miss the signatures in
892 * a lot of case. It's now closer to XFree, we just don't check
893 * for signatures at all... Something better will have to be done
894 * if we end up having conflicts
895 */
896 u32 segstart;
897 unsigned char __iomem *rom_base = NULL;
898
899 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
900 rom_base = ioremap(segstart, 0x10000);
901 if (rom_base == NULL)
902 return NULL;
903 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
904 break;
905 iounmap(rom_base);
906 rom_base = NULL;
907 }
908 return rom_base;
909 }
910 #endif
911 #endif /* ndef(__sparc__) */
912
913 /* fill in known card constants if pll_block is not available */
914 static void __devinit aty128_timings(struct aty128fb_par *par)
915 {
916 #ifdef CONFIG_PPC_OF
917 /* instead of a table lookup, assume OF has properly
918 * setup the PLL registers and use their values
919 * to set the XCLK values and reference divider values */
920
921 u32 x_mpll_ref_fb_div;
922 u32 xclk_cntl;
923 u32 Nx, M;
924 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
925 #endif
926
927 if (!par->constants.ref_clk)
928 par->constants.ref_clk = 2950;
929
930 #ifdef CONFIG_PPC_OF
931 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
932 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
933 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
934 M = x_mpll_ref_fb_div & 0x0000ff;
935
936 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
937 (M * PostDivSet[xclk_cntl]));
938
939 par->constants.ref_divider =
940 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
941 #endif
942
943 if (!par->constants.ref_divider) {
944 par->constants.ref_divider = 0x3b;
945
946 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
947 aty_pll_writeupdate(par);
948 }
949 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
950 aty_pll_writeupdate(par);
951
952 /* from documentation */
953 if (!par->constants.ppll_min)
954 par->constants.ppll_min = 12500;
955 if (!par->constants.ppll_max)
956 par->constants.ppll_max = 25000; /* 23000 on some cards? */
957 if (!par->constants.xclk)
958 par->constants.xclk = 0x1d4d; /* same as mclk */
959
960 par->constants.fifo_width = 128;
961 par->constants.fifo_depth = 32;
962
963 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
964 case 0:
965 par->mem = &sdr_128;
966 break;
967 case 1:
968 par->mem = &sdr_sgram;
969 break;
970 case 2:
971 par->mem = &ddr_sgram;
972 break;
973 default:
974 par->mem = &sdr_sgram;
975 }
976 }
977
978
979
980 /*
981 * CRTC programming
982 */
983
984 /* Program the CRTC registers */
985 static void aty128_set_crtc(const struct aty128_crtc *crtc,
986 const struct aty128fb_par *par)
987 {
988 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
989 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
990 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
991 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
992 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
993 aty_st_le32(CRTC_PITCH, crtc->pitch);
994 aty_st_le32(CRTC_OFFSET, crtc->offset);
995 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
996 /* Disable ATOMIC updating. Is this the right place? */
997 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
998 }
999
1000
1001 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1002 struct aty128_crtc *crtc,
1003 const struct aty128fb_par *par)
1004 {
1005 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1006 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1007 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1008 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1009 u32 depth, bytpp;
1010 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1011
1012 /* input */
1013 xres = var->xres;
1014 yres = var->yres;
1015 vxres = var->xres_virtual;
1016 vyres = var->yres_virtual;
1017 xoffset = var->xoffset;
1018 yoffset = var->yoffset;
1019 bpp = var->bits_per_pixel;
1020 left = var->left_margin;
1021 right = var->right_margin;
1022 upper = var->upper_margin;
1023 lower = var->lower_margin;
1024 hslen = var->hsync_len;
1025 vslen = var->vsync_len;
1026 sync = var->sync;
1027 vmode = var->vmode;
1028
1029 if (bpp != 16)
1030 depth = bpp;
1031 else
1032 depth = (var->green.length == 6) ? 16 : 15;
1033
1034 /* check for mode eligibility
1035 * accept only non interlaced modes */
1036 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1037 return -EINVAL;
1038
1039 /* convert (and round up) and validate */
1040 xres = (xres + 7) & ~7;
1041 xoffset = (xoffset + 7) & ~7;
1042
1043 if (vxres < xres + xoffset)
1044 vxres = xres + xoffset;
1045
1046 if (vyres < yres + yoffset)
1047 vyres = yres + yoffset;
1048
1049 /* convert depth into ATI register depth */
1050 dst = depth_to_dst(depth);
1051
1052 if (dst == -EINVAL) {
1053 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1054 return -EINVAL;
1055 }
1056
1057 /* convert register depth to bytes per pixel */
1058 bytpp = mode_bytpp[dst];
1059
1060 /* make sure there is enough video ram for the mode */
1061 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1062 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1063 return -EINVAL;
1064 }
1065
1066 h_disp = (xres >> 3) - 1;
1067 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1068
1069 v_disp = yres - 1;
1070 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1071
1072 /* check to make sure h_total and v_total are in range */
1073 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1074 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1075 return -EINVAL;
1076 }
1077
1078 h_sync_wid = (hslen + 7) >> 3;
1079 if (h_sync_wid == 0)
1080 h_sync_wid = 1;
1081 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1082 h_sync_wid = 0x3f;
1083
1084 h_sync_strt = (h_disp << 3) + right;
1085
1086 v_sync_wid = vslen;
1087 if (v_sync_wid == 0)
1088 v_sync_wid = 1;
1089 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1090 v_sync_wid = 0x1f;
1091
1092 v_sync_strt = v_disp + lower;
1093
1094 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1095 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1096
1097 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1098
1099 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1100
1101 crtc->h_total = h_total | (h_disp << 16);
1102 crtc->v_total = v_total | (v_disp << 16);
1103
1104 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1105 (h_sync_pol << 23);
1106 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1107 (v_sync_pol << 23);
1108
1109 crtc->pitch = vxres >> 3;
1110
1111 crtc->offset = 0;
1112
1113 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1114 crtc->offset_cntl = 0x00010000;
1115 else
1116 crtc->offset_cntl = 0;
1117
1118 crtc->vxres = vxres;
1119 crtc->vyres = vyres;
1120 crtc->xoffset = xoffset;
1121 crtc->yoffset = yoffset;
1122 crtc->depth = depth;
1123 crtc->bpp = bpp;
1124
1125 return 0;
1126 }
1127
1128
1129 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1130 {
1131
1132 /* fill in pixel info */
1133 var->red.msb_right = 0;
1134 var->green.msb_right = 0;
1135 var->blue.offset = 0;
1136 var->blue.msb_right = 0;
1137 var->transp.offset = 0;
1138 var->transp.length = 0;
1139 var->transp.msb_right = 0;
1140 switch (pix_width) {
1141 case CRTC_PIX_WIDTH_8BPP:
1142 var->bits_per_pixel = 8;
1143 var->red.offset = 0;
1144 var->red.length = 8;
1145 var->green.offset = 0;
1146 var->green.length = 8;
1147 var->blue.length = 8;
1148 break;
1149 case CRTC_PIX_WIDTH_15BPP:
1150 var->bits_per_pixel = 16;
1151 var->red.offset = 10;
1152 var->red.length = 5;
1153 var->green.offset = 5;
1154 var->green.length = 5;
1155 var->blue.length = 5;
1156 break;
1157 case CRTC_PIX_WIDTH_16BPP:
1158 var->bits_per_pixel = 16;
1159 var->red.offset = 11;
1160 var->red.length = 5;
1161 var->green.offset = 5;
1162 var->green.length = 6;
1163 var->blue.length = 5;
1164 break;
1165 case CRTC_PIX_WIDTH_24BPP:
1166 var->bits_per_pixel = 24;
1167 var->red.offset = 16;
1168 var->red.length = 8;
1169 var->green.offset = 8;
1170 var->green.length = 8;
1171 var->blue.length = 8;
1172 break;
1173 case CRTC_PIX_WIDTH_32BPP:
1174 var->bits_per_pixel = 32;
1175 var->red.offset = 16;
1176 var->red.length = 8;
1177 var->green.offset = 8;
1178 var->green.length = 8;
1179 var->blue.length = 8;
1180 var->transp.offset = 24;
1181 var->transp.length = 8;
1182 break;
1183 default:
1184 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1185 return -EINVAL;
1186 }
1187
1188 return 0;
1189 }
1190
1191
1192 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1193 struct fb_var_screeninfo *var)
1194 {
1195 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1196 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1197 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1198 u32 pix_width;
1199
1200 /* fun with masking */
1201 h_total = crtc->h_total & 0x1ff;
1202 h_disp = (crtc->h_total >> 16) & 0xff;
1203 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1204 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1205 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1206 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1207 v_total = crtc->v_total & 0x7ff;
1208 v_disp = (crtc->v_total >> 16) & 0x7ff;
1209 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1210 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1211 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1212 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1213 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1214
1215 /* do conversions */
1216 xres = (h_disp + 1) << 3;
1217 yres = v_disp + 1;
1218 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1219 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1220 hslen = h_sync_wid << 3;
1221 upper = v_total - v_sync_strt - v_sync_wid;
1222 lower = v_sync_strt - v_disp;
1223 vslen = v_sync_wid;
1224 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1225 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1226 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1227
1228 aty128_pix_width_to_var(pix_width, var);
1229
1230 var->xres = xres;
1231 var->yres = yres;
1232 var->xres_virtual = crtc->vxres;
1233 var->yres_virtual = crtc->vyres;
1234 var->xoffset = crtc->xoffset;
1235 var->yoffset = crtc->yoffset;
1236 var->left_margin = left;
1237 var->right_margin = right;
1238 var->upper_margin = upper;
1239 var->lower_margin = lower;
1240 var->hsync_len = hslen;
1241 var->vsync_len = vslen;
1242 var->sync = sync;
1243 var->vmode = FB_VMODE_NONINTERLACED;
1244
1245 return 0;
1246 }
1247
1248 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1249 {
1250 if (on) {
1251 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1252 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1253 } else
1254 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1255 }
1256
1257 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1258 {
1259 u32 reg;
1260 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1261 struct fb_info *info = pci_get_drvdata(par->pdev);
1262 #endif
1263
1264 if (on) {
1265 reg = aty_ld_le32(LVDS_GEN_CNTL);
1266 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1267 reg &= ~LVDS_DISPLAY_DIS;
1268 aty_st_le32(LVDS_GEN_CNTL, reg);
1269 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1270 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1271 #endif
1272 } else {
1273 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1274 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1275 #endif
1276 reg = aty_ld_le32(LVDS_GEN_CNTL);
1277 reg |= LVDS_DISPLAY_DIS;
1278 aty_st_le32(LVDS_GEN_CNTL, reg);
1279 mdelay(100);
1280 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1281 aty_st_le32(LVDS_GEN_CNTL, reg);
1282 }
1283 }
1284
1285 static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1286 {
1287 u32 div3;
1288
1289 unsigned char post_conv[] = /* register values for post dividers */
1290 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1291
1292 /* select PPLL_DIV_3 */
1293 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1294
1295 /* reset PLL */
1296 aty_st_pll(PPLL_CNTL,
1297 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1298
1299 /* write the reference divider */
1300 aty_pll_wait_readupdate(par);
1301 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1302 aty_pll_writeupdate(par);
1303
1304 div3 = aty_ld_pll(PPLL_DIV_3);
1305 div3 &= ~PPLL_FB3_DIV_MASK;
1306 div3 |= pll->feedback_divider;
1307 div3 &= ~PPLL_POST3_DIV_MASK;
1308 div3 |= post_conv[pll->post_divider] << 16;
1309
1310 /* write feedback and post dividers */
1311 aty_pll_wait_readupdate(par);
1312 aty_st_pll(PPLL_DIV_3, div3);
1313 aty_pll_writeupdate(par);
1314
1315 aty_pll_wait_readupdate(par);
1316 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1317 aty_pll_writeupdate(par);
1318
1319 /* clear the reset, just in case */
1320 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1321 }
1322
1323
1324 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1325 const struct aty128fb_par *par)
1326 {
1327 const struct aty128_constants c = par->constants;
1328 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1329 u32 output_freq;
1330 u32 vclk; /* in .01 MHz */
1331 int i = 0;
1332 u32 n, d;
1333
1334 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1335
1336 /* adjust pixel clock if necessary */
1337 if (vclk > c.ppll_max)
1338 vclk = c.ppll_max;
1339 if (vclk * 12 < c.ppll_min)
1340 vclk = c.ppll_min/12;
1341
1342 pll->post_divider = -1;
1343
1344 /* now, find an acceptable divider */
1345 for (i = 0; i < sizeof(post_dividers); i++) {
1346 output_freq = post_dividers[i] * vclk;
1347 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1348 pll->post_divider = post_dividers[i];
1349 break;
1350 }
1351 }
1352
1353 if (pll->post_divider < 0)
1354 return -EINVAL;
1355
1356 /* calculate feedback divider */
1357 n = c.ref_divider * output_freq;
1358 d = c.ref_clk;
1359
1360 pll->feedback_divider = round_div(n, d);
1361 pll->vclk = vclk;
1362
1363 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1364 "vclk_per: %d\n", pll->post_divider,
1365 pll->feedback_divider, vclk, output_freq,
1366 c.ref_divider, period_in_ps);
1367
1368 return 0;
1369 }
1370
1371
1372 static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1373 {
1374 var->pixclock = 100000000 / pll->vclk;
1375
1376 return 0;
1377 }
1378
1379
1380 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1381 const struct aty128fb_par *par)
1382 {
1383 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1384 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1385 }
1386
1387
1388 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1389 const struct aty128_pll *pll,
1390 u32 depth,
1391 const struct aty128fb_par *par)
1392 {
1393 const struct aty128_meminfo *m = par->mem;
1394 u32 xclk = par->constants.xclk;
1395 u32 fifo_width = par->constants.fifo_width;
1396 u32 fifo_depth = par->constants.fifo_depth;
1397 s32 x, b, p, ron, roff;
1398 u32 n, d, bpp;
1399
1400 /* round up to multiple of 8 */
1401 bpp = (depth+7) & ~7;
1402
1403 n = xclk * fifo_width;
1404 d = pll->vclk * bpp;
1405 x = round_div(n, d);
1406
1407 ron = 4 * m->MB +
1408 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1409 2 * m->Trp +
1410 m->Twr +
1411 m->CL +
1412 m->Tr2w +
1413 x;
1414
1415 DBG("x %x\n", x);
1416
1417 b = 0;
1418 while (x) {
1419 x >>= 1;
1420 b++;
1421 }
1422 p = b + 1;
1423
1424 ron <<= (11 - p);
1425
1426 n <<= (11 - p);
1427 x = round_div(n, d);
1428 roff = x * (fifo_depth - 4);
1429
1430 if ((ron + m->Rloop) >= roff) {
1431 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1432 return -EINVAL;
1433 }
1434
1435 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1436 p, m->Rloop, x, ron, roff);
1437
1438 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1439 dsp->dda_on_off = ron << 16 | roff;
1440
1441 return 0;
1442 }
1443
1444
1445 /*
1446 * This actually sets the video mode.
1447 */
1448 static int aty128fb_set_par(struct fb_info *info)
1449 {
1450 struct aty128fb_par *par = info->par;
1451 u32 config;
1452 int err;
1453
1454 if ((err = aty128_decode_var(&info->var, par)) != 0)
1455 return err;
1456
1457 if (par->blitter_may_be_busy)
1458 wait_for_idle(par);
1459
1460 /* clear all registers that may interfere with mode setting */
1461 aty_st_le32(OVR_CLR, 0);
1462 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1463 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1464 aty_st_le32(OV0_SCALE_CNTL, 0);
1465 aty_st_le32(MPP_TB_CONFIG, 0);
1466 aty_st_le32(MPP_GP_CONFIG, 0);
1467 aty_st_le32(SUBPIC_CNTL, 0);
1468 aty_st_le32(VIPH_CONTROL, 0);
1469 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1470 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1471 aty_st_le32(CAP0_TRIG_CNTL, 0);
1472 aty_st_le32(CAP1_TRIG_CNTL, 0);
1473
1474 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1475
1476 aty128_set_crtc(&par->crtc, par);
1477 aty128_set_pll(&par->pll, par);
1478 aty128_set_fifo(&par->fifo_reg, par);
1479
1480 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1481
1482 #if defined(__BIG_ENDIAN)
1483 if (par->crtc.bpp == 32)
1484 config |= 2; /* make aperture do 32 bit swapping */
1485 else if (par->crtc.bpp == 16)
1486 config |= 1; /* make aperture do 16 bit swapping */
1487 #endif
1488
1489 aty_st_le32(CONFIG_CNTL, config);
1490 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1491
1492 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1493 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1494 : FB_VISUAL_DIRECTCOLOR;
1495
1496 if (par->chip_gen == rage_M3) {
1497 aty128_set_crt_enable(par, par->crt_on);
1498 aty128_set_lcd_enable(par, par->lcd_on);
1499 }
1500 if (par->accel_flags & FB_ACCELF_TEXT)
1501 aty128_init_engine(par);
1502
1503 #ifdef CONFIG_BOOTX_TEXT
1504 btext_update_display(info->fix.smem_start,
1505 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1506 ((par->crtc.v_total>>16) & 0x7ff)+1,
1507 par->crtc.bpp,
1508 par->crtc.vxres*par->crtc.bpp/8);
1509 #endif /* CONFIG_BOOTX_TEXT */
1510
1511 return 0;
1512 }
1513
1514 /*
1515 * encode/decode the User Defined Part of the Display
1516 */
1517
1518 static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1519 {
1520 int err;
1521 struct aty128_crtc crtc;
1522 struct aty128_pll pll;
1523 struct aty128_ddafifo fifo_reg;
1524
1525 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1526 return err;
1527
1528 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1529 return err;
1530
1531 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1532 return err;
1533
1534 par->crtc = crtc;
1535 par->pll = pll;
1536 par->fifo_reg = fifo_reg;
1537 par->accel_flags = var->accel_flags;
1538
1539 return 0;
1540 }
1541
1542
1543 static int aty128_encode_var(struct fb_var_screeninfo *var,
1544 const struct aty128fb_par *par)
1545 {
1546 int err;
1547
1548 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1549 return err;
1550
1551 if ((err = aty128_pll_to_var(&par->pll, var)))
1552 return err;
1553
1554 var->nonstd = 0;
1555 var->activate = 0;
1556
1557 var->height = -1;
1558 var->width = -1;
1559 var->accel_flags = par->accel_flags;
1560
1561 return 0;
1562 }
1563
1564
1565 static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1566 {
1567 struct aty128fb_par par;
1568 int err;
1569
1570 par = *(struct aty128fb_par *)info->par;
1571 if ((err = aty128_decode_var(var, &par)) != 0)
1572 return err;
1573 aty128_encode_var(var, &par);
1574 return 0;
1575 }
1576
1577
1578 /*
1579 * Pan or Wrap the Display
1580 */
1581 static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb)
1582 {
1583 struct aty128fb_par *par = fb->par;
1584 u32 xoffset, yoffset;
1585 u32 offset;
1586 u32 xres, yres;
1587
1588 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1589 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1590
1591 xoffset = (var->xoffset +7) & ~7;
1592 yoffset = var->yoffset;
1593
1594 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1595 return -EINVAL;
1596
1597 par->crtc.xoffset = xoffset;
1598 par->crtc.yoffset = yoffset;
1599
1600 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1601
1602 if (par->crtc.bpp == 24)
1603 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1604
1605 aty_st_le32(CRTC_OFFSET, offset);
1606
1607 return 0;
1608 }
1609
1610
1611 /*
1612 * Helper function to store a single palette register
1613 */
1614 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1615 struct aty128fb_par *par)
1616 {
1617 if (par->chip_gen == rage_M3) {
1618 #if 0
1619 /* Note: For now, on M3, we set palette on both heads, which may
1620 * be useless. Can someone with a M3 check this ?
1621 *
1622 * This code would still be useful if using the second CRTC to
1623 * do mirroring
1624 */
1625
1626 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1627 aty_st_8(PALETTE_INDEX, regno);
1628 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1629 #endif
1630 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1631 }
1632
1633 aty_st_8(PALETTE_INDEX, regno);
1634 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1635 }
1636
1637 static int aty128fb_sync(struct fb_info *info)
1638 {
1639 struct aty128fb_par *par = info->par;
1640
1641 if (par->blitter_may_be_busy)
1642 wait_for_idle(par);
1643 return 0;
1644 }
1645
1646 #ifndef MODULE
1647 static int __devinit aty128fb_setup(char *options)
1648 {
1649 char *this_opt;
1650
1651 if (!options || !*options)
1652 return 0;
1653
1654 while ((this_opt = strsep(&options, ",")) != NULL) {
1655 if (!strncmp(this_opt, "lcd:", 4)) {
1656 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1657 continue;
1658 } else if (!strncmp(this_opt, "crt:", 4)) {
1659 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1660 continue;
1661 } else if (!strncmp(this_opt, "backlight:", 10)) {
1662 backlight = simple_strtoul(this_opt+10, NULL, 0);
1663 continue;
1664 }
1665 #ifdef CONFIG_MTRR
1666 if(!strncmp(this_opt, "nomtrr", 6)) {
1667 mtrr = 0;
1668 continue;
1669 }
1670 #endif
1671 #ifdef CONFIG_PPC_PMAC
1672 /* vmode and cmode deprecated */
1673 if (!strncmp(this_opt, "vmode:", 6)) {
1674 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1675 if (vmode > 0 && vmode <= VMODE_MAX)
1676 default_vmode = vmode;
1677 continue;
1678 } else if (!strncmp(this_opt, "cmode:", 6)) {
1679 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1680 switch (cmode) {
1681 case 0:
1682 case 8:
1683 default_cmode = CMODE_8;
1684 break;
1685 case 15:
1686 case 16:
1687 default_cmode = CMODE_16;
1688 break;
1689 case 24:
1690 case 32:
1691 default_cmode = CMODE_32;
1692 break;
1693 }
1694 continue;
1695 }
1696 #endif /* CONFIG_PPC_PMAC */
1697 mode_option = this_opt;
1698 }
1699 return 0;
1700 }
1701 #endif /* MODULE */
1702
1703 /* Backlight */
1704 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1705 #define MAX_LEVEL 0xFF
1706
1707 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1708 int level)
1709 {
1710 struct fb_info *info = pci_get_drvdata(par->pdev);
1711 int atylevel;
1712
1713 /* Get and convert the value */
1714 /* No locking of bl_curve since we read a single value */
1715 atylevel = MAX_LEVEL -
1716 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1717
1718 if (atylevel < 0)
1719 atylevel = 0;
1720 else if (atylevel > MAX_LEVEL)
1721 atylevel = MAX_LEVEL;
1722
1723 return atylevel;
1724 }
1725
1726 /* We turn off the LCD completely instead of just dimming the backlight.
1727 * This provides greater power saving and the display is useless without
1728 * backlight anyway
1729 */
1730 #define BACKLIGHT_LVDS_OFF
1731 /* That one prevents proper CRT output with LCD off */
1732 #undef BACKLIGHT_DAC_OFF
1733
1734 static int aty128_bl_update_status(struct backlight_device *bd)
1735 {
1736 struct aty128fb_par *par = class_get_devdata(&bd->class_dev);
1737 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1738 int level;
1739
1740 if (bd->props.power != FB_BLANK_UNBLANK ||
1741 bd->props.fb_blank != FB_BLANK_UNBLANK ||
1742 !par->lcd_on)
1743 level = 0;
1744 else
1745 level = bd->props.brightness;
1746
1747 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1748 if (level > 0) {
1749 reg |= LVDS_DIGION;
1750 if (!(reg & LVDS_ON)) {
1751 reg &= ~LVDS_BLON;
1752 aty_st_le32(LVDS_GEN_CNTL, reg);
1753 aty_ld_le32(LVDS_GEN_CNTL);
1754 mdelay(10);
1755 reg |= LVDS_BLON;
1756 aty_st_le32(LVDS_GEN_CNTL, reg);
1757 }
1758 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1759 reg |= (aty128_bl_get_level_brightness(par, level) << LVDS_BL_MOD_LEVEL_SHIFT);
1760 #ifdef BACKLIGHT_LVDS_OFF
1761 reg |= LVDS_ON | LVDS_EN;
1762 reg &= ~LVDS_DISPLAY_DIS;
1763 #endif
1764 aty_st_le32(LVDS_GEN_CNTL, reg);
1765 #ifdef BACKLIGHT_DAC_OFF
1766 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1767 #endif
1768 } else {
1769 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1770 reg |= (aty128_bl_get_level_brightness(par, 0) << LVDS_BL_MOD_LEVEL_SHIFT);
1771 #ifdef BACKLIGHT_LVDS_OFF
1772 reg |= LVDS_DISPLAY_DIS;
1773 aty_st_le32(LVDS_GEN_CNTL, reg);
1774 aty_ld_le32(LVDS_GEN_CNTL);
1775 udelay(10);
1776 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1777 #endif
1778 aty_st_le32(LVDS_GEN_CNTL, reg);
1779 #ifdef BACKLIGHT_DAC_OFF
1780 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1781 #endif
1782 }
1783
1784 return 0;
1785 }
1786
1787 static int aty128_bl_get_brightness(struct backlight_device *bd)
1788 {
1789 return bd->props.brightness;
1790 }
1791
1792 static struct backlight_ops aty128_bl_data = {
1793 .get_brightness = aty128_bl_get_brightness,
1794 .update_status = aty128_bl_update_status,
1795 };
1796
1797 static void aty128_bl_set_power(struct fb_info *info, int power)
1798 {
1799 if (info->bl_dev) {
1800 info->bl_dev->props.power = power;
1801 backlight_update_status(info->bl_dev);
1802 }
1803 }
1804
1805 static void aty128_bl_init(struct aty128fb_par *par)
1806 {
1807 struct fb_info *info = pci_get_drvdata(par->pdev);
1808 struct backlight_device *bd;
1809 char name[12];
1810
1811 /* Could be extended to Rage128Pro LVDS output too */
1812 if (par->chip_gen != rage_M3)
1813 return;
1814
1815 #ifdef CONFIG_PMAC_BACKLIGHT
1816 if (!pmac_has_backlight_type("ati"))
1817 return;
1818 #endif
1819
1820 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1821
1822 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data);
1823 if (IS_ERR(bd)) {
1824 info->bl_dev = NULL;
1825 printk(KERN_WARNING "aty128: Backlight registration failed\n");
1826 goto error;
1827 }
1828
1829 info->bl_dev = bd;
1830 fb_bl_default_curve(info, 0,
1831 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1832 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1833
1834 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1835 bd->props.brightness = bd->props.max_brightness;
1836 bd->props.power = FB_BLANK_UNBLANK;
1837 backlight_update_status(bd);
1838
1839 printk("aty128: Backlight initialized (%s)\n", name);
1840
1841 return;
1842
1843 error:
1844 return;
1845 }
1846
1847 static void aty128_bl_exit(struct backlight_device *bd)
1848 {
1849 backlight_device_unregister(bd);
1850 printk("aty128: Backlight unloaded\n");
1851 }
1852 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1853
1854 /*
1855 * Initialisation
1856 */
1857
1858 #ifdef CONFIG_PPC_PMAC
1859 static void aty128_early_resume(void *data)
1860 {
1861 struct aty128fb_par *par = data;
1862
1863 if (try_acquire_console_sem())
1864 return;
1865 aty128_do_resume(par->pdev);
1866 release_console_sem();
1867 }
1868 #endif /* CONFIG_PPC_PMAC */
1869
1870 static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1871 {
1872 struct fb_info *info = pci_get_drvdata(pdev);
1873 struct aty128fb_par *par = info->par;
1874 struct fb_var_screeninfo var;
1875 char video_card[DEVICE_NAME_SIZE];
1876 u8 chip_rev;
1877 u32 dac;
1878
1879 /* Get the chip revision */
1880 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1881
1882 strcpy(video_card, "Rage128 XX ");
1883 video_card[8] = ent->device >> 8;
1884 video_card[9] = ent->device & 0xFF;
1885
1886 /* range check to make sure */
1887 if (ent->driver_data < ARRAY_SIZE(r128_family))
1888 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1889
1890 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1891
1892 if (par->vram_size % (1024 * 1024) == 0)
1893 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1894 else
1895 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1896
1897 par->chip_gen = ent->driver_data;
1898
1899 /* fill in info */
1900 info->fbops = &aty128fb_ops;
1901 info->flags = FBINFO_FLAG_DEFAULT;
1902
1903 par->lcd_on = default_lcd_on;
1904 par->crt_on = default_crt_on;
1905
1906 var = default_var;
1907 #ifdef CONFIG_PPC_PMAC
1908 if (machine_is(powermac)) {
1909 /* Indicate sleep capability */
1910 if (par->chip_gen == rage_M3) {
1911 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1912 pmac_set_early_video_resume(aty128_early_resume, par);
1913 }
1914
1915 /* Find default mode */
1916 if (mode_option) {
1917 if (!mac_find_mode(&var, info, mode_option, 8))
1918 var = default_var;
1919 } else {
1920 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1921 default_vmode = VMODE_1024_768_60;
1922
1923 /* iMacs need that resolution
1924 * PowerMac2,1 first r128 iMacs
1925 * PowerMac2,2 summer 2000 iMacs
1926 * PowerMac4,1 january 2001 iMacs "flower power"
1927 */
1928 if (machine_is_compatible("PowerMac2,1") ||
1929 machine_is_compatible("PowerMac2,2") ||
1930 machine_is_compatible("PowerMac4,1"))
1931 default_vmode = VMODE_1024_768_75;
1932
1933 /* iBook SE */
1934 if (machine_is_compatible("PowerBook2,2"))
1935 default_vmode = VMODE_800_600_60;
1936
1937 /* PowerBook Firewire (Pismo), iBook Dual USB */
1938 if (machine_is_compatible("PowerBook3,1") ||
1939 machine_is_compatible("PowerBook4,1"))
1940 default_vmode = VMODE_1024_768_60;
1941
1942 /* PowerBook Titanium */
1943 if (machine_is_compatible("PowerBook3,2"))
1944 default_vmode = VMODE_1152_768_60;
1945
1946 if (default_cmode > 16)
1947 default_cmode = CMODE_32;
1948 else if (default_cmode > 8)
1949 default_cmode = CMODE_16;
1950 else
1951 default_cmode = CMODE_8;
1952
1953 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1954 var = default_var;
1955 }
1956 } else
1957 #endif /* CONFIG_PPC_PMAC */
1958 {
1959 if (mode_option)
1960 if (fb_find_mode(&var, info, mode_option, NULL,
1961 0, &defaultmode, 8) == 0)
1962 var = default_var;
1963 }
1964
1965 var.accel_flags &= ~FB_ACCELF_TEXT;
1966 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1967
1968 if (aty128fb_check_var(&var, info)) {
1969 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1970 return 0;
1971 }
1972
1973 /* setup the DAC the way we like it */
1974 dac = aty_ld_le32(DAC_CNTL);
1975 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1976 dac |= DAC_MASK;
1977 if (par->chip_gen == rage_M3)
1978 dac |= DAC_PALETTE2_SNOOP_EN;
1979 aty_st_le32(DAC_CNTL, dac);
1980
1981 /* turn off bus mastering, just in case */
1982 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1983
1984 info->var = var;
1985 fb_alloc_cmap(&info->cmap, 256, 0);
1986
1987 var.activate = FB_ACTIVATE_NOW;
1988
1989 aty128_init_engine(par);
1990
1991 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1992 par->pdev = pdev;
1993 par->asleep = 0;
1994 par->lock_blank = 0;
1995
1996 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1997 if (backlight)
1998 aty128_bl_init(par);
1999 #endif
2000
2001 if (register_framebuffer(info) < 0)
2002 return 0;
2003
2004 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
2005 info->node, info->fix.id, video_card);
2006
2007 return 1; /* success! */
2008 }
2009
2010 #ifdef CONFIG_PCI
2011 /* register a card ++ajoshi */
2012 static int __devinit aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2013 {
2014 unsigned long fb_addr, reg_addr;
2015 struct aty128fb_par *par;
2016 struct fb_info *info;
2017 int err;
2018 #ifndef __sparc__
2019 void __iomem *bios = NULL;
2020 #endif
2021
2022 /* Enable device in PCI config */
2023 if ((err = pci_enable_device(pdev))) {
2024 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2025 err);
2026 return -ENODEV;
2027 }
2028
2029 fb_addr = pci_resource_start(pdev, 0);
2030 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2031 "aty128fb FB")) {
2032 printk(KERN_ERR "aty128fb: cannot reserve frame "
2033 "buffer memory\n");
2034 return -ENODEV;
2035 }
2036
2037 reg_addr = pci_resource_start(pdev, 2);
2038 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2039 "aty128fb MMIO")) {
2040 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2041 goto err_free_fb;
2042 }
2043
2044 /* We have the resources. Now virtualize them */
2045 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2046 if (info == NULL) {
2047 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2048 goto err_free_mmio;
2049 }
2050 par = info->par;
2051
2052 info->pseudo_palette = par->pseudo_palette;
2053
2054 /* Virtualize mmio region */
2055 info->fix.mmio_start = reg_addr;
2056 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
2057 if (!par->regbase)
2058 goto err_free_info;
2059
2060 /* Grab memory size from the card */
2061 // How does this relate to the resource length from the PCI hardware?
2062 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
2063
2064 /* Virtualize the framebuffer */
2065 info->screen_base = ioremap(fb_addr, par->vram_size);
2066 if (!info->screen_base)
2067 goto err_unmap_out;
2068
2069 /* Set up info->fix */
2070 info->fix = aty128fb_fix;
2071 info->fix.smem_start = fb_addr;
2072 info->fix.smem_len = par->vram_size;
2073 info->fix.mmio_start = reg_addr;
2074
2075 /* If we can't test scratch registers, something is seriously wrong */
2076 if (!register_test(par)) {
2077 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2078 goto err_out;
2079 }
2080
2081 #ifndef __sparc__
2082 bios = aty128_map_ROM(par, pdev);
2083 #ifdef CONFIG_X86
2084 if (bios == NULL)
2085 bios = aty128_find_mem_vbios(par);
2086 #endif
2087 if (bios == NULL)
2088 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2089 else {
2090 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2091 aty128_get_pllinfo(par, bios);
2092 pci_unmap_rom(pdev, bios);
2093 }
2094 #endif /* __sparc__ */
2095
2096 aty128_timings(par);
2097 pci_set_drvdata(pdev, info);
2098
2099 if (!aty128_init(pdev, ent))
2100 goto err_out;
2101
2102 #ifdef CONFIG_MTRR
2103 if (mtrr) {
2104 par->mtrr.vram = mtrr_add(info->fix.smem_start,
2105 par->vram_size, MTRR_TYPE_WRCOMB, 1);
2106 par->mtrr.vram_valid = 1;
2107 /* let there be speed */
2108 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2109 }
2110 #endif /* CONFIG_MTRR */
2111 return 0;
2112
2113 err_out:
2114 iounmap(info->screen_base);
2115 err_unmap_out:
2116 iounmap(par->regbase);
2117 err_free_info:
2118 framebuffer_release(info);
2119 err_free_mmio:
2120 release_mem_region(pci_resource_start(pdev, 2),
2121 pci_resource_len(pdev, 2));
2122 err_free_fb:
2123 release_mem_region(pci_resource_start(pdev, 0),
2124 pci_resource_len(pdev, 0));
2125 return -ENODEV;
2126 }
2127
2128 static void __devexit aty128_remove(struct pci_dev *pdev)
2129 {
2130 struct fb_info *info = pci_get_drvdata(pdev);
2131 struct aty128fb_par *par;
2132
2133 if (!info)
2134 return;
2135
2136 par = info->par;
2137
2138 unregister_framebuffer(info);
2139
2140 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2141 aty128_bl_exit(info->bl_dev);
2142 #endif
2143
2144 #ifdef CONFIG_MTRR
2145 if (par->mtrr.vram_valid)
2146 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2147 par->vram_size);
2148 #endif /* CONFIG_MTRR */
2149 iounmap(par->regbase);
2150 iounmap(info->screen_base);
2151
2152 release_mem_region(pci_resource_start(pdev, 0),
2153 pci_resource_len(pdev, 0));
2154 release_mem_region(pci_resource_start(pdev, 2),
2155 pci_resource_len(pdev, 2));
2156 framebuffer_release(info);
2157 }
2158 #endif /* CONFIG_PCI */
2159
2160
2161
2162 /*
2163 * Blank the display.
2164 */
2165 static int aty128fb_blank(int blank, struct fb_info *fb)
2166 {
2167 struct aty128fb_par *par = fb->par;
2168 u8 state = 0;
2169
2170 if (par->lock_blank || par->asleep)
2171 return 0;
2172
2173 if (blank & FB_BLANK_VSYNC_SUSPEND)
2174 state |= 2;
2175 if (blank & FB_BLANK_HSYNC_SUSPEND)
2176 state |= 1;
2177 if (blank & FB_BLANK_POWERDOWN)
2178 state |= 4;
2179
2180 aty_st_8(CRTC_EXT_CNTL+1, state);
2181
2182 if (par->chip_gen == rage_M3) {
2183 aty128_set_crt_enable(par, par->crt_on && !blank);
2184 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2185 }
2186
2187 return 0;
2188 }
2189
2190 /*
2191 * Set a single color register. The values supplied are already
2192 * rounded down to the hardware's capabilities (according to the
2193 * entries in the var structure). Return != 0 for invalid regno.
2194 */
2195 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2196 u_int transp, struct fb_info *info)
2197 {
2198 struct aty128fb_par *par = info->par;
2199
2200 if (regno > 255
2201 || (par->crtc.depth == 16 && regno > 63)
2202 || (par->crtc.depth == 15 && regno > 31))
2203 return 1;
2204
2205 red >>= 8;
2206 green >>= 8;
2207 blue >>= 8;
2208
2209 if (regno < 16) {
2210 int i;
2211 u32 *pal = info->pseudo_palette;
2212
2213 switch (par->crtc.depth) {
2214 case 15:
2215 pal[regno] = (regno << 10) | (regno << 5) | regno;
2216 break;
2217 case 16:
2218 pal[regno] = (regno << 11) | (regno << 6) | regno;
2219 break;
2220 case 24:
2221 pal[regno] = (regno << 16) | (regno << 8) | regno;
2222 break;
2223 case 32:
2224 i = (regno << 8) | regno;
2225 pal[regno] = (i << 16) | i;
2226 break;
2227 }
2228 }
2229
2230 if (par->crtc.depth == 16 && regno > 0) {
2231 /*
2232 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2233 * have 32 slots for R and B values but 64 slots for G values.
2234 * Thus the R and B values go in one slot but the G value
2235 * goes in a different slot, and we have to avoid disturbing
2236 * the other fields in the slots we touch.
2237 */
2238 par->green[regno] = green;
2239 if (regno < 32) {
2240 par->red[regno] = red;
2241 par->blue[regno] = blue;
2242 aty128_st_pal(regno * 8, red, par->green[regno*2],
2243 blue, par);
2244 }
2245 red = par->red[regno/2];
2246 blue = par->blue[regno/2];
2247 regno <<= 2;
2248 } else if (par->crtc.bpp == 16)
2249 regno <<= 3;
2250 aty128_st_pal(regno, red, green, blue, par);
2251
2252 return 0;
2253 }
2254
2255 #define ATY_MIRROR_LCD_ON 0x00000001
2256 #define ATY_MIRROR_CRT_ON 0x00000002
2257
2258 /* out param: u32* backlight value: 0 to 15 */
2259 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2260 /* in param: u32* backlight value: 0 to 15 */
2261 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2262
2263 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2264 {
2265 struct aty128fb_par *par = info->par;
2266 u32 value;
2267 int rc;
2268
2269 switch (cmd) {
2270 case FBIO_ATY128_SET_MIRROR:
2271 if (par->chip_gen != rage_M3)
2272 return -EINVAL;
2273 rc = get_user(value, (__u32 __user *)arg);
2274 if (rc)
2275 return rc;
2276 par->lcd_on = (value & 0x01) != 0;
2277 par->crt_on = (value & 0x02) != 0;
2278 if (!par->crt_on && !par->lcd_on)
2279 par->lcd_on = 1;
2280 aty128_set_crt_enable(par, par->crt_on);
2281 aty128_set_lcd_enable(par, par->lcd_on);
2282 return 0;
2283 case FBIO_ATY128_GET_MIRROR:
2284 if (par->chip_gen != rage_M3)
2285 return -EINVAL;
2286 value = (par->crt_on << 1) | par->lcd_on;
2287 return put_user(value, (__u32 __user *)arg);
2288 }
2289 return -EINVAL;
2290 }
2291
2292 #if 0
2293 /*
2294 * Accelerated functions
2295 */
2296
2297 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2298 u_int width, u_int height,
2299 struct fb_info_aty128 *par)
2300 {
2301 u32 save_dp_datatype, save_dp_cntl, dstval;
2302
2303 if (!width || !height)
2304 return;
2305
2306 dstval = depth_to_dst(par->current_par.crtc.depth);
2307 if (dstval == DST_24BPP) {
2308 srcx *= 3;
2309 dstx *= 3;
2310 width *= 3;
2311 } else if (dstval == -EINVAL) {
2312 printk("aty128fb: invalid depth or RGBA\n");
2313 return;
2314 }
2315
2316 wait_for_fifo(2, par);
2317 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2318 save_dp_cntl = aty_ld_le32(DP_CNTL);
2319
2320 wait_for_fifo(6, par);
2321 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2322 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2323 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2324 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2325
2326 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2327 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2328
2329 par->blitter_may_be_busy = 1;
2330
2331 wait_for_fifo(2, par);
2332 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2333 aty_st_le32(DP_CNTL, save_dp_cntl);
2334 }
2335
2336
2337 /*
2338 * Text mode accelerated functions
2339 */
2340
2341 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2342 int height, int width)
2343 {
2344 sx *= fontwidth(p);
2345 sy *= fontheight(p);
2346 dx *= fontwidth(p);
2347 dy *= fontheight(p);
2348 width *= fontwidth(p);
2349 height *= fontheight(p);
2350
2351 aty128_rectcopy(sx, sy, dx, dy, width, height,
2352 (struct fb_info_aty128 *)p->fb_info);
2353 }
2354 #endif /* 0 */
2355
2356 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2357 {
2358 u32 pmgt;
2359 u16 pwr_command;
2360 struct pci_dev *pdev = par->pdev;
2361
2362 if (!par->pm_reg)
2363 return;
2364
2365 /* Set the chip into the appropriate suspend mode (we use D2,
2366 * D3 would require a complete re-initialisation of the chip,
2367 * including PCI config registers, clocks, AGP configuration, ...)
2368 */
2369 if (suspend) {
2370 /* Make sure CRTC2 is reset. Remove that the day we decide to
2371 * actually use CRTC2 and replace it with real code for disabling
2372 * the CRTC2 output during sleep
2373 */
2374 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2375 ~(CRTC2_EN));
2376
2377 /* Set the power management mode to be PCI based */
2378 /* Use this magic value for now */
2379 pmgt = 0x0c005407;
2380 aty_st_pll(POWER_MANAGEMENT, pmgt);
2381 (void)aty_ld_pll(POWER_MANAGEMENT);
2382 aty_st_le32(BUS_CNTL1, 0x00000010);
2383 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2384 mdelay(100);
2385 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2386 /* Switch PCI power management to D2 */
2387 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2388 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2389 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2390 } else {
2391 /* Switch back PCI power management to D0 */
2392 mdelay(100);
2393 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2394 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2395 mdelay(100);
2396 }
2397 }
2398
2399 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2400 {
2401 struct fb_info *info = pci_get_drvdata(pdev);
2402 struct aty128fb_par *par = info->par;
2403
2404 /* We don't do anything but D2, for now we return 0, but
2405 * we may want to change that. How do we know if the BIOS
2406 * can properly take care of D3 ? Also, with swsusp, we
2407 * know we'll be rebooted, ...
2408 */
2409 #ifndef CONFIG_PPC_PMAC
2410 /* HACK ALERT ! Once I find a proper way to say to each driver
2411 * individually what will happen with it's PCI slot, I'll change
2412 * that. On laptops, the AGP slot is just unclocked, so D2 is
2413 * expected, while on desktops, the card is powered off
2414 */
2415 return 0;
2416 #endif /* CONFIG_PPC_PMAC */
2417
2418 if (state.event == pdev->dev.power.power_state.event)
2419 return 0;
2420
2421 printk(KERN_DEBUG "aty128fb: suspending...\n");
2422
2423 acquire_console_sem();
2424
2425 fb_set_suspend(info, 1);
2426
2427 /* Make sure engine is reset */
2428 wait_for_idle(par);
2429 aty128_reset_engine(par);
2430 wait_for_idle(par);
2431
2432 /* Blank display and LCD */
2433 aty128fb_blank(VESA_POWERDOWN, info);
2434
2435 /* Sleep */
2436 par->asleep = 1;
2437 par->lock_blank = 1;
2438
2439 #ifdef CONFIG_PPC_PMAC
2440 /* On powermac, we have hooks to properly suspend/resume AGP now,
2441 * use them here. We'll ultimately need some generic support here,
2442 * but the generic code isn't quite ready for that yet
2443 */
2444 pmac_suspend_agp_for_card(pdev);
2445 #endif /* CONFIG_PPC_PMAC */
2446
2447 /* We need a way to make sure the fbdev layer will _not_ touch the
2448 * framebuffer before we put the chip to suspend state. On 2.4, I
2449 * used dummy fb ops, 2.5 need proper support for this at the
2450 * fbdev level
2451 */
2452 if (state.event != PM_EVENT_ON)
2453 aty128_set_suspend(par, 1);
2454
2455 release_console_sem();
2456
2457 pdev->dev.power.power_state = state;
2458
2459 return 0;
2460 }
2461
2462 static int aty128_do_resume(struct pci_dev *pdev)
2463 {
2464 struct fb_info *info = pci_get_drvdata(pdev);
2465 struct aty128fb_par *par = info->par;
2466
2467 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2468 return 0;
2469
2470 /* Wakeup chip */
2471 aty128_set_suspend(par, 0);
2472 par->asleep = 0;
2473
2474 /* Restore display & engine */
2475 aty128_reset_engine(par);
2476 wait_for_idle(par);
2477 aty128fb_set_par(info);
2478 fb_pan_display(info, &info->var);
2479 fb_set_cmap(&info->cmap, info);
2480
2481 /* Refresh */
2482 fb_set_suspend(info, 0);
2483
2484 /* Unblank */
2485 par->lock_blank = 0;
2486 aty128fb_blank(0, info);
2487
2488 #ifdef CONFIG_PPC_PMAC
2489 /* On powermac, we have hooks to properly suspend/resume AGP now,
2490 * use them here. We'll ultimately need some generic support here,
2491 * but the generic code isn't quite ready for that yet
2492 */
2493 pmac_resume_agp_for_card(pdev);
2494 #endif /* CONFIG_PPC_PMAC */
2495
2496 pdev->dev.power.power_state = PMSG_ON;
2497
2498 printk(KERN_DEBUG "aty128fb: resumed !\n");
2499
2500 return 0;
2501 }
2502
2503 static int aty128_pci_resume(struct pci_dev *pdev)
2504 {
2505 int rc;
2506
2507 acquire_console_sem();
2508 rc = aty128_do_resume(pdev);
2509 release_console_sem();
2510
2511 return rc;
2512 }
2513
2514
2515 static int __devinit aty128fb_init(void)
2516 {
2517 #ifndef MODULE
2518 char *option = NULL;
2519
2520 if (fb_get_options("aty128fb", &option))
2521 return -ENODEV;
2522 aty128fb_setup(option);
2523 #endif
2524
2525 return pci_register_driver(&aty128fb_driver);
2526 }
2527
2528 static void __exit aty128fb_exit(void)
2529 {
2530 pci_unregister_driver(&aty128fb_driver);
2531 }
2532
2533 module_init(aty128fb_init);
2534
2535 module_exit(aty128fb_exit);
2536
2537 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2538 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2539 MODULE_LICENSE("GPL");
2540 module_param(mode_option, charp, 0);
2541 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2542 #ifdef CONFIG_MTRR
2543 module_param_named(nomtrr, mtrr, invbool, 0);
2544 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2545 #endif
2546
Linux with added FPC-III support