x86/mm: Use WRITE_ONCE() when setting PTEs
[linux/fpc-iii.git] / arch / arm64 / kernel / smp_spin_table.c
blob9a00eee9acc842993b9114b09f69998901a9cc06
1 /*
2 * Spin Table SMP initialisation
4 * Copyright (C) 2013 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/of.h>
22 #include <linux/smp.h>
23 #include <linux/types.h>
25 #include <asm/cacheflush.h>
26 #include <asm/cpu_ops.h>
27 #include <asm/cputype.h>
28 #include <asm/io.h>
29 #include <asm/smp_plat.h>
31 extern void secondary_holding_pen(void);
32 volatile unsigned long __section(".mmuoff.data.read")
33 secondary_holding_pen_release = INVALID_HWID;
35 static phys_addr_t cpu_release_addr[NR_CPUS];
38 * Write secondary_holding_pen_release in a way that is guaranteed to be
39 * visible to all observers, irrespective of whether they're taking part
40 * in coherency or not. This is necessary for the hotplug code to work
41 * reliably.
43 static void write_pen_release(u64 val)
45 void *start = (void *)&secondary_holding_pen_release;
46 unsigned long size = sizeof(secondary_holding_pen_release);
48 secondary_holding_pen_release = val;
49 __flush_dcache_area(start, size);
53 static int smp_spin_table_cpu_init(unsigned int cpu)
55 struct device_node *dn;
56 int ret;
58 dn = of_get_cpu_node(cpu, NULL);
59 if (!dn)
60 return -ENODEV;
63 * Determine the address from which the CPU is polling.
65 ret = of_property_read_u64(dn, "cpu-release-addr",
66 &cpu_release_addr[cpu]);
67 if (ret)
68 pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
69 cpu);
71 of_node_put(dn);
73 return ret;
76 static int smp_spin_table_cpu_prepare(unsigned int cpu)
78 __le64 __iomem *release_addr;
80 if (!cpu_release_addr[cpu])
81 return -ENODEV;
84 * The cpu-release-addr may or may not be inside the linear mapping.
85 * As ioremap_cache will either give us a new mapping or reuse the
86 * existing linear mapping, we can use it to cover both cases. In
87 * either case the memory will be MT_NORMAL.
89 release_addr = ioremap_cache(cpu_release_addr[cpu],
90 sizeof(*release_addr));
91 if (!release_addr)
92 return -ENOMEM;
95 * We write the release address as LE regardless of the native
96 * endianess of the kernel. Therefore, any boot-loaders that
97 * read this address need to convert this address to the
98 * boot-loader's endianess before jumping. This is mandated by
99 * the boot protocol.
101 writeq_relaxed(__pa(secondary_holding_pen), release_addr);
102 __flush_dcache_area((__force void *)release_addr,
103 sizeof(*release_addr));
106 * Send an event to wake up the secondary CPU.
108 sev();
110 iounmap(release_addr);
112 return 0;
115 static int smp_spin_table_cpu_boot(unsigned int cpu)
118 * Update the pen release flag.
120 write_pen_release(cpu_logical_map(cpu));
123 * Send an event, causing the secondaries to read pen_release.
125 sev();
127 return 0;
130 const struct cpu_operations smp_spin_table_ops = {
131 .name = "spin-table",
132 .cpu_init = smp_spin_table_cpu_init,
133 .cpu_prepare = smp_spin_table_cpu_prepare,
134 .cpu_boot = smp_spin_table_cpu_boot,