drm/radeon: fix voltage setup on hawaii
[linux/fpc-iii.git] / arch / cris / include / asm / io.h
blob752a3f45df60cd475b51b21bb567b9bd48f90581
1 #ifndef _ASM_CRIS_IO_H
2 #define _ASM_CRIS_IO_H
4 #include <asm/page.h> /* for __va, __pa */
5 #include <arch/io.h>
6 #include <asm-generic/iomap.h>
7 #include <linux/kernel.h>
9 struct cris_io_operations
11 u32 (*read_mem)(void *addr, int size);
12 void (*write_mem)(u32 val, int size, void *addr);
13 u32 (*read_io)(u32 port, void *addr, int size, int count);
14 void (*write_io)(u32 port, void *addr, int size, int count);
17 #ifdef CONFIG_PCI
18 extern struct cris_io_operations *cris_iops;
19 #else
20 #define cris_iops ((struct cris_io_operations*)NULL)
21 #endif
24 * Change virtual addresses to physical addresses and vv.
27 static inline unsigned long virt_to_phys(volatile void * address)
29 return __pa(address);
32 static inline void * phys_to_virt(unsigned long address)
34 return __va(address);
37 extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
38 extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
40 static inline void __iomem * ioremap (unsigned long offset, unsigned long size)
42 return __ioremap(offset, size, 0);
45 extern void iounmap(volatile void * __iomem addr);
47 extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
50 * IO bus memory addresses are also 1:1 with the physical address
52 #define virt_to_bus virt_to_phys
53 #define bus_to_virt phys_to_virt
56 * readX/writeX() are used to access memory mapped devices. On some
57 * architectures the memory mapped IO stuff needs to be accessed
58 * differently. On the CRIS architecture, we just read/write the
59 * memory location directly.
61 #ifdef CONFIG_PCI
62 #define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
63 #else
64 #define PCI_SPACE(x) 0
65 #endif
66 static inline unsigned char readb(const volatile void __iomem *addr)
68 if (PCI_SPACE(addr) && cris_iops)
69 return cris_iops->read_mem((void*)addr, 1);
70 else
71 return *(volatile unsigned char __force *) addr;
73 static inline unsigned short readw(const volatile void __iomem *addr)
75 if (PCI_SPACE(addr) && cris_iops)
76 return cris_iops->read_mem((void*)addr, 2);
77 else
78 return *(volatile unsigned short __force *) addr;
80 static inline unsigned int readl(const volatile void __iomem *addr)
82 if (PCI_SPACE(addr) && cris_iops)
83 return cris_iops->read_mem((void*)addr, 4);
84 else
85 return *(volatile unsigned int __force *) addr;
87 #define readb_relaxed(addr) readb(addr)
88 #define readw_relaxed(addr) readw(addr)
89 #define readl_relaxed(addr) readl(addr)
90 #define __raw_readb readb
91 #define __raw_readw readw
92 #define __raw_readl readl
94 static inline void writeb(unsigned char b, volatile void __iomem *addr)
96 if (PCI_SPACE(addr) && cris_iops)
97 cris_iops->write_mem(b, 1, (void*)addr);
98 else
99 *(volatile unsigned char __force *) addr = b;
101 static inline void writew(unsigned short b, volatile void __iomem *addr)
103 if (PCI_SPACE(addr) && cris_iops)
104 cris_iops->write_mem(b, 2, (void*)addr);
105 else
106 *(volatile unsigned short __force *) addr = b;
108 static inline void writel(unsigned int b, volatile void __iomem *addr)
110 if (PCI_SPACE(addr) && cris_iops)
111 cris_iops->write_mem(b, 4, (void*)addr);
112 else
113 *(volatile unsigned int __force *) addr = b;
115 #define writeb_relaxed(b, addr) writeb(b, addr)
116 #define writew_relaxed(b, addr) writew(b, addr)
117 #define writel_relaxed(b, addr) writel(b, addr)
118 #define __raw_writeb writeb
119 #define __raw_writew writew
120 #define __raw_writel writel
122 #define mmiowb()
124 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
125 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
126 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
129 /* I/O port access. Normally there is no I/O space on CRIS but when
130 * Cardbus/PCI is enabled the request is passed through the bridge.
133 #define IO_SPACE_LIMIT 0xffff
134 #define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
135 #define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
136 #define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
137 #define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
138 #define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
139 #define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
140 static inline void outb(unsigned char data, unsigned int port)
142 if (cris_iops)
143 cris_iops->write_io(port, (void *) &data, 1, 1);
145 static inline void outw(unsigned short data, unsigned int port)
147 if (cris_iops)
148 cris_iops->write_io(port, (void *) &data, 2, 1);
150 static inline void outl(unsigned int data, unsigned int port)
152 if (cris_iops)
153 cris_iops->write_io(port, (void *) &data, 4, 1);
155 static inline void outsb(unsigned int port, const void *addr,
156 unsigned long count)
158 if (cris_iops)
159 cris_iops->write_io(port, (void *)addr, 1, count);
161 static inline void outsw(unsigned int port, const void *addr,
162 unsigned long count)
164 if (cris_iops)
165 cris_iops->write_io(port, (void *)addr, 2, count);
167 static inline void outsl(unsigned int port, const void *addr,
168 unsigned long count)
170 if (cris_iops)
171 cris_iops->write_io(port, (void *)addr, 4, count);
174 #define inb_p(port) inb(port)
175 #define inw_p(port) inw(port)
176 #define inl_p(port) inl(port)
177 #define outb_p(val, port) outb((val), (port))
178 #define outw_p(val, port) outw((val), (port))
179 #define outl_p(val, port) outl((val), (port))
182 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
183 * access
185 #define xlate_dev_mem_ptr(p) __va(p)
188 * Convert a virtual cached pointer to an uncached pointer
190 #define xlate_dev_kmem_ptr(p) p
192 #endif