1 #ifndef _PARISC_BITOPS_H
2 #define _PARISC_BITOPS_H
4 #ifndef _LINUX_BITOPS_H
5 #error only <linux/bitops.h> can be included directly
8 #include <linux/compiler.h>
9 #include <asm/types.h> /* for BITS_PER_LONG/SHIFT_PER_LONG */
10 #include <asm/byteorder.h>
11 #include <asm/barrier.h>
12 #include <linux/atomic.h>
15 * HP-PARISC specific bit operations
16 * for a detailed description of the functions please refer
17 * to include/asm-i386/bitops.h or kerneldoc
20 #define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
23 /* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
24 * on use of volatile and __*_bit() (set/clear/change):
25 * *_bit() want use of volatile.
26 * __*_bit() are "relaxed" and don't use spinlock or volatile.
29 static __inline__
void set_bit(int nr
, volatile unsigned long * addr
)
31 unsigned long mask
= 1UL << CHOP_SHIFTCOUNT(nr
);
34 addr
+= (nr
>> SHIFT_PER_LONG
);
35 _atomic_spin_lock_irqsave(addr
, flags
);
37 _atomic_spin_unlock_irqrestore(addr
, flags
);
40 static __inline__
void clear_bit(int nr
, volatile unsigned long * addr
)
42 unsigned long mask
= ~(1UL << CHOP_SHIFTCOUNT(nr
));
45 addr
+= (nr
>> SHIFT_PER_LONG
);
46 _atomic_spin_lock_irqsave(addr
, flags
);
48 _atomic_spin_unlock_irqrestore(addr
, flags
);
51 static __inline__
void change_bit(int nr
, volatile unsigned long * addr
)
53 unsigned long mask
= 1UL << CHOP_SHIFTCOUNT(nr
);
56 addr
+= (nr
>> SHIFT_PER_LONG
);
57 _atomic_spin_lock_irqsave(addr
, flags
);
59 _atomic_spin_unlock_irqrestore(addr
, flags
);
62 static __inline__
int test_and_set_bit(int nr
, volatile unsigned long * addr
)
64 unsigned long mask
= 1UL << CHOP_SHIFTCOUNT(nr
);
69 addr
+= (nr
>> SHIFT_PER_LONG
);
70 _atomic_spin_lock_irqsave(addr
, flags
);
72 set
= (old
& mask
) ? 1 : 0;
75 _atomic_spin_unlock_irqrestore(addr
, flags
);
80 static __inline__
int test_and_clear_bit(int nr
, volatile unsigned long * addr
)
82 unsigned long mask
= 1UL << CHOP_SHIFTCOUNT(nr
);
87 addr
+= (nr
>> SHIFT_PER_LONG
);
88 _atomic_spin_lock_irqsave(addr
, flags
);
90 set
= (old
& mask
) ? 1 : 0;
93 _atomic_spin_unlock_irqrestore(addr
, flags
);
98 static __inline__
int test_and_change_bit(int nr
, volatile unsigned long * addr
)
100 unsigned long mask
= 1UL << CHOP_SHIFTCOUNT(nr
);
101 unsigned long oldbit
;
104 addr
+= (nr
>> SHIFT_PER_LONG
);
105 _atomic_spin_lock_irqsave(addr
, flags
);
107 *addr
= oldbit
^ mask
;
108 _atomic_spin_unlock_irqrestore(addr
, flags
);
110 return (oldbit
& mask
) ? 1 : 0;
113 #include <asm-generic/bitops/non-atomic.h>
118 * __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
119 * @word: The word to search
121 * __ffs() return is undefined if no bit is set.
123 * 32-bit fast __ffs by LaMont Jones "lamont At hp com".
124 * 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
125 * (with help from willy/jejb to get the semantics right)
127 * This algorithm avoids branches by making use of nullification.
128 * One side effect of "extr" instructions is it sets PSW[N] bit.
129 * How PSW[N] (nullify next insn) gets set is determined by the
130 * "condition" field (eg "<>" or "TR" below) in the extr* insn.
131 * Only the 1st and one of either the 2cd or 3rd insn will get executed.
132 * Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
133 * cycles for each mispredicted branch.
136 static __inline__
unsigned long __ffs(unsigned long x
)
143 " extrd,u,*<> %0,63,32,%%r0\n"
144 " extrd,u,*TR %0,31,32,%0\n" /* move top 32-bits down */
149 " extru,<> %0,31,16,%%r0\n"
150 " extru,TR %0,15,16,%0\n" /* xxxx0000 -> 0000xxxx */
152 " extru,<> %0,31,8,%%r0\n"
153 " extru,TR %0,23,8,%0\n" /* 0000xx00 -> 000000xx */
155 " extru,<> %0,31,4,%%r0\n"
156 " extru,TR %0,27,4,%0\n" /* 000000x0 -> 0000000x */
158 " extru,<> %0,31,2,%%r0\n"
159 " extru,TR %0,29,2,%0\n" /* 0000000y, 1100b -> 0011b */
161 " extru,= %0,31,1,%%r0\n" /* check last bit */
163 : "+r" (x
), "=r" (ret
) );
167 #include <asm-generic/bitops/ffz.h>
170 * ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
171 * This is defined the same way as the libc and compiler builtin
172 * ffs routines, therefore differs in spirit from the above ffz (man ffs).
174 static __inline__
int ffs(int x
)
176 return x
? (__ffs((unsigned long)x
) + 1) : 0;
180 * fls: find last (most significant) bit set.
181 * fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
184 static __inline__
int fls(int x
)
192 " extru,<> %0,15,16,%%r0\n"
193 " zdep,TR %0,15,16,%0\n" /* xxxx0000 */
195 " extru,<> %0,7,8,%%r0\n"
196 " zdep,TR %0,23,24,%0\n" /* xx000000 */
198 " extru,<> %0,3,4,%%r0\n"
199 " zdep,TR %0,27,28,%0\n" /* x0000000 */
201 " extru,<> %0,1,2,%%r0\n"
202 " zdep,TR %0,29,30,%0\n" /* y0000000 (y&3 = 0) */
204 " extru,= %0,0,1,%%r0\n"
205 " addi 1,%1,%1\n" /* if y & 8, add 1 */
206 : "+r" (x
), "=r" (ret
) );
211 #include <asm-generic/bitops/__fls.h>
212 #include <asm-generic/bitops/fls64.h>
213 #include <asm-generic/bitops/hweight.h>
214 #include <asm-generic/bitops/lock.h>
215 #include <asm-generic/bitops/sched.h>
217 #endif /* __KERNEL__ */
219 #include <asm-generic/bitops/find.h>
223 #include <asm-generic/bitops/le.h>
224 #include <asm-generic/bitops/ext2-atomic-setbit.h>
226 #endif /* __KERNEL__ */
228 #endif /* _PARISC_BITOPS_H */