Linux 3.4.102
[linux/fpc-iii.git] / drivers / crypto / talitos.h
blob3c173954ef295d618da2084e5082b940708536b5
1 /*
2 * Freescale SEC (talitos) device register and descriptor header defines
4 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
35 /* global register offset addresses */
36 #define TALITOS_MCR 0x1030 /* master control register */
37 #define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
38 #define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
39 #define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
40 #define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
41 #define TALITOS_MCR_SWR 0x1 /* s/w reset */
42 #define TALITOS_MCR_LO 0x1034
43 #define TALITOS_IMR 0x1008 /* interrupt mask register */
44 #define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
45 #define TALITOS_IMR_DONE 0x00055 /* done IRQs */
46 #define TALITOS_IMR_LO 0x100C
47 #define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
48 #define TALITOS_ISR 0x1010 /* interrupt status register */
49 #define TALITOS_ISR_4CHERR 0xaa /* 4 channel errors mask */
50 #define TALITOS_ISR_4CHDONE 0x55 /* 4 channel done mask */
51 #define TALITOS_ISR_CH_0_2_ERR 0x22 /* channels 0, 2 errors mask */
52 #define TALITOS_ISR_CH_0_2_DONE 0x11 /* channels 0, 2 done mask */
53 #define TALITOS_ISR_CH_1_3_ERR 0x88 /* channels 1, 3 errors mask */
54 #define TALITOS_ISR_CH_1_3_DONE 0x44 /* channels 1, 3 done mask */
55 #define TALITOS_ISR_LO 0x1014
56 #define TALITOS_ICR 0x1018 /* interrupt clear register */
57 #define TALITOS_ICR_LO 0x101C
59 /* channel register address stride */
60 #define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
61 #define TALITOS_CH_STRIDE 0x100
63 /* channel configuration register */
64 #define TALITOS_CCCR 0x8
65 #define TALITOS_CCCR_CONT 0x2 /* channel continue */
66 #define TALITOS_CCCR_RESET 0x1 /* channel reset */
67 #define TALITOS_CCCR_LO 0xc
68 #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
69 #define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
70 #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
71 #define TALITOS_CCCR_LO_NT 0x4 /* notification type */
72 #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
74 /* CCPSR: channel pointer status register */
75 #define TALITOS_CCPSR 0x10
76 #define TALITOS_CCPSR_LO 0x14
77 #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
78 #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
79 #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
80 #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
81 #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
82 #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
83 #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
84 #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
85 #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
86 #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
87 #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
88 #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
90 /* channel fetch fifo register */
91 #define TALITOS_FF 0x48
92 #define TALITOS_FF_LO 0x4c
94 /* current descriptor pointer register */
95 #define TALITOS_CDPR 0x40
96 #define TALITOS_CDPR_LO 0x44
98 /* descriptor buffer register */
99 #define TALITOS_DESCBUF 0x80
100 #define TALITOS_DESCBUF_LO 0x84
102 /* gather link table */
103 #define TALITOS_GATHER 0xc0
104 #define TALITOS_GATHER_LO 0xc4
106 /* scatter link table */
107 #define TALITOS_SCATTER 0xe0
108 #define TALITOS_SCATTER_LO 0xe4
110 /* execution unit interrupt status registers */
111 #define TALITOS_DEUISR 0x2030 /* DES unit */
112 #define TALITOS_DEUISR_LO 0x2034
113 #define TALITOS_AESUISR 0x4030 /* AES unit */
114 #define TALITOS_AESUISR_LO 0x4034
115 #define TALITOS_MDEUISR 0x6030 /* message digest unit */
116 #define TALITOS_MDEUISR_LO 0x6034
117 #define TALITOS_MDEUICR 0x6038 /* interrupt control */
118 #define TALITOS_MDEUICR_LO 0x603c
119 #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
120 #define TALITOS_AFEUISR 0x8030 /* arc4 unit */
121 #define TALITOS_AFEUISR_LO 0x8034
122 #define TALITOS_RNGUISR 0xa030 /* random number unit */
123 #define TALITOS_RNGUISR_LO 0xa034
124 #define TALITOS_RNGUSR 0xa028 /* rng status */
125 #define TALITOS_RNGUSR_LO 0xa02c
126 #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
127 #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
128 #define TALITOS_RNGUDSR 0xa010 /* data size */
129 #define TALITOS_RNGUDSR_LO 0xa014
130 #define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */
131 #define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */
132 #define TALITOS_RNGURCR 0xa018 /* reset control */
133 #define TALITOS_RNGURCR_LO 0xa01c
134 #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
135 #define TALITOS_PKEUISR 0xc030 /* public key unit */
136 #define TALITOS_PKEUISR_LO 0xc034
137 #define TALITOS_KEUISR 0xe030 /* kasumi unit */
138 #define TALITOS_KEUISR_LO 0xe034
139 #define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/
140 #define TALITOS_CRCUISR_LO 0xf034
142 #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
143 #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
146 * talitos descriptor header (hdr) bits
149 /* written back when done */
150 #define DESC_HDR_DONE cpu_to_be32(0xff000000)
151 #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
152 #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
153 #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
155 /* primary execution unit select */
156 #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
157 #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
158 #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
159 #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
160 #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
161 #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
162 #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
163 #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
164 #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
165 #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
167 /* primary execution unit mode (MODE0) and derivatives */
168 #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
169 #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
170 #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
171 #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
172 #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
173 #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
174 #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
175 #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
176 #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
177 #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
178 #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
179 #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
180 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
181 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
182 #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
183 DESC_HDR_MODE0_MDEU_HMAC)
184 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
185 DESC_HDR_MODE0_MDEU_HMAC)
186 #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
187 DESC_HDR_MODE0_MDEU_HMAC)
189 /* secondary execution unit select (SEL1) */
190 #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
191 #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
192 #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
193 #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
195 /* secondary execution unit mode (MODE1) and derivatives */
196 #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
197 #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
198 #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
199 #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
200 #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
201 #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
202 #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
203 #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
204 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
205 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
206 #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
207 DESC_HDR_MODE1_MDEU_HMAC)
208 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
209 DESC_HDR_MODE1_MDEU_HMAC)
210 #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
211 DESC_HDR_MODE1_MDEU_HMAC)
213 /* direction of overall data flow (DIR) */
214 #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
216 /* request done notification (DN) */
217 #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
219 /* descriptor types */
220 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
221 #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
222 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
223 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
225 /* link table extent field bits */
226 #define DESC_PTR_LNKTBL_JUMP 0x80
227 #define DESC_PTR_LNKTBL_RETURN 0x02
228 #define DESC_PTR_LNKTBL_NEXT 0x01