?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.4.102
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-i801.c
blobd63e130690e99faf5c47542dbe92cb254205ef49
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 Avoton (SOC) 0x1f3c 32 hard yes yes yes
57
58 Features supported by this driver:
59 Software PEC no
60 Hardware PEC yes
61 Block buffer yes
62 Block process call transaction no
63 I2C block read transaction yes (doesn't use the block buffer)
64 Slave mode no
65
66 See the file Documentation/i2c/busses/i2c-i801 for details.
67 */
68
69 #include <linux/module.h>
70 #include <linux/pci.h>
71 #include <linux/kernel.h>
72 #include <linux/stddef.h>
73 #include <linux/delay.h>
74 #include <linux/ioport.h>
75 #include <linux/init.h>
76 #include <linux/i2c.h>
77 #include <linux/acpi.h>
78 #include <linux/io.h>
79 #include <linux/dmi.h>
80 #include <linux/slab.h>
81
82 /* I801 SMBus address offsets */
83 #define SMBHSTSTS(p) (0 + (p)->smba)
84 #define SMBHSTCNT(p) (2 + (p)->smba)
85 #define SMBHSTCMD(p) (3 + (p)->smba)
86 #define SMBHSTADD(p) (4 + (p)->smba)
87 #define SMBHSTDAT0(p) (5 + (p)->smba)
88 #define SMBHSTDAT1(p) (6 + (p)->smba)
89 #define SMBBLKDAT(p) (7 + (p)->smba)
90 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
91 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
92 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
93
94 /* PCI Address Constants */
95 #define SMBBAR 4
96 #define SMBHSTCFG 0x040
97
98 /* Host configuration bits for SMBHSTCFG */
99 #define SMBHSTCFG_HST_EN 1
100 #define SMBHSTCFG_SMB_SMI_EN 2
101 #define SMBHSTCFG_I2C_EN 4
102
103 /* Auxiliary control register bits, ICH4+ only */
104 #define SMBAUXCTL_CRC 1
105 #define SMBAUXCTL_E32B 2
106
107 /* kill bit for SMBHSTCNT */
108 #define SMBHSTCNT_KILL 2
109
110 /* Other settings */
111 #define MAX_RETRIES 400
112 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
113
114 /* I801 command constants */
115 #define I801_QUICK 0x00
116 #define I801_BYTE 0x04
117 #define I801_BYTE_DATA 0x08
118 #define I801_WORD_DATA 0x0C
119 #define I801_PROC_CALL 0x10 /* unimplemented */
120 #define I801_BLOCK_DATA 0x14
121 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
122 #define I801_BLOCK_LAST 0x34
123 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
124 #define I801_START 0x40
125 #define I801_PEC_EN 0x80 /* ICH3 and later */
126
127 /* I801 Hosts Status register bits */
128 #define SMBHSTSTS_BYTE_DONE 0x80
129 #define SMBHSTSTS_INUSE_STS 0x40
130 #define SMBHSTSTS_SMBALERT_STS 0x20
131 #define SMBHSTSTS_FAILED 0x10
132 #define SMBHSTSTS_BUS_ERR 0x08
133 #define SMBHSTSTS_DEV_ERR 0x04
134 #define SMBHSTSTS_INTR 0x02
135 #define SMBHSTSTS_HOST_BUSY 0x01
136
137 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
138 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
139 SMBHSTSTS_INTR)
140
141 /* Older devices have their ID defined in <linux/pci_ids.h> */
142 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
143 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
144 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
145 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
146 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
147 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
148 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
149 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
150 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
151 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
152 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
153 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
154
155 struct i801_priv {
156 struct i2c_adapter adapter;
157 unsigned long smba;
158 unsigned char original_hstcfg;
159 struct pci_dev *pci_dev;
160 unsigned int features;
161 };
162
163 static struct pci_driver i801_driver;
164
165 #define FEATURE_SMBUS_PEC (1 << 0)
166 #define FEATURE_BLOCK_BUFFER (1 << 1)
167 #define FEATURE_BLOCK_PROC (1 << 2)
168 #define FEATURE_I2C_BLOCK_READ (1 << 3)
169 /* Not really a feature, but it's convenient to handle it as such */
170 #define FEATURE_IDF (1 << 15)
171
172 static const char *i801_feature_names[] = {
173 "SMBus PEC",
174 "Block buffer",
175 "Block process call",
176 "I2C block read",
177 };
178
179 static unsigned int disable_features;
180 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
181 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
182
183 /* Make sure the SMBus host is ready to start transmitting.
184 Return 0 if it is, -EBUSY if it is not. */
185 static int i801_check_pre(struct i801_priv *priv)
186 {
187 int status;
188
189 status = inb_p(SMBHSTSTS(priv));
190 if (status & SMBHSTSTS_HOST_BUSY) {
191 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
192 return -EBUSY;
193 }
194
195 status &= STATUS_FLAGS;
196 if (status) {
197 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
198 status);
199 outb_p(status, SMBHSTSTS(priv));
200 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
201 if (status) {
202 dev_err(&priv->pci_dev->dev,
203 "Failed clearing status flags (%02x)\n",
204 status);
205 return -EBUSY;
206 }
207 }
208
209 return 0;
210 }
211
212 /* Convert the status register to an error code, and clear it. */
213 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
214 {
215 int result = 0;
216
217 /* If the SMBus is still busy, we give up */
218 if (timeout) {
219 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
220 /* try to stop the current command */
221 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
222 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
223 SMBHSTCNT(priv));
224 usleep_range(1000, 2000);
225 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
226 SMBHSTCNT(priv));
227
228 /* Check if it worked */
229 status = inb_p(SMBHSTSTS(priv));
230 if ((status & SMBHSTSTS_HOST_BUSY) ||
231 !(status & SMBHSTSTS_FAILED))
232 dev_err(&priv->pci_dev->dev,
233 "Failed terminating the transaction\n");
234 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
235 return -ETIMEDOUT;
236 }
237
238 if (status & SMBHSTSTS_FAILED) {
239 result = -EIO;
240 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
241 }
242 if (status & SMBHSTSTS_DEV_ERR) {
243 result = -ENXIO;
244 dev_dbg(&priv->pci_dev->dev, "No response\n");
245 }
246 if (status & SMBHSTSTS_BUS_ERR) {
247 result = -EAGAIN;
248 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
249 }
250
251 if (result) {
252 /* Clear error flags */
253 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
254 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
255 if (status) {
256 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
257 "flags at end of transaction (%02x)\n",
258 status);
259 }
260 }
261
262 return result;
263 }
264
265 static int i801_transaction(struct i801_priv *priv, int xact)
266 {
267 int status;
268 int result;
269 int timeout = 0;
270
271 result = i801_check_pre(priv);
272 if (result < 0)
273 return result;
274
275 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
276 * INTREN, SMBSCMD are passed in xact */
277 outb_p(xact | I801_START, SMBHSTCNT(priv));
278
279 /* We will always wait for a fraction of a second! */
280 do {
281 usleep_range(250, 500);
282 status = inb_p(SMBHSTSTS(priv));
283 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_RETRIES));
284
285 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
286 if (result < 0)
287 return result;
288
289 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
290 return 0;
291 }
292
293 /* wait for INTR bit as advised by Intel */
294 static void i801_wait_hwpec(struct i801_priv *priv)
295 {
296 int timeout = 0;
297 int status;
298
299 do {
300 usleep_range(250, 500);
301 status = inb_p(SMBHSTSTS(priv));
302 } while ((!(status & SMBHSTSTS_INTR))
303 && (timeout++ < MAX_RETRIES));
304
305 if (timeout > MAX_RETRIES)
306 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
307
308 outb_p(status, SMBHSTSTS(priv));
309 }
310
311 static int i801_block_transaction_by_block(struct i801_priv *priv,
312 union i2c_smbus_data *data,
313 char read_write, int hwpec)
314 {
315 int i, len;
316 int status;
317
318 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
319
320 /* Use 32-byte buffer to process this transaction */
321 if (read_write == I2C_SMBUS_WRITE) {
322 len = data->block[0];
323 outb_p(len, SMBHSTDAT0(priv));
324 for (i = 0; i < len; i++)
325 outb_p(data->block[i+1], SMBBLKDAT(priv));
326 }
327
328 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
329 I801_PEC_EN * hwpec);
330 if (status)
331 return status;
332
333 if (read_write == I2C_SMBUS_READ) {
334 len = inb_p(SMBHSTDAT0(priv));
335 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
336 return -EPROTO;
337
338 data->block[0] = len;
339 for (i = 0; i < len; i++)
340 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
341 }
342 return 0;
343 }
344
345 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
346 union i2c_smbus_data *data,
347 char read_write, int command,
348 int hwpec)
349 {
350 int i, len;
351 int smbcmd;
352 int status;
353 int result;
354 int timeout;
355
356 result = i801_check_pre(priv);
357 if (result < 0)
358 return result;
359
360 len = data->block[0];
361
362 if (read_write == I2C_SMBUS_WRITE) {
363 outb_p(len, SMBHSTDAT0(priv));
364 outb_p(data->block[1], SMBBLKDAT(priv));
365 }
366
367 for (i = 1; i <= len; i++) {
368 if (i == len && read_write == I2C_SMBUS_READ) {
369 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
370 smbcmd = I801_I2C_BLOCK_LAST;
371 else
372 smbcmd = I801_BLOCK_LAST;
373 } else {
374 if (command == I2C_SMBUS_I2C_BLOCK_DATA
375 && read_write == I2C_SMBUS_READ)
376 smbcmd = I801_I2C_BLOCK_DATA;
377 else
378 smbcmd = I801_BLOCK_DATA;
379 }
380 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
381
382 if (i == 1)
383 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
384 SMBHSTCNT(priv));
385
386 /* We will always wait for a fraction of a second! */
387 timeout = 0;
388 do {
389 usleep_range(250, 500);
390 status = inb_p(SMBHSTSTS(priv));
391 } while ((!(status & SMBHSTSTS_BYTE_DONE))
392 && (timeout++ < MAX_RETRIES));
393
394 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
395 if (result < 0)
396 return result;
397
398 if (i == 1 && read_write == I2C_SMBUS_READ
399 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
400 len = inb_p(SMBHSTDAT0(priv));
401 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
402 dev_err(&priv->pci_dev->dev,
403 "Illegal SMBus block read size %d\n",
404 len);
405 /* Recover */
406 while (inb_p(SMBHSTSTS(priv)) &
407 SMBHSTSTS_HOST_BUSY)
408 outb_p(SMBHSTSTS_BYTE_DONE,
409 SMBHSTSTS(priv));
410 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
411 return -EPROTO;
412 }
413 data->block[0] = len;
414 }
415
416 /* Retrieve/store value in SMBBLKDAT */
417 if (read_write == I2C_SMBUS_READ)
418 data->block[i] = inb_p(SMBBLKDAT(priv));
419 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
420 outb_p(data->block[i+1], SMBBLKDAT(priv));
421
422 /* signals SMBBLKDAT ready */
423 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
424 }
425
426 return 0;
427 }
428
429 static int i801_set_block_buffer_mode(struct i801_priv *priv)
430 {
431 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
432 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
433 return -EIO;
434 return 0;
435 }
436
437 /* Block transaction function */
438 static int i801_block_transaction(struct i801_priv *priv,
439 union i2c_smbus_data *data, char read_write,
440 int command, int hwpec)
441 {
442 int result = 0;
443 unsigned char hostc;
444
445 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
446 if (read_write == I2C_SMBUS_WRITE) {
447 /* set I2C_EN bit in configuration register */
448 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
449 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
450 hostc | SMBHSTCFG_I2C_EN);
451 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
452 dev_err(&priv->pci_dev->dev,
453 "I2C block read is unsupported!\n");
454 return -EOPNOTSUPP;
455 }
456 }
457
458 if (read_write == I2C_SMBUS_WRITE
459 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
460 if (data->block[0] < 1)
461 data->block[0] = 1;
462 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
463 data->block[0] = I2C_SMBUS_BLOCK_MAX;
464 } else {
465 data->block[0] = 32; /* max for SMBus block reads */
466 }
467
468 /* Experience has shown that the block buffer can only be used for
469 SMBus (not I2C) block transactions, even though the datasheet
470 doesn't mention this limitation. */
471 if ((priv->features & FEATURE_BLOCK_BUFFER)
472 && command != I2C_SMBUS_I2C_BLOCK_DATA
473 && i801_set_block_buffer_mode(priv) == 0)
474 result = i801_block_transaction_by_block(priv, data,
475 read_write, hwpec);
476 else
477 result = i801_block_transaction_byte_by_byte(priv, data,
478 read_write,
479 command, hwpec);
480
481 if (result == 0 && hwpec)
482 i801_wait_hwpec(priv);
483
484 if (command == I2C_SMBUS_I2C_BLOCK_DATA
485 && read_write == I2C_SMBUS_WRITE) {
486 /* restore saved configuration register value */
487 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
488 }
489 return result;
490 }
491
492 /* Return negative errno on error. */
493 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
494 unsigned short flags, char read_write, u8 command,
495 int size, union i2c_smbus_data *data)
496 {
497 int hwpec;
498 int block = 0;
499 int ret, xact = 0;
500 struct i801_priv *priv = i2c_get_adapdata(adap);
501
502 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
503 && size != I2C_SMBUS_QUICK
504 && size != I2C_SMBUS_I2C_BLOCK_DATA;
505
506 switch (size) {
507 case I2C_SMBUS_QUICK:
508 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
509 SMBHSTADD(priv));
510 xact = I801_QUICK;
511 break;
512 case I2C_SMBUS_BYTE:
513 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
514 SMBHSTADD(priv));
515 if (read_write == I2C_SMBUS_WRITE)
516 outb_p(command, SMBHSTCMD(priv));
517 xact = I801_BYTE;
518 break;
519 case I2C_SMBUS_BYTE_DATA:
520 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
521 SMBHSTADD(priv));
522 outb_p(command, SMBHSTCMD(priv));
523 if (read_write == I2C_SMBUS_WRITE)
524 outb_p(data->byte, SMBHSTDAT0(priv));
525 xact = I801_BYTE_DATA;
526 break;
527 case I2C_SMBUS_WORD_DATA:
528 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
529 SMBHSTADD(priv));
530 outb_p(command, SMBHSTCMD(priv));
531 if (read_write == I2C_SMBUS_WRITE) {
532 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
533 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
534 }
535 xact = I801_WORD_DATA;
536 break;
537 case I2C_SMBUS_BLOCK_DATA:
538 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
539 SMBHSTADD(priv));
540 outb_p(command, SMBHSTCMD(priv));
541 block = 1;
542 break;
543 case I2C_SMBUS_I2C_BLOCK_DATA:
544 /* NB: page 240 of ICH5 datasheet shows that the R/#W
545 * bit should be cleared here, even when reading */
546 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
547 if (read_write == I2C_SMBUS_READ) {
548 /* NB: page 240 of ICH5 datasheet also shows
549 * that DATA1 is the cmd field when reading */
550 outb_p(command, SMBHSTDAT1(priv));
551 } else
552 outb_p(command, SMBHSTCMD(priv));
553 block = 1;
554 break;
555 default:
556 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
557 size);
558 return -EOPNOTSUPP;
559 }
560
561 if (hwpec) /* enable/disable hardware PEC */
562 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
563 else
564 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
565 SMBAUXCTL(priv));
566
567 if (block)
568 ret = i801_block_transaction(priv, data, read_write, size,
569 hwpec);
570 else
571 ret = i801_transaction(priv, xact | ENABLE_INT9);
572
573 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
574 time, so we forcibly disable it after every transaction. Turn off
575 E32B for the same reason. */
576 if (hwpec || block)
577 outb_p(inb_p(SMBAUXCTL(priv)) &
578 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
579
580 if (block)
581 return ret;
582 if (ret)
583 return ret;
584 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
585 return 0;
586
587 switch (xact & 0x7f) {
588 case I801_BYTE: /* Result put in SMBHSTDAT0 */
589 case I801_BYTE_DATA:
590 data->byte = inb_p(SMBHSTDAT0(priv));
591 break;
592 case I801_WORD_DATA:
593 data->word = inb_p(SMBHSTDAT0(priv)) +
594 (inb_p(SMBHSTDAT1(priv)) << 8);
595 break;
596 }
597 return 0;
598 }
599
600
601 static u32 i801_func(struct i2c_adapter *adapter)
602 {
603 struct i801_priv *priv = i2c_get_adapdata(adapter);
604
605 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
606 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
607 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
608 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
609 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
610 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
611 }
612
613 static const struct i2c_algorithm smbus_algorithm = {
614 .smbus_xfer = i801_access,
615 .functionality = i801_func,
616 };
617
618 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
636 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
637 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
638 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
639 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
640 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
641 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
642 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
643 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
644 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
645 { 0, }
646 };
647
648 MODULE_DEVICE_TABLE(pci, i801_ids);
649
650 #if defined CONFIG_X86 && defined CONFIG_DMI
651 static unsigned char apanel_addr;
652
653 /* Scan the system ROM for the signature "FJKEYINF" */
654 static __init const void __iomem *bios_signature(const void __iomem *bios)
655 {
656 ssize_t offset;
657 const unsigned char signature[] = "FJKEYINF";
658
659 for (offset = 0; offset < 0x10000; offset += 0x10) {
660 if (check_signature(bios + offset, signature,
661 sizeof(signature)-1))
662 return bios + offset;
663 }
664 return NULL;
665 }
666
667 static void __init input_apanel_init(void)
668 {
669 void __iomem *bios;
670 const void __iomem *p;
671
672 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
673 p = bios_signature(bios);
674 if (p) {
675 /* just use the first address */
676 apanel_addr = readb(p + 8 + 3) >> 1;
677 }
678 iounmap(bios);
679 }
680
681 struct dmi_onboard_device_info {
682 const char *name;
683 u8 type;
684 unsigned short i2c_addr;
685 const char *i2c_type;
686 };
687
688 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
689 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
690 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
691 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
692 };
693
694 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
695 struct i2c_adapter *adap)
696 {
697 int i;
698 struct i2c_board_info info;
699
700 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
701 /* & ~0x80, ignore enabled/disabled bit */
702 if ((type & ~0x80) != dmi_devices[i].type)
703 continue;
704 if (strcasecmp(name, dmi_devices[i].name))
705 continue;
706
707 memset(&info, 0, sizeof(struct i2c_board_info));
708 info.addr = dmi_devices[i].i2c_addr;
709 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
710 i2c_new_device(adap, &info);
711 break;
712 }
713 }
714
715 /* We use our own function to check for onboard devices instead of
716 dmi_find_device() as some buggy BIOS's have the devices we are interested
717 in marked as disabled */
718 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
719 void *adap)
720 {
721 int i, count;
722
723 if (dm->type != 10)
724 return;
725
726 count = (dm->length - sizeof(struct dmi_header)) / 2;
727 for (i = 0; i < count; i++) {
728 const u8 *d = (char *)(dm + 1) + (i * 2);
729 const char *name = ((char *) dm) + dm->length;
730 u8 type = d[0];
731 u8 s = d[1];
732
733 if (!s)
734 continue;
735 s--;
736 while (s > 0 && name[0]) {
737 name += strlen(name) + 1;
738 s--;
739 }
740 if (name[0] == 0) /* Bogus string reference */
741 continue;
742
743 dmi_check_onboard_device(type, name, adap);
744 }
745 }
746
747 /* Register optional slaves */
748 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
749 {
750 /* Only register slaves on main SMBus channel */
751 if (priv->features & FEATURE_IDF)
752 return;
753
754 if (apanel_addr) {
755 struct i2c_board_info info;
756
757 memset(&info, 0, sizeof(struct i2c_board_info));
758 info.addr = apanel_addr;
759 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
760 i2c_new_device(&priv->adapter, &info);
761 }
762
763 if (dmi_name_in_vendors("FUJITSU"))
764 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
765 }
766 #else
767 static void __init input_apanel_init(void) {}
768 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
769 #endif /* CONFIG_X86 && CONFIG_DMI */
770
771 static int __devinit i801_probe(struct pci_dev *dev,
772 const struct pci_device_id *id)
773 {
774 unsigned char temp;
775 int err, i;
776 struct i801_priv *priv;
777
778 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
779 if (!priv)
780 return -ENOMEM;
781
782 i2c_set_adapdata(&priv->adapter, priv);
783 priv->adapter.owner = THIS_MODULE;
784 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
785 priv->adapter.algo = &smbus_algorithm;
786
787 priv->pci_dev = dev;
788 switch (dev->device) {
789 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
790 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
791 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
792 priv->features |= FEATURE_IDF;
793 /* fall through */
794 default:
795 priv->features |= FEATURE_I2C_BLOCK_READ;
796 /* fall through */
797 case PCI_DEVICE_ID_INTEL_82801DB_3:
798 priv->features |= FEATURE_SMBUS_PEC;
799 priv->features |= FEATURE_BLOCK_BUFFER;
800 /* fall through */
801 case PCI_DEVICE_ID_INTEL_82801CA_3:
802 case PCI_DEVICE_ID_INTEL_82801BA_2:
803 case PCI_DEVICE_ID_INTEL_82801AB_3:
804 case PCI_DEVICE_ID_INTEL_82801AA_3:
805 break;
806 }
807
808 /* Disable features on user request */
809 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
810 if (priv->features & disable_features & (1 << i))
811 dev_notice(&dev->dev, "%s disabled by user\n",
812 i801_feature_names[i]);
813 }
814 priv->features &= ~disable_features;
815
816 err = pci_enable_device(dev);
817 if (err) {
818 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
819 err);
820 goto exit;
821 }
822
823 /* Determine the address of the SMBus area */
824 priv->smba = pci_resource_start(dev, SMBBAR);
825 if (!priv->smba) {
826 dev_err(&dev->dev, "SMBus base address uninitialized, "
827 "upgrade BIOS\n");
828 err = -ENODEV;
829 goto exit;
830 }
831
832 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
833 if (err) {
834 err = -ENODEV;
835 goto exit;
836 }
837
838 err = pci_request_region(dev, SMBBAR, i801_driver.name);
839 if (err) {
840 dev_err(&dev->dev, "Failed to request SMBus region "
841 "0x%lx-0x%Lx\n", priv->smba,
842 (unsigned long long)pci_resource_end(dev, SMBBAR));
843 goto exit;
844 }
845
846 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
847 priv->original_hstcfg = temp;
848 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
849 if (!(temp & SMBHSTCFG_HST_EN)) {
850 dev_info(&dev->dev, "Enabling SMBus device\n");
851 temp |= SMBHSTCFG_HST_EN;
852 }
853 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
854
855 if (temp & SMBHSTCFG_SMB_SMI_EN)
856 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
857 else
858 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
859
860 /* Clear special mode bits */
861 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
862 outb_p(inb_p(SMBAUXCTL(priv)) &
863 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
864
865 /* set up the sysfs linkage to our parent device */
866 priv->adapter.dev.parent = &dev->dev;
867
868 /* Retry up to 3 times on lost arbitration */
869 priv->adapter.retries = 3;
870
871 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
872 "SMBus I801 adapter at %04lx", priv->smba);
873 err = i2c_add_adapter(&priv->adapter);
874 if (err) {
875 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
876 goto exit_release;
877 }
878
879 i801_probe_optional_slaves(priv);
880
881 pci_set_drvdata(dev, priv);
882 return 0;
883
884 exit_release:
885 pci_release_region(dev, SMBBAR);
886 exit:
887 kfree(priv);
888 return err;
889 }
890
891 static void __devexit i801_remove(struct pci_dev *dev)
892 {
893 struct i801_priv *priv = pci_get_drvdata(dev);
894
895 i2c_del_adapter(&priv->adapter);
896 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
897 pci_release_region(dev, SMBBAR);
898 pci_set_drvdata(dev, NULL);
899 kfree(priv);
900 /*
901 * do not call pci_disable_device(dev) since it can cause hard hangs on
902 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
903 */
904 }
905
906 #ifdef CONFIG_PM
907 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
908 {
909 struct i801_priv *priv = pci_get_drvdata(dev);
910
911 pci_save_state(dev);
912 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
913 pci_set_power_state(dev, pci_choose_state(dev, mesg));
914 return 0;
915 }
916
917 static int i801_resume(struct pci_dev *dev)
918 {
919 pci_set_power_state(dev, PCI_D0);
920 pci_restore_state(dev);
921 return pci_enable_device(dev);
922 }
923 #else
924 #define i801_suspend NULL
925 #define i801_resume NULL
926 #endif
927
928 static struct pci_driver i801_driver = {
929 .name = "i801_smbus",
930 .id_table = i801_ids,
931 .probe = i801_probe,
932 .remove = __devexit_p(i801_remove),
933 .suspend = i801_suspend,
934 .resume = i801_resume,
935 };
936
937 static int __init i2c_i801_init(void)
938 {
939 if (dmi_name_in_vendors("FUJITSU"))
940 input_apanel_init();
941 return pci_register_driver(&i801_driver);
942 }
943
944 static void __exit i2c_i801_exit(void)
945 {
946 pci_unregister_driver(&i801_driver);
947 }
948
949 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
950 "Jean Delvare <khali@linux-fr.org>");
951 MODULE_DESCRIPTION("I801 SMBus driver");
952 MODULE_LICENSE("GPL");
953
954 module_init(i2c_i801_init);
955 module_exit(i2c_i801_exit);
Linux with added FPC-III support