drivers/infiniband/hw/cxgb4/iw_cxgb4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __IW_CXGB4_H__
  32 #define __IW_CXGB4_H__
  33
  34 #include <linux/mutex.h>
  35 #include <linux/list.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/idr.h>
  38 #include <linux/completion.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/inet.h>
  44 #include <linux/wait.h>
  45 #include <linux/kref.h>
  46 #include <linux/timer.h>
  47 #include <linux/io.h>
  48 #include <linux/kfifo.h>
  49
  50 #include <asm/byteorder.h>
  51
  52 #include <net/net_namespace.h>
  53
  54 #include <rdma/ib_verbs.h>
  55 #include <rdma/iw_cm.h>
  56
  57 #include "cxgb4.h"
  58 #include "cxgb4_uld.h"
  59 #include "l2t.h"
  60 #include "user.h"
  61
  62 #define DRV_NAME "iw_cxgb4"
  63 #define MOD DRV_NAME ":"
  64
  65 extern int c4iw_debug;
  66 #define PDBG(fmt, args...) \
  67 do { \
  68         if (c4iw_debug) \
  69                 printk(MOD fmt, ## args); \
  70 } while (0)
  71
  72 #include "t4.h"
  73
  74 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
  75 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
  76
  77 static inline void *cplhdr(struct sk_buff *skb)
  78 {
  79         return skb->data;
  80 }
  81
  82 struct c4iw_resource {
  83         struct kfifo tpt_fifo;
  84         spinlock_t tpt_fifo_lock;
  85         struct kfifo qid_fifo;
  86         spinlock_t qid_fifo_lock;
  87         struct kfifo pdid_fifo;
  88         spinlock_t pdid_fifo_lock;
  89 };
  90
  91 struct c4iw_qid_list {
  92         struct list_head entry;
  93         u32 qid;
  94 };
  95
  96 struct c4iw_dev_ucontext {
  97         struct list_head qpids;
  98         struct list_head cqids;
  99         struct mutex lock;
 100 };
 101
 102 enum c4iw_rdev_flags {
 103         T4_FATAL_ERROR = (1<<0),
 104 };
 105
 106 struct c4iw_rdev {
 107         struct c4iw_resource resource;
 108         unsigned long qpshift;
 109         u32 qpmask;
 110         unsigned long cqshift;
 111         u32 cqmask;
 112         struct c4iw_dev_ucontext uctx;
 113         struct gen_pool *pbl_pool;
 114         struct gen_pool *rqt_pool;
 115         struct gen_pool *ocqp_pool;
 116         u32 flags;
 117         struct cxgb4_lld_info lldi;
 118         unsigned long oc_mw_pa;
 119         void __iomem *oc_mw_kva;
 120 };
 121
 122 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
 123 {
 124         return rdev->flags & T4_FATAL_ERROR;
 125 }
 126
 127 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
 128 {
 129         return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
 130 }
 131
 132 #define C4IW_WR_TO (10*HZ)
 133
 134 struct c4iw_wr_wait {
 135         struct completion completion;
 136         int ret;
 137 };
 138
 139 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
 140 {
 141         wr_waitp->ret = 0;
 142         init_completion(&wr_waitp->completion);
 143 }
 144
 145 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
 146 {
 147         wr_waitp->ret = ret;
 148         complete(&wr_waitp->completion);
 149 }
 150
 151 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
 152                                  struct c4iw_wr_wait *wr_waitp,
 153                                  u32 hwtid, u32 qpid,
 154                                  const char *func)
 155 {
 156         unsigned to = C4IW_WR_TO;
 157         int ret;
 158
 159         do {
 160                 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
 161                 if (!ret) {
 162                         printk(KERN_ERR MOD "%s - Device %s not responding - "
 163                                "tid %u qpid %u\n", func,
 164                                pci_name(rdev->lldi.pdev), hwtid, qpid);
 165                         if (c4iw_fatal_error(rdev)) {
 166                                 wr_waitp->ret = -EIO;
 167                                 break;
 168                         }
 169                         to = to << 2;
 170                 }
 171         } while (!ret);
 172         if (wr_waitp->ret)
 173                 PDBG("%s: FW reply %d tid %u qpid %u\n",
 174                      pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
 175         return wr_waitp->ret;
 176 }
 177
 178 struct c4iw_dev {
 179         struct ib_device ibdev;
 180         struct c4iw_rdev rdev;
 181         u32 device_cap_flags;
 182         struct idr cqidr;
 183         struct idr qpidr;
 184         struct idr mmidr;
 185         spinlock_t lock;
 186         struct dentry *debugfs_root;
 187 };
 188
 189 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
 190 {
 191         return container_of(ibdev, struct c4iw_dev, ibdev);
 192 }
 193
 194 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
 195 {
 196         return container_of(rdev, struct c4iw_dev, rdev);
 197 }
 198
 199 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
 200 {
 201         return idr_find(&rhp->cqidr, cqid);
 202 }
 203
 204 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
 205 {
 206         return idr_find(&rhp->qpidr, qpid);
 207 }
 208
 209 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
 210 {
 211         return idr_find(&rhp->mmidr, mmid);
 212 }
 213
 214 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 215                                 void *handle, u32 id)
 216 {
 217         int ret;
 218         int newid;
 219
 220         do {
 221                 if (!idr_pre_get(idr, GFP_KERNEL))
 222                         return -ENOMEM;
 223                 spin_lock_irq(&rhp->lock);
 224                 ret = idr_get_new_above(idr, handle, id, &newid);
 225                 BUG_ON(newid != id);
 226                 spin_unlock_irq(&rhp->lock);
 227         } while (ret == -EAGAIN);
 228
 229         return ret;
 230 }
 231
 232 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
 233 {
 234         spin_lock_irq(&rhp->lock);
 235         idr_remove(idr, id);
 236         spin_unlock_irq(&rhp->lock);
 237 }
 238
 239 struct c4iw_pd {
 240         struct ib_pd ibpd;
 241         u32 pdid;
 242         struct c4iw_dev *rhp;
 243 };
 244
 245 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
 246 {
 247         return container_of(ibpd, struct c4iw_pd, ibpd);
 248 }
 249
 250 struct tpt_attributes {
 251         u64 len;
 252         u64 va_fbo;
 253         enum fw_ri_mem_perms perms;
 254         u32 stag;
 255         u32 pdid;
 256         u32 qpid;
 257         u32 pbl_addr;
 258         u32 pbl_size;
 259         u32 state:1;
 260         u32 type:2;
 261         u32 rsvd:1;
 262         u32 remote_invaliate_disable:1;
 263         u32 zbva:1;
 264         u32 mw_bind_enable:1;
 265         u32 page_size:5;
 266 };
 267
 268 struct c4iw_mr {
 269         struct ib_mr ibmr;
 270         struct ib_umem *umem;
 271         struct c4iw_dev *rhp;
 272         u64 kva;
 273         struct tpt_attributes attr;
 274 };
 275
 276 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
 277 {
 278         return container_of(ibmr, struct c4iw_mr, ibmr);
 279 }
 280
 281 struct c4iw_mw {
 282         struct ib_mw ibmw;
 283         struct c4iw_dev *rhp;
 284         u64 kva;
 285         struct tpt_attributes attr;
 286 };
 287
 288 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
 289 {
 290         return container_of(ibmw, struct c4iw_mw, ibmw);
 291 }
 292
 293 struct c4iw_fr_page_list {
 294         struct ib_fast_reg_page_list ibpl;
 295         DEFINE_DMA_UNMAP_ADDR(mapping);
 296         dma_addr_t dma_addr;
 297         struct c4iw_dev *dev;
 298         int size;
 299 };
 300
 301 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
 302                                         struct ib_fast_reg_page_list *ibpl)
 303 {
 304         return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
 305 }
 306
 307 struct c4iw_cq {
 308         struct ib_cq ibcq;
 309         struct c4iw_dev *rhp;
 310         struct t4_cq cq;
 311         spinlock_t lock;
 312         spinlock_t comp_handler_lock;
 313         atomic_t refcnt;
 314         wait_queue_head_t wait;
 315 };
 316
 317 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
 318 {
 319         return container_of(ibcq, struct c4iw_cq, ibcq);
 320 }
 321
 322 struct c4iw_mpa_attributes {
 323         u8 initiator;
 324         u8 recv_marker_enabled;
 325         u8 xmit_marker_enabled;
 326         u8 crc_enabled;
 327         u8 enhanced_rdma_conn;
 328         u8 version;
 329         u8 p2p_type;
 330 };
 331
 332 struct c4iw_qp_attributes {
 333         u32 scq;
 334         u32 rcq;
 335         u32 sq_num_entries;
 336         u32 rq_num_entries;
 337         u32 sq_max_sges;
 338         u32 sq_max_sges_rdma_write;
 339         u32 rq_max_sges;
 340         u32 state;
 341         u8 enable_rdma_read;
 342         u8 enable_rdma_write;
 343         u8 enable_bind;
 344         u8 enable_mmid0_fastreg;
 345         u32 max_ord;
 346         u32 max_ird;
 347         u32 pd;
 348         u32 next_state;
 349         char terminate_buffer[52];
 350         u32 terminate_msg_len;
 351         u8 is_terminate_local;
 352         struct c4iw_mpa_attributes mpa_attr;
 353         struct c4iw_ep *llp_stream_handle;
 354         u8 layer_etype;
 355         u8 ecode;
 356 };
 357
 358 struct c4iw_qp {
 359         struct ib_qp ibqp;
 360         struct c4iw_dev *rhp;
 361         struct c4iw_ep *ep;
 362         struct c4iw_qp_attributes attr;
 363         struct t4_wq wq;
 364         spinlock_t lock;
 365         struct mutex mutex;
 366         atomic_t refcnt;
 367         wait_queue_head_t wait;
 368         struct timer_list timer;
 369 };
 370
 371 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
 372 {
 373         return container_of(ibqp, struct c4iw_qp, ibqp);
 374 }
 375
 376 struct c4iw_ucontext {
 377         struct ib_ucontext ibucontext;
 378         struct c4iw_dev_ucontext uctx;
 379         u32 key;
 380         spinlock_t mmap_lock;
 381         struct list_head mmaps;
 382 };
 383
 384 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
 385 {
 386         return container_of(c, struct c4iw_ucontext, ibucontext);
 387 }
 388
 389 struct c4iw_mm_entry {
 390         struct list_head entry;
 391         u64 addr;
 392         u32 key;
 393         unsigned len;
 394 };
 395
 396 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
 397                                                 u32 key, unsigned len)
 398 {
 399         struct list_head *pos, *nxt;
 400         struct c4iw_mm_entry *mm;
 401
 402         spin_lock(&ucontext->mmap_lock);
 403         list_for_each_safe(pos, nxt, &ucontext->mmaps) {
 404
 405                 mm = list_entry(pos, struct c4iw_mm_entry, entry);
 406                 if (mm->key == key && mm->len == len) {
 407                         list_del_init(&mm->entry);
 408                         spin_unlock(&ucontext->mmap_lock);
 409                         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 410                              key, (unsigned long long) mm->addr, mm->len);
 411                         return mm;
 412                 }
 413         }
 414         spin_unlock(&ucontext->mmap_lock);
 415         return NULL;
 416 }
 417
 418 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
 419                                struct c4iw_mm_entry *mm)
 420 {
 421         spin_lock(&ucontext->mmap_lock);
 422         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 423              mm->key, (unsigned long long) mm->addr, mm->len);
 424         list_add_tail(&mm->entry, &ucontext->mmaps);
 425         spin_unlock(&ucontext->mmap_lock);
 426 }
 427
 428 enum c4iw_qp_attr_mask {
 429         C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
 430         C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
 431         C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
 432         C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
 433         C4IW_QP_ATTR_MAX_ORD = 1 << 11,
 434         C4IW_QP_ATTR_MAX_IRD = 1 << 12,
 435         C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
 436         C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
 437         C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
 438         C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
 439         C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
 440                                      C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
 441                                      C4IW_QP_ATTR_MAX_ORD |
 442                                      C4IW_QP_ATTR_MAX_IRD |
 443                                      C4IW_QP_ATTR_LLP_STREAM_HANDLE |
 444                                      C4IW_QP_ATTR_STREAM_MSG_BUFFER |
 445                                      C4IW_QP_ATTR_MPA_ATTR |
 446                                      C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
 447 };
 448
 449 int c4iw_modify_qp(struct c4iw_dev *rhp,
 450                                 struct c4iw_qp *qhp,
 451                                 enum c4iw_qp_attr_mask mask,
 452                                 struct c4iw_qp_attributes *attrs,
 453                                 int internal);
 454
 455 enum c4iw_qp_state {
 456         C4IW_QP_STATE_IDLE,
 457         C4IW_QP_STATE_RTS,
 458         C4IW_QP_STATE_ERROR,
 459         C4IW_QP_STATE_TERMINATE,
 460         C4IW_QP_STATE_CLOSING,
 461         C4IW_QP_STATE_TOT
 462 };
 463
 464 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
 465 {
 466         switch (ib_state) {
 467         case IB_QPS_RESET:
 468         case IB_QPS_INIT:
 469                 return C4IW_QP_STATE_IDLE;
 470         case IB_QPS_RTS:
 471                 return C4IW_QP_STATE_RTS;
 472         case IB_QPS_SQD:
 473                 return C4IW_QP_STATE_CLOSING;
 474         case IB_QPS_SQE:
 475                 return C4IW_QP_STATE_TERMINATE;
 476         case IB_QPS_ERR:
 477                 return C4IW_QP_STATE_ERROR;
 478         default:
 479                 return -1;
 480         }
 481 }
 482
 483 static inline u32 c4iw_ib_to_tpt_access(int a)
 484 {
 485         return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 486                (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
 487                (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
 488                FW_RI_MEM_ACCESS_LOCAL_READ;
 489 }
 490
 491 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
 492 {
 493         return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 494                (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
 495 }
 496
 497 enum c4iw_mmid_state {
 498         C4IW_STAG_STATE_VALID,
 499         C4IW_STAG_STATE_INVALID
 500 };
 501
 502 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
 503
 504 #define MPA_KEY_REQ "MPA ID Req Frame"
 505 #define MPA_KEY_REP "MPA ID Rep Frame"
 506
 507 #define MPA_MAX_PRIVATE_DATA    256
 508 #define MPA_ENHANCED_RDMA_CONN  0x10
 509 #define MPA_REJECT              0x20
 510 #define MPA_CRC                 0x40
 511 #define MPA_MARKERS             0x80
 512 #define MPA_FLAGS_MASK          0xE0
 513
 514 #define MPA_V2_PEER2PEER_MODEL          0x8000
 515 #define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
 516 #define MPA_V2_RDMA_WRITE_RTR           0x8000
 517 #define MPA_V2_RDMA_READ_RTR            0x4000
 518 #define MPA_V2_IRD_ORD_MASK             0x3FFF
 519
 520 #define c4iw_put_ep(ep) { \
 521         PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
 522              ep, atomic_read(&((ep)->kref.refcount))); \
 523         WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
 524         kref_put(&((ep)->kref), _c4iw_free_ep); \
 525 }
 526
 527 #define c4iw_get_ep(ep) { \
 528         PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
 529              ep, atomic_read(&((ep)->kref.refcount))); \
 530         kref_get(&((ep)->kref));  \
 531 }
 532 void _c4iw_free_ep(struct kref *kref);
 533
 534 struct mpa_message {
 535         u8 key[16];
 536         u8 flags;
 537         u8 revision;
 538         __be16 private_data_size;
 539         u8 private_data[0];
 540 };
 541
 542 struct mpa_v2_conn_params {
 543         __be16 ird;
 544         __be16 ord;
 545 };
 546
 547 struct terminate_message {
 548         u8 layer_etype;
 549         u8 ecode;
 550         __be16 hdrct_rsvd;
 551         u8 len_hdrs[0];
 552 };
 553
 554 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
 555
 556 enum c4iw_layers_types {
 557         LAYER_RDMAP             = 0x00,
 558         LAYER_DDP               = 0x10,
 559         LAYER_MPA               = 0x20,
 560         RDMAP_LOCAL_CATA        = 0x00,
 561         RDMAP_REMOTE_PROT       = 0x01,
 562         RDMAP_REMOTE_OP         = 0x02,
 563         DDP_LOCAL_CATA          = 0x00,
 564         DDP_TAGGED_ERR          = 0x01,
 565         DDP_UNTAGGED_ERR        = 0x02,
 566         DDP_LLP                 = 0x03
 567 };
 568
 569 enum c4iw_rdma_ecodes {
 570         RDMAP_INV_STAG          = 0x00,
 571         RDMAP_BASE_BOUNDS       = 0x01,
 572         RDMAP_ACC_VIOL          = 0x02,
 573         RDMAP_STAG_NOT_ASSOC    = 0x03,
 574         RDMAP_TO_WRAP           = 0x04,
 575         RDMAP_INV_VERS          = 0x05,
 576         RDMAP_INV_OPCODE        = 0x06,
 577         RDMAP_STREAM_CATA       = 0x07,
 578         RDMAP_GLOBAL_CATA       = 0x08,
 579         RDMAP_CANT_INV_STAG     = 0x09,
 580         RDMAP_UNSPECIFIED       = 0xff
 581 };
 582
 583 enum c4iw_ddp_ecodes {
 584         DDPT_INV_STAG           = 0x00,
 585         DDPT_BASE_BOUNDS        = 0x01,
 586         DDPT_STAG_NOT_ASSOC     = 0x02,
 587         DDPT_TO_WRAP            = 0x03,
 588         DDPT_INV_VERS           = 0x04,
 589         DDPU_INV_QN             = 0x01,
 590         DDPU_INV_MSN_NOBUF      = 0x02,
 591         DDPU_INV_MSN_RANGE      = 0x03,
 592         DDPU_INV_MO             = 0x04,
 593         DDPU_MSG_TOOBIG         = 0x05,
 594         DDPU_INV_VERS           = 0x06
 595 };
 596
 597 enum c4iw_mpa_ecodes {
 598         MPA_CRC_ERR             = 0x02,
 599         MPA_MARKER_ERR          = 0x03,
 600         MPA_LOCAL_CATA          = 0x05,
 601         MPA_INSUFF_IRD          = 0x06,
 602         MPA_NOMATCH_RTR         = 0x07,
 603 };
 604
 605 enum c4iw_ep_state {
 606         IDLE = 0,
 607         LISTEN,
 608         CONNECTING,
 609         MPA_REQ_WAIT,
 610         MPA_REQ_SENT,
 611         MPA_REQ_RCVD,
 612         MPA_REP_SENT,
 613         FPDU_MODE,
 614         ABORTING,
 615         CLOSING,
 616         MORIBUND,
 617         DEAD,
 618 };
 619
 620 enum c4iw_ep_flags {
 621         PEER_ABORT_IN_PROGRESS  = 0,
 622         ABORT_REQ_IN_PROGRESS   = 1,
 623         RELEASE_RESOURCES       = 2,
 624         CLOSE_SENT              = 3,
 625 };
 626
 627 struct c4iw_ep_common {
 628         struct iw_cm_id *cm_id;
 629         struct c4iw_qp *qp;
 630         struct c4iw_dev *dev;
 631         enum c4iw_ep_state state;
 632         struct kref kref;
 633         struct mutex mutex;
 634         struct sockaddr_in local_addr;
 635         struct sockaddr_in remote_addr;
 636         struct c4iw_wr_wait wr_wait;
 637         unsigned long flags;
 638 };
 639
 640 struct c4iw_listen_ep {
 641         struct c4iw_ep_common com;
 642         unsigned int stid;
 643         int backlog;
 644 };
 645
 646 struct c4iw_ep {
 647         struct c4iw_ep_common com;
 648         struct c4iw_ep *parent_ep;
 649         struct timer_list timer;
 650         struct list_head entry;
 651         unsigned int atid;
 652         u32 hwtid;
 653         u32 snd_seq;
 654         u32 rcv_seq;
 655         struct l2t_entry *l2t;
 656         struct dst_entry *dst;
 657         struct sk_buff *mpa_skb;
 658         struct c4iw_mpa_attributes mpa_attr;
 659         u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
 660         unsigned int mpa_pkt_len;
 661         u32 ird;
 662         u32 ord;
 663         u32 smac_idx;
 664         u32 tx_chan;
 665         u32 mtu;
 666         u16 mss;
 667         u16 emss;
 668         u16 plen;
 669         u16 rss_qid;
 670         u16 txq_idx;
 671         u16 ctrlq_idx;
 672         u8 tos;
 673         u8 retry_with_mpa_v1;
 674         u8 tried_with_mpa_v1;
 675 };
 676
 677 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
 678 {
 679         return cm_id->provider_data;
 680 }
 681
 682 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
 683 {
 684         return cm_id->provider_data;
 685 }
 686
 687 static inline int compute_wscale(int win)
 688 {
 689         int wscale = 0;
 690
 691         while (wscale < 14 && (65535<<wscale) < win)
 692                 wscale++;
 693         return wscale;
 694 }
 695
 696 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
 697
 698 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 699                      struct l2t_entry *l2t);
 700 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
 701                    struct c4iw_dev_ucontext *uctx);
 702 u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
 703 void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
 704 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
 705 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
 706 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 707 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
 708 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
 709 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 710 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 711 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
 712 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 713 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
 714 int c4iw_register_device(struct c4iw_dev *dev);
 715 void c4iw_unregister_device(struct c4iw_dev *dev);
 716 int __init c4iw_cm_init(void);
 717 void __exit c4iw_cm_term(void);
 718 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
 719                                struct c4iw_dev_ucontext *uctx);
 720 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
 721                             struct c4iw_dev_ucontext *uctx);
 722 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 723 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 724                       struct ib_send_wr **bad_wr);
 725 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 726                       struct ib_recv_wr **bad_wr);
 727 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
 728                  struct ib_mw_bind *mw_bind);
 729 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 730 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
 731 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
 732 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 733 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
 734 void c4iw_qp_add_ref(struct ib_qp *qp);
 735 void c4iw_qp_rem_ref(struct ib_qp *qp);
 736 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
 737 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
 738                                         struct ib_device *device,
 739                                         int page_list_len);
 740 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
 741 int c4iw_dealloc_mw(struct ib_mw *mw);
 742 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
 743 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
 744                                            u64 length, u64 virt, int acc,
 745                                            struct ib_udata *udata);
 746 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
 747 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
 748                                         struct ib_phys_buf *buffer_list,
 749                                         int num_phys_buf,
 750                                         int acc,
 751                                         u64 *iova_start);
 752 int c4iw_reregister_phys_mem(struct ib_mr *mr,
 753                                      int mr_rereg_mask,
 754                                      struct ib_pd *pd,
 755                                      struct ib_phys_buf *buffer_list,
 756                                      int num_phys_buf,
 757                                      int acc, u64 *iova_start);
 758 int c4iw_dereg_mr(struct ib_mr *ib_mr);
 759 int c4iw_destroy_cq(struct ib_cq *ib_cq);
 760 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
 761                                         int vector,
 762                                         struct ib_ucontext *ib_context,
 763                                         struct ib_udata *udata);
 764 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
 765 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 766 int c4iw_destroy_qp(struct ib_qp *ib_qp);
 767 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
 768                              struct ib_qp_init_attr *attrs,
 769                              struct ib_udata *udata);
 770 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 771                                  int attr_mask, struct ib_udata *udata);
 772 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
 773 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
 774 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 775 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
 776 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 777 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
 778 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 779 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
 780 void c4iw_flush_hw_cq(struct t4_cq *cq);
 781 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 782 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 783 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
 784 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
 785 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
 786 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
 787 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
 788 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
 789 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 790 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
 791                 struct c4iw_dev_ucontext *uctx);
 792 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 793 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
 794                 struct c4iw_dev_ucontext *uctx);
 795 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
 796
 797 extern struct cxgb4_client t4c_client;
 798 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
 799 extern int c4iw_max_read_depth;
 800
 801 #endif