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Linux 3.4.102
[linux/fpc-iii.git] / drivers / infiniband / hw / qib / qib_iba7322.c
blobd25205309d456807385eeb8b3e05881224a22b51
1 /*
2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 /*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
36 */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/jiffies.h>
43 #include <linux/module.h>
44 #include <rdma/ib_verbs.h>
45 #include <rdma/ib_smi.h>
46
47 #include "qib.h"
48 #include "qib_7322_regs.h"
49 #include "qib_qsfp.h"
50
51 #include "qib_mad.h"
52
53 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
54 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
55 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
56 static irqreturn_t qib_7322intr(int irq, void *data);
57 static irqreturn_t qib_7322bufavail(int irq, void *data);
58 static irqreturn_t sdma_intr(int irq, void *data);
59 static irqreturn_t sdma_idle_intr(int irq, void *data);
60 static irqreturn_t sdma_progress_intr(int irq, void *data);
61 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
62 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
63 struct qib_ctxtdata *rcd);
64 static u8 qib_7322_phys_portstate(u64);
65 static u32 qib_7322_iblink_state(u64);
66 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
67 u16 linitcmd);
68 static void force_h1(struct qib_pportdata *);
69 static void adj_tx_serdes(struct qib_pportdata *);
70 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
71 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
72
73 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
74 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
75 static void serdes_7322_los_enable(struct qib_pportdata *, int);
76 static int serdes_7322_init_old(struct qib_pportdata *);
77 static int serdes_7322_init_new(struct qib_pportdata *);
78
79 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
80
81 /* LE2 serdes values for different cases */
82 #define LE2_DEFAULT 5
83 #define LE2_5m 4
84 #define LE2_QME 0
85
86 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
87 #define IBSD(hw_pidx) (hw_pidx + 2)
88
89 /* these are variables for documentation and experimentation purposes */
90 static const unsigned rcv_int_timeout = 375;
91 static const unsigned rcv_int_count = 16;
92 static const unsigned sdma_idle_cnt = 64;
93
94 /* Time to stop altering Rx Equalization parameters, after link up. */
95 #define RXEQ_DISABLE_MSECS 2500
96
97 /*
98 * Number of VLs we are configured to use (to allow for more
99 * credits per vl, etc.)
100 */
101 ushort qib_num_cfg_vls = 2;
102 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
103 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
104
105 static ushort qib_chase = 1;
106 module_param_named(chase, qib_chase, ushort, S_IRUGO);
107 MODULE_PARM_DESC(chase, "Enable state chase handling");
108
109 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
110 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
111 MODULE_PARM_DESC(long_attenuation, \
112 "attenuation cutoff (dB) for long copper cable setup");
113
114 static ushort qib_singleport;
115 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
116 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
117
118 static ushort qib_krcvq01_no_msi;
119 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
120 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
121
122 /*
123 * Receive header queue sizes
124 */
125 static unsigned qib_rcvhdrcnt;
126 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
127 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
128
129 static unsigned qib_rcvhdrsize;
130 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
131 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
132
133 static unsigned qib_rcvhdrentsize;
134 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
135 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
136
137 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
138 /* for read back, default index is ~5m copper cable */
139 static char txselect_list[MAX_ATTEN_LEN] = "10";
140 static struct kparam_string kp_txselect = {
141 .string = txselect_list,
142 .maxlen = MAX_ATTEN_LEN
143 };
144 static int setup_txselect(const char *, struct kernel_param *);
145 module_param_call(txselect, setup_txselect, param_get_string,
146 &kp_txselect, S_IWUSR | S_IRUGO);
147 MODULE_PARM_DESC(txselect, \
148 "Tx serdes indices (for no QSFP or invalid QSFP data)");
149
150 #define BOARD_QME7342 5
151 #define BOARD_QMH7342 6
152 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
153 BOARD_QMH7342)
154 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
155 BOARD_QME7342)
156
157 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
158
159 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
160
161 #define MASK_ACROSS(lsb, msb) \
162 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
163
164 #define SYM_RMASK(regname, fldname) ((u64) \
165 QIB_7322_##regname##_##fldname##_RMASK)
166
167 #define SYM_MASK(regname, fldname) ((u64) \
168 QIB_7322_##regname##_##fldname##_RMASK << \
169 QIB_7322_##regname##_##fldname##_LSB)
170
171 #define SYM_FIELD(value, regname, fldname) ((u64) \
172 (((value) >> SYM_LSB(regname, fldname)) & \
173 SYM_RMASK(regname, fldname)))
174
175 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
176 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
177 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
178
179 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
180 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
181 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
182 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
183 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
184 /* Below because most, but not all, fields of IntMask have that full suffix */
185 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
186
187
188 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
189
190 /*
191 * the size bits give us 2^N, in KB units. 0 marks as invalid,
192 * and 7 is reserved. We currently use only 2KB and 4KB
193 */
194 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
195 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
196 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
197 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
198
199 #define SendIBSLIDAssignMask \
200 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
201 #define SendIBSLMCMask \
202 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
203
204 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
205 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
206 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
207 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
208 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
209 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
210
211 #define _QIB_GPIO_SDA_NUM 1
212 #define _QIB_GPIO_SCL_NUM 0
213 #define QIB_EEPROM_WEN_NUM 14
214 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
215
216 /* HW counter clock is at 4nsec */
217 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
218
219 /* full speed IB port 1 only */
220 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
221 #define PORT_SPD_CAP_SHIFT 3
222
223 /* full speed featuremask, both ports */
224 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
225
226 /*
227 * This file contains almost all the chip-specific register information and
228 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
229 */
230
231 /* Use defines to tie machine-generated names to lower-case names */
232 #define kr_contextcnt KREG_IDX(ContextCnt)
233 #define kr_control KREG_IDX(Control)
234 #define kr_counterregbase KREG_IDX(CntrRegBase)
235 #define kr_errclear KREG_IDX(ErrClear)
236 #define kr_errmask KREG_IDX(ErrMask)
237 #define kr_errstatus KREG_IDX(ErrStatus)
238 #define kr_extctrl KREG_IDX(EXTCtrl)
239 #define kr_extstatus KREG_IDX(EXTStatus)
240 #define kr_gpio_clear KREG_IDX(GPIOClear)
241 #define kr_gpio_mask KREG_IDX(GPIOMask)
242 #define kr_gpio_out KREG_IDX(GPIOOut)
243 #define kr_gpio_status KREG_IDX(GPIOStatus)
244 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
245 #define kr_debugportval KREG_IDX(DebugPortValueReg)
246 #define kr_fmask KREG_IDX(feature_mask)
247 #define kr_act_fmask KREG_IDX(active_feature_mask)
248 #define kr_hwerrclear KREG_IDX(HwErrClear)
249 #define kr_hwerrmask KREG_IDX(HwErrMask)
250 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
251 #define kr_intclear KREG_IDX(IntClear)
252 #define kr_intmask KREG_IDX(IntMask)
253 #define kr_intredirect KREG_IDX(IntRedirect0)
254 #define kr_intstatus KREG_IDX(IntStatus)
255 #define kr_pagealign KREG_IDX(PageAlign)
256 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
257 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
258 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
259 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
260 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
261 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
262 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
263 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
264 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
265 #define kr_revision KREG_IDX(Revision)
266 #define kr_scratch KREG_IDX(Scratch)
267 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
268 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
269 #define kr_sendctrl KREG_IDX(SendCtrl)
270 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
271 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
272 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
273 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
274 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
275 #define kr_sendpiosize KREG_IDX(SendBufSize)
276 #define kr_sendregbase KREG_IDX(SendRegBase)
277 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
278 #define kr_userregbase KREG_IDX(UserRegBase)
279 #define kr_intgranted KREG_IDX(Int_Granted)
280 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
281 #define kr_intblocked KREG_IDX(IntBlocked)
282 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
283
284 /*
285 * per-port kernel registers. Access only with qib_read_kreg_port()
286 * or qib_write_kreg_port()
287 */
288 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
289 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
290 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
291 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
292 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
293 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
294 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
295 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
296 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
297 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
298 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
299 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
300 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
301 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
302 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
303 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
304 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
305 #define krp_psstart KREG_IBPORT_IDX(PSStart)
306 #define krp_psstat KREG_IBPORT_IDX(PSStat)
307 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
308 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
309 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
310 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
311 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
312 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
313 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
314 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
315 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
316 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
317 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
318 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
319 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
320 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
321 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
322 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
323 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
324 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
325 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
326 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
327 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
328 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
329 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
330 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
331 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
332 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
333 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
334 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
335 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
336 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
337 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
338
339 /*
340 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
341 * or qib_write_kreg_ctxt()
342 */
343 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
344 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
345
346 /*
347 * TID Flow table, per context. Reduces
348 * number of hdrq updates to one per flow (or on errors).
349 * context 0 and 1 share same memory, but have distinct
350 * addresses. Since for now, we never use expected sends
351 * on kernel contexts, we don't worry about that (we initialize
352 * those entries for ctxt 0/1 on driver load twice, for example).
353 */
354 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
355 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
356
357 /* these are the error bits in the tid flows, and are W1C */
358 #define TIDFLOW_ERRBITS ( \
359 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
360 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
361 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
362 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
363
364 /* Most (not all) Counters are per-IBport.
365 * Requires LBIntCnt is at offset 0 in the group
366 */
367 #define CREG_IDX(regname) \
368 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
369
370 #define crp_badformat CREG_IDX(RxVersionErrCnt)
371 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
372 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
373 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
374 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
375 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
376 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
377 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
378 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
379 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
380 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
381 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
382 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
383 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
384 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
385 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
386 #define crp_pktsend CREG_IDX(TxDataPktCnt)
387 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
388 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
389 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
390 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
391 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
392 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
393 #define crp_rcvebp CREG_IDX(RxEBPCnt)
394 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
395 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
396 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
397 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
398 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
399 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
400 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
401 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
402 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
403 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
404 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
405 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
406 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
407 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
408 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
409 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
410 #define crp_wordrcv CREG_IDX(RxDwordCnt)
411 #define crp_wordsend CREG_IDX(TxDwordCnt)
412 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
413
414 /* these are the (few) counters that are not port-specific */
415 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
416 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
417 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
418 #define cr_lbint CREG_DEVIDX(LBIntCnt)
419 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
420 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
421 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
422 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
423 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
424
425 /* no chip register for # of IB ports supported, so define */
426 #define NUM_IB_PORTS 2
427
428 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
429 #define NUM_VL15_BUFS NUM_IB_PORTS
430
431 /*
432 * context 0 and 1 are special, and there is no chip register that
433 * defines this value, so we have to define it here.
434 * These are all allocated to either 0 or 1 for single port
435 * hardware configuration, otherwise each gets half
436 */
437 #define KCTXT0_EGRCNT 2048
438
439 /* values for vl and port fields in PBC, 7322-specific */
440 #define PBC_PORT_SEL_LSB 26
441 #define PBC_PORT_SEL_RMASK 1
442 #define PBC_VL_NUM_LSB 27
443 #define PBC_VL_NUM_RMASK 7
444 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
445 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
446
447 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
448 [IB_RATE_2_5_GBPS] = 16,
449 [IB_RATE_5_GBPS] = 8,
450 [IB_RATE_10_GBPS] = 4,
451 [IB_RATE_20_GBPS] = 2,
452 [IB_RATE_30_GBPS] = 2,
453 [IB_RATE_40_GBPS] = 1
454 };
455
456 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
457 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
458
459 /* link training states, from IBC */
460 #define IB_7322_LT_STATE_DISABLED 0x00
461 #define IB_7322_LT_STATE_LINKUP 0x01
462 #define IB_7322_LT_STATE_POLLACTIVE 0x02
463 #define IB_7322_LT_STATE_POLLQUIET 0x03
464 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
465 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
466 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
467 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
468 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
469 #define IB_7322_LT_STATE_CFGIDLE 0x0b
470 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
471 #define IB_7322_LT_STATE_TXREVLANES 0x0d
472 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
473 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
474 #define IB_7322_LT_STATE_CFGENH 0x10
475 #define IB_7322_LT_STATE_CFGTEST 0x11
476 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
477 #define IB_7322_LT_STATE_CFGWAITENH 0x13
478
479 /* link state machine states from IBC */
480 #define IB_7322_L_STATE_DOWN 0x0
481 #define IB_7322_L_STATE_INIT 0x1
482 #define IB_7322_L_STATE_ARM 0x2
483 #define IB_7322_L_STATE_ACTIVE 0x3
484 #define IB_7322_L_STATE_ACT_DEFER 0x4
485
486 static const u8 qib_7322_physportstate[0x20] = {
487 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
488 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
489 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
490 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
491 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
492 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
493 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
494 [IB_7322_LT_STATE_CFGRCVFCFG] =
495 IB_PHYSPORTSTATE_CFG_TRAIN,
496 [IB_7322_LT_STATE_CFGWAITRMT] =
497 IB_PHYSPORTSTATE_CFG_TRAIN,
498 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
499 [IB_7322_LT_STATE_RECOVERRETRAIN] =
500 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
501 [IB_7322_LT_STATE_RECOVERWAITRMT] =
502 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
503 [IB_7322_LT_STATE_RECOVERIDLE] =
504 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
505 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
506 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
507 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
508 IB_PHYSPORTSTATE_CFG_TRAIN,
509 [IB_7322_LT_STATE_CFGWAITENH] =
510 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
511 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
512 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
513 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
514 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
515 };
516
517 struct qib_chip_specific {
518 u64 __iomem *cregbase;
519 u64 *cntrs;
520 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
521 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
522 u64 main_int_mask; /* clear bits which have dedicated handlers */
523 u64 int_enable_mask; /* for per port interrupts in single port mode */
524 u64 errormask;
525 u64 hwerrmask;
526 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
527 u64 gpio_mask; /* shadow the gpio mask register */
528 u64 extctrl; /* shadow the gpio output enable, etc... */
529 u32 ncntrs;
530 u32 nportcntrs;
531 u32 cntrnamelen;
532 u32 portcntrnamelen;
533 u32 numctxts;
534 u32 rcvegrcnt;
535 u32 updthresh; /* current AvailUpdThld */
536 u32 updthresh_dflt; /* default AvailUpdThld */
537 u32 r1;
538 int irq;
539 u32 num_msix_entries;
540 u32 sdmabufcnt;
541 u32 lastbuf_for_pio;
542 u32 stay_in_freeze;
543 u32 recovery_ports_initted;
544 struct qib_msix_entry *msix_entries;
545 unsigned long *sendchkenable;
546 unsigned long *sendgrhchk;
547 unsigned long *sendibchk;
548 u32 rcvavail_timeout[18];
549 char emsgbuf[128]; /* for device error interrupt msg buffer */
550 };
551
552 /* Table of entries in "human readable" form Tx Emphasis. */
553 struct txdds_ent {
554 u8 amp;
555 u8 pre;
556 u8 main;
557 u8 post;
558 };
559
560 struct vendor_txdds_ent {
561 u8 oui[QSFP_VOUI_LEN];
562 u8 *partnum;
563 struct txdds_ent sdr;
564 struct txdds_ent ddr;
565 struct txdds_ent qdr;
566 };
567
568 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
569
570 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
571 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
572 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
573 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
574
575 #define H1_FORCE_VAL 8
576 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
577 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
578
579 /* The static and dynamic registers are paired, and the pairs indexed by spd */
580 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
581 + ((spd) * 2))
582
583 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
584 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
585 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
586 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
587 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
588
589 struct qib_chippport_specific {
590 u64 __iomem *kpregbase;
591 u64 __iomem *cpregbase;
592 u64 *portcntrs;
593 struct qib_pportdata *ppd;
594 wait_queue_head_t autoneg_wait;
595 struct delayed_work autoneg_work;
596 struct delayed_work ipg_work;
597 struct timer_list chase_timer;
598 /*
599 * these 5 fields are used to establish deltas for IB symbol
600 * errors and linkrecovery errors. They can be reported on
601 * some chips during link negotiation prior to INIT, and with
602 * DDR when faking DDR negotiations with non-IBTA switches.
603 * The chip counters are adjusted at driver unload if there is
604 * a non-zero delta.
605 */
606 u64 ibdeltainprog;
607 u64 ibsymdelta;
608 u64 ibsymsnap;
609 u64 iblnkerrdelta;
610 u64 iblnkerrsnap;
611 u64 iblnkdownsnap;
612 u64 iblnkdowndelta;
613 u64 ibmalfdelta;
614 u64 ibmalfsnap;
615 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
616 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
617 unsigned long qdr_dfe_time;
618 unsigned long chase_end;
619 u32 autoneg_tries;
620 u32 recovery_init;
621 u32 qdr_dfe_on;
622 u32 qdr_reforce;
623 /*
624 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
625 * entry zero is unused, to simplify indexing
626 */
627 u8 h1_val;
628 u8 no_eep; /* txselect table index to use if no qsfp info */
629 u8 ipg_tries;
630 u8 ibmalfusesnap;
631 struct qib_qsfp_data qsfp_data;
632 char epmsgbuf[192]; /* for port error interrupt msg buffer */
633 };
634
635 static struct {
636 const char *name;
637 irq_handler_t handler;
638 int lsb;
639 int port; /* 0 if not port-specific, else port # */
640 } irq_table[] = {
641 { "", qib_7322intr, -1, 0 },
642 { " (buf avail)", qib_7322bufavail,
643 SYM_LSB(IntStatus, SendBufAvail), 0 },
644 { " (sdma 0)", sdma_intr,
645 SYM_LSB(IntStatus, SDmaInt_0), 1 },
646 { " (sdma 1)", sdma_intr,
647 SYM_LSB(IntStatus, SDmaInt_1), 2 },
648 { " (sdmaI 0)", sdma_idle_intr,
649 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
650 { " (sdmaI 1)", sdma_idle_intr,
651 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
652 { " (sdmaP 0)", sdma_progress_intr,
653 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
654 { " (sdmaP 1)", sdma_progress_intr,
655 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
656 { " (sdmaC 0)", sdma_cleanup_intr,
657 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
658 { " (sdmaC 1)", sdma_cleanup_intr,
659 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
660 };
661
662 /* ibcctrl bits */
663 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
664 /* cycle through TS1/TS2 till OK */
665 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
666 /* wait for TS1, then go on */
667 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
668 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
669
670 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
671 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
672 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
673
674 #define BLOB_7322_IBCHG 0x101
675
676 static inline void qib_write_kreg(const struct qib_devdata *dd,
677 const u32 regno, u64 value);
678 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
679 static void write_7322_initregs(struct qib_devdata *);
680 static void write_7322_init_portregs(struct qib_pportdata *);
681 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
682 static void check_7322_rxe_status(struct qib_pportdata *);
683 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
684
685 /**
686 * qib_read_ureg32 - read 32-bit virtualized per-context register
687 * @dd: device
688 * @regno: register number
689 * @ctxt: context number
690 *
691 * Return the contents of a register that is virtualized to be per context.
692 * Returns -1 on errors (not distinguishable from valid contents at
693 * runtime; we may add a separate error variable at some point).
694 */
695 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
696 enum qib_ureg regno, int ctxt)
697 {
698 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
699 return 0;
700 return readl(regno + (u64 __iomem *)(
701 (dd->ureg_align * ctxt) + (dd->userbase ?
702 (char __iomem *)dd->userbase :
703 (char __iomem *)dd->kregbase + dd->uregbase)));
704 }
705
706 /**
707 * qib_read_ureg - read virtualized per-context register
708 * @dd: device
709 * @regno: register number
710 * @ctxt: context number
711 *
712 * Return the contents of a register that is virtualized to be per context.
713 * Returns -1 on errors (not distinguishable from valid contents at
714 * runtime; we may add a separate error variable at some point).
715 */
716 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
717 enum qib_ureg regno, int ctxt)
718 {
719
720 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
721 return 0;
722 return readq(regno + (u64 __iomem *)(
723 (dd->ureg_align * ctxt) + (dd->userbase ?
724 (char __iomem *)dd->userbase :
725 (char __iomem *)dd->kregbase + dd->uregbase)));
726 }
727
728 /**
729 * qib_write_ureg - write virtualized per-context register
730 * @dd: device
731 * @regno: register number
732 * @value: value
733 * @ctxt: context
734 *
735 * Write the contents of a register that is virtualized to be per context.
736 */
737 static inline void qib_write_ureg(const struct qib_devdata *dd,
738 enum qib_ureg regno, u64 value, int ctxt)
739 {
740 u64 __iomem *ubase;
741 if (dd->userbase)
742 ubase = (u64 __iomem *)
743 ((char __iomem *) dd->userbase +
744 dd->ureg_align * ctxt);
745 else
746 ubase = (u64 __iomem *)
747 (dd->uregbase +
748 (char __iomem *) dd->kregbase +
749 dd->ureg_align * ctxt);
750
751 if (dd->kregbase && (dd->flags & QIB_PRESENT))
752 writeq(value, &ubase[regno]);
753 }
754
755 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
756 const u32 regno)
757 {
758 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
759 return -1;
760 return readl((u32 __iomem *) &dd->kregbase[regno]);
761 }
762
763 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
764 const u32 regno)
765 {
766 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
767 return -1;
768 return readq(&dd->kregbase[regno]);
769 }
770
771 static inline void qib_write_kreg(const struct qib_devdata *dd,
772 const u32 regno, u64 value)
773 {
774 if (dd->kregbase && (dd->flags & QIB_PRESENT))
775 writeq(value, &dd->kregbase[regno]);
776 }
777
778 /*
779 * not many sanity checks for the port-specific kernel register routines,
780 * since they are only used when it's known to be safe.
781 */
782 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
783 const u16 regno)
784 {
785 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
786 return 0ULL;
787 return readq(&ppd->cpspec->kpregbase[regno]);
788 }
789
790 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
791 const u16 regno, u64 value)
792 {
793 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
794 (ppd->dd->flags & QIB_PRESENT))
795 writeq(value, &ppd->cpspec->kpregbase[regno]);
796 }
797
798 /**
799 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
800 * @dd: the qlogic_ib device
801 * @regno: the register number to write
802 * @ctxt: the context containing the register
803 * @value: the value to write
804 */
805 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
806 const u16 regno, unsigned ctxt,
807 u64 value)
808 {
809 qib_write_kreg(dd, regno + ctxt, value);
810 }
811
812 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
813 {
814 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
815 return 0;
816 return readq(&dd->cspec->cregbase[regno]);
817
818
819 }
820
821 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
822 {
823 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
824 return 0;
825 return readl(&dd->cspec->cregbase[regno]);
826
827
828 }
829
830 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
831 u16 regno, u64 value)
832 {
833 if (ppd->cpspec && ppd->cpspec->cpregbase &&
834 (ppd->dd->flags & QIB_PRESENT))
835 writeq(value, &ppd->cpspec->cpregbase[regno]);
836 }
837
838 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
839 u16 regno)
840 {
841 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
842 !(ppd->dd->flags & QIB_PRESENT))
843 return 0;
844 return readq(&ppd->cpspec->cpregbase[regno]);
845 }
846
847 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
848 u16 regno)
849 {
850 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
851 !(ppd->dd->flags & QIB_PRESENT))
852 return 0;
853 return readl(&ppd->cpspec->cpregbase[regno]);
854 }
855
856 /* bits in Control register */
857 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
858 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
859
860 /* bits in general interrupt regs */
861 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
862 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
863 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
864 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
865 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
866 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
867 #define QIB_I_C_ERROR INT_MASK(Err)
868
869 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
870 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
871 #define QIB_I_GPIO INT_MASK(AssertGPIO)
872 #define QIB_I_P_SDMAINT(pidx) \
873 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
874 INT_MASK_P(SDmaProgress, pidx) | \
875 INT_MASK_PM(SDmaCleanupDone, pidx))
876
877 /* Interrupt bits that are "per port" */
878 #define QIB_I_P_BITSEXTANT(pidx) \
879 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
880 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
881 INT_MASK_P(SDmaProgress, pidx) | \
882 INT_MASK_PM(SDmaCleanupDone, pidx))
883
884 /* Interrupt bits that are common to a device */
885 /* currently unused: QIB_I_SPIOSENT */
886 #define QIB_I_C_BITSEXTANT \
887 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
888 QIB_I_SPIOSENT | \
889 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
890
891 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
892 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
893
894 /*
895 * Error bits that are "per port".
896 */
897 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
898 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
899 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
900 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
901 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
902 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
903 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
904 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
905 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
906 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
907 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
908 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
909 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
910 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
911 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
912 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
913 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
914 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
915 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
916 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
917 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
918 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
919 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
920 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
921 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
922 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
923 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
924 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
925
926 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
927 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
928 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
929 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
930 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
931 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
932 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
933 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
934 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
935 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
936 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
937
938 /* Error bits that are common to a device */
939 #define QIB_E_RESET ERR_MASK(ResetNegated)
940 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
941 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
942
943
944 /*
945 * Per chip (rather than per-port) errors. Most either do
946 * nothing but trigger a print (because they self-recover, or
947 * always occur in tandem with other errors that handle the
948 * issue), or because they indicate errors with no recovery,
949 * but we want to know that they happened.
950 */
951 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
952 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
953 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
954 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
955 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
956 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
957 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
958 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
959
960 /* SDMA chip errors (not per port)
961 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
962 * the SDMAHALT error immediately, so we just print the dup error via the
963 * E_AUTO mechanism. This is true of most of the per-port fatal errors
964 * as well, but since this is port-independent, by definition, it's
965 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
966 * packet send errors, and so are handled in the same manner as other
967 * per-packet errors.
968 */
969 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
970 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
971 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
972
973 /*
974 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
975 * it is used to print "common" packet errors.
976 */
977 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
978 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
979 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
980 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
981 QIB_E_P_REBP)
982
983 /* Error Bits that Packet-related (Receive, per-port) */
984 #define QIB_E_P_RPKTERRS (\
985 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
986 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
987 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
988 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
989 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
990 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
991
992 /*
993 * Error bits that are Send-related (per port)
994 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
995 * All of these potentially need to have a buffer disarmed
996 */
997 #define QIB_E_P_SPKTERRS (\
998 QIB_E_P_SUNEXP_PKTNUM |\
999 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1000 QIB_E_P_SMAXPKTLEN |\
1001 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1002 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1003 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1004
1005 #define QIB_E_SPKTERRS ( \
1006 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1007 ERR_MASK_N(SendUnsupportedVLErr) | \
1008 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1009
1010 #define QIB_E_P_SDMAERRS ( \
1011 QIB_E_P_SDMAHALT | \
1012 QIB_E_P_SDMADESCADDRMISALIGN | \
1013 QIB_E_P_SDMAUNEXPDATA | \
1014 QIB_E_P_SDMAMISSINGDW | \
1015 QIB_E_P_SDMADWEN | \
1016 QIB_E_P_SDMARPYTAG | \
1017 QIB_E_P_SDMA1STDESC | \
1018 QIB_E_P_SDMABASE | \
1019 QIB_E_P_SDMATAILOUTOFBOUND | \
1020 QIB_E_P_SDMAOUTOFBOUND | \
1021 QIB_E_P_SDMAGENMISMATCH)
1022
1023 /*
1024 * This sets some bits more than once, but makes it more obvious which
1025 * bits are not handled under other categories, and the repeat definition
1026 * is not a problem.
1027 */
1028 #define QIB_E_P_BITSEXTANT ( \
1029 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1030 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1031 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1032 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1033 )
1034
1035 /*
1036 * These are errors that can occur when the link
1037 * changes state while a packet is being sent or received. This doesn't
1038 * cover things like EBP or VCRC that can be the result of a sending
1039 * having the link change state, so we receive a "known bad" packet.
1040 * All of these are "per port", so renamed:
1041 */
1042 #define QIB_E_P_LINK_PKTERRS (\
1043 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1044 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1045 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1046 QIB_E_P_RUNEXPCHAR)
1047
1048 /*
1049 * This sets some bits more than once, but makes it more obvious which
1050 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1051 * and the repeat definition is not a problem.
1052 */
1053 #define QIB_E_C_BITSEXTANT (\
1054 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1055 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1056 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1057
1058 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1059 #define E_SPKT_ERRS_IGNORE 0
1060
1061 #define QIB_EXTS_MEMBIST_DISABLED \
1062 SYM_MASK(EXTStatus, MemBISTDisabled)
1063 #define QIB_EXTS_MEMBIST_ENDTEST \
1064 SYM_MASK(EXTStatus, MemBISTEndTest)
1065
1066 #define QIB_E_SPIOARMLAUNCH \
1067 ERR_MASK(SendArmLaunchErr)
1068
1069 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1070 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1071
1072 /*
1073 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1074 * and also if forced QDR (only QDR enabled). It's enabled for the
1075 * forced QDR case so that scrambling will be enabled by the TS3
1076 * exchange, when supported by both sides of the link.
1077 */
1078 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1079 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1080 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1081 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1082 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1083 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1084 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1085 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1086
1087 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1088 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1089
1090 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1091 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1092 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1093
1094 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1095 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1096 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1097 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1098 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1099 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1100 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1101
1102 #define IBA7322_REDIRECT_VEC_PER_REG 12
1103
1104 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1105 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1106 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1107 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1108 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1109
1110 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1111
1112 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1113 .msg = #fldname , .sz = sizeof(#fldname) }
1114 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1115 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
1116 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1117 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1118 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1119 HWE_AUTO(PCIESerdesPClkNotDetect),
1120 HWE_AUTO(PowerOnBISTFailed),
1121 HWE_AUTO(TempsenseTholdReached),
1122 HWE_AUTO(MemoryErr),
1123 HWE_AUTO(PCIeBusParityErr),
1124 HWE_AUTO(PcieCplTimeout),
1125 HWE_AUTO(PciePoisonedTLP),
1126 HWE_AUTO_P(SDmaMemReadErr, 1),
1127 HWE_AUTO_P(SDmaMemReadErr, 0),
1128 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1129 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1130 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1131 HWE_AUTO(statusValidNoEop),
1132 HWE_AUTO(LATriggered),
1133 { .mask = 0, .sz = 0 }
1134 };
1135
1136 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1137 .msg = #fldname, .sz = sizeof(#fldname) }
1138 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1139 .msg = #fldname, .sz = sizeof(#fldname) }
1140 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1141 E_AUTO(RcvEgrFullErr),
1142 E_AUTO(RcvHdrFullErr),
1143 E_AUTO(ResetNegated),
1144 E_AUTO(HardwareErr),
1145 E_AUTO(InvalidAddrErr),
1146 E_AUTO(SDmaVL15Err),
1147 E_AUTO(SBufVL15MisUseErr),
1148 E_AUTO(InvalidEEPCmd),
1149 E_AUTO(RcvContextShareErr),
1150 E_AUTO(SendVLMismatchErr),
1151 E_AUTO(SendArmLaunchErr),
1152 E_AUTO(SendSpecialTriggerErr),
1153 E_AUTO(SDmaWrongPortErr),
1154 E_AUTO(SDmaBufMaskDuplicateErr),
1155 { .mask = 0, .sz = 0 }
1156 };
1157
1158 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1159 E_P_AUTO(IBStatusChanged),
1160 E_P_AUTO(SHeadersErr),
1161 E_P_AUTO(VL15BufMisuseErr),
1162 /*
1163 * SDmaHaltErr is not really an error, make it clearer;
1164 */
1165 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1166 .sz = 11},
1167 E_P_AUTO(SDmaDescAddrMisalignErr),
1168 E_P_AUTO(SDmaUnexpDataErr),
1169 E_P_AUTO(SDmaMissingDwErr),
1170 E_P_AUTO(SDmaDwEnErr),
1171 E_P_AUTO(SDmaRpyTagErr),
1172 E_P_AUTO(SDma1stDescErr),
1173 E_P_AUTO(SDmaBaseErr),
1174 E_P_AUTO(SDmaTailOutOfBoundErr),
1175 E_P_AUTO(SDmaOutOfBoundErr),
1176 E_P_AUTO(SDmaGenMismatchErr),
1177 E_P_AUTO(SendBufMisuseErr),
1178 E_P_AUTO(SendUnsupportedVLErr),
1179 E_P_AUTO(SendUnexpectedPktNumErr),
1180 E_P_AUTO(SendDroppedDataPktErr),
1181 E_P_AUTO(SendDroppedSmpPktErr),
1182 E_P_AUTO(SendPktLenErr),
1183 E_P_AUTO(SendUnderRunErr),
1184 E_P_AUTO(SendMaxPktLenErr),
1185 E_P_AUTO(SendMinPktLenErr),
1186 E_P_AUTO(RcvIBLostLinkErr),
1187 E_P_AUTO(RcvHdrErr),
1188 E_P_AUTO(RcvHdrLenErr),
1189 E_P_AUTO(RcvBadTidErr),
1190 E_P_AUTO(RcvBadVersionErr),
1191 E_P_AUTO(RcvIBFlowErr),
1192 E_P_AUTO(RcvEBPErr),
1193 E_P_AUTO(RcvUnsupportedVLErr),
1194 E_P_AUTO(RcvUnexpectedCharErr),
1195 E_P_AUTO(RcvShortPktLenErr),
1196 E_P_AUTO(RcvLongPktLenErr),
1197 E_P_AUTO(RcvMaxPktLenErr),
1198 E_P_AUTO(RcvMinPktLenErr),
1199 E_P_AUTO(RcvICRCErr),
1200 E_P_AUTO(RcvVCRCErr),
1201 E_P_AUTO(RcvFormatErr),
1202 { .mask = 0, .sz = 0 }
1203 };
1204
1205 /*
1206 * Below generates "auto-message" for interrupts not specific to any port or
1207 * context
1208 */
1209 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1210 .msg = #fldname, .sz = sizeof(#fldname) }
1211 /* Below generates "auto-message" for interrupts specific to a port */
1212 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1213 SYM_LSB(IntMask, fldname##Mask##_0), \
1214 SYM_LSB(IntMask, fldname##Mask##_1)), \
1215 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1216 /* For some reason, the SerDesTrimDone bits are reversed */
1217 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1218 SYM_LSB(IntMask, fldname##Mask##_1), \
1219 SYM_LSB(IntMask, fldname##Mask##_0)), \
1220 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1221 /*
1222 * Below generates "auto-message" for interrupts specific to a context,
1223 * with ctxt-number appended
1224 */
1225 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1226 SYM_LSB(IntMask, fldname##0IntMask), \
1227 SYM_LSB(IntMask, fldname##17IntMask)), \
1228 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
1229
1230 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1231 INTR_AUTO_P(SDmaInt),
1232 INTR_AUTO_P(SDmaProgressInt),
1233 INTR_AUTO_P(SDmaIdleInt),
1234 INTR_AUTO_P(SDmaCleanupDone),
1235 INTR_AUTO_C(RcvUrg),
1236 INTR_AUTO_P(ErrInt),
1237 INTR_AUTO(ErrInt), /* non-port-specific errs */
1238 INTR_AUTO(AssertGPIOInt),
1239 INTR_AUTO_P(SendDoneInt),
1240 INTR_AUTO(SendBufAvailInt),
1241 INTR_AUTO_C(RcvAvail),
1242 { .mask = 0, .sz = 0 }
1243 };
1244
1245 #define TXSYMPTOM_AUTO_P(fldname) \
1246 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1247 .msg = #fldname, .sz = sizeof(#fldname) }
1248 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1249 TXSYMPTOM_AUTO_P(NonKeyPacket),
1250 TXSYMPTOM_AUTO_P(GRHFail),
1251 TXSYMPTOM_AUTO_P(PkeyFail),
1252 TXSYMPTOM_AUTO_P(QPFail),
1253 TXSYMPTOM_AUTO_P(SLIDFail),
1254 TXSYMPTOM_AUTO_P(RawIPV6),
1255 TXSYMPTOM_AUTO_P(PacketTooSmall),
1256 { .mask = 0, .sz = 0 }
1257 };
1258
1259 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1260
1261 /*
1262 * Called when we might have an error that is specific to a particular
1263 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1264 * because we don't need to force the update of pioavail
1265 */
1266 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1267 {
1268 struct qib_devdata *dd = ppd->dd;
1269 u32 i;
1270 int any;
1271 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1272 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1273 unsigned long sbuf[4];
1274
1275 /*
1276 * It's possible that sendbuffererror could have bits set; might
1277 * have already done this as a result of hardware error handling.
1278 */
1279 any = 0;
1280 for (i = 0; i < regcnt; ++i) {
1281 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1282 if (sbuf[i]) {
1283 any = 1;
1284 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1285 }
1286 }
1287
1288 if (any)
1289 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1290 }
1291
1292 /* No txe_recover yet, if ever */
1293
1294 /* No decode__errors yet */
1295 static void err_decode(char *msg, size_t len, u64 errs,
1296 const struct qib_hwerror_msgs *msp)
1297 {
1298 u64 these, lmask;
1299 int took, multi, n = 0;
1300
1301 while (errs && msp && msp->mask) {
1302 multi = (msp->mask & (msp->mask - 1));
1303 while (errs & msp->mask) {
1304 these = (errs & msp->mask);
1305 lmask = (these & (these - 1)) ^ these;
1306 if (len) {
1307 if (n++) {
1308 /* separate the strings */
1309 *msg++ = ',';
1310 len--;
1311 }
1312 BUG_ON(!msp->sz);
1313 /* msp->sz counts the nul */
1314 took = min_t(size_t, msp->sz - (size_t)1, len);
1315 memcpy(msg, msp->msg, took);
1316 len -= took;
1317 msg += took;
1318 if (len)
1319 *msg = '\0';
1320 }
1321 errs &= ~lmask;
1322 if (len && multi) {
1323 /* More than one bit this mask */
1324 int idx = -1;
1325
1326 while (lmask & msp->mask) {
1327 ++idx;
1328 lmask >>= 1;
1329 }
1330 took = scnprintf(msg, len, "_%d", idx);
1331 len -= took;
1332 msg += took;
1333 }
1334 }
1335 ++msp;
1336 }
1337 /* If some bits are left, show in hex. */
1338 if (len && errs)
1339 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1340 (unsigned long long) errs);
1341 }
1342
1343 /* only called if r1 set */
1344 static void flush_fifo(struct qib_pportdata *ppd)
1345 {
1346 struct qib_devdata *dd = ppd->dd;
1347 u32 __iomem *piobuf;
1348 u32 bufn;
1349 u32 *hdr;
1350 u64 pbc;
1351 const unsigned hdrwords = 7;
1352 static struct qib_ib_header ibhdr = {
1353 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1354 .lrh[1] = IB_LID_PERMISSIVE,
1355 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1356 .lrh[3] = IB_LID_PERMISSIVE,
1357 .u.oth.bth[0] = cpu_to_be32(
1358 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1359 .u.oth.bth[1] = cpu_to_be32(0),
1360 .u.oth.bth[2] = cpu_to_be32(0),
1361 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1362 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1363 };
1364
1365 /*
1366 * Send a dummy VL15 packet to flush the launch FIFO.
1367 * This will not actually be sent since the TxeBypassIbc bit is set.
1368 */
1369 pbc = PBC_7322_VL15_SEND |
1370 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1371 (hdrwords + SIZE_OF_CRC);
1372 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1373 if (!piobuf)
1374 return;
1375 writeq(pbc, piobuf);
1376 hdr = (u32 *) &ibhdr;
1377 if (dd->flags & QIB_PIO_FLUSH_WC) {
1378 qib_flush_wc();
1379 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1380 qib_flush_wc();
1381 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1382 qib_flush_wc();
1383 } else
1384 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1385 qib_sendbuf_done(dd, bufn);
1386 }
1387
1388 /*
1389 * This is called with interrupts disabled and sdma_lock held.
1390 */
1391 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1392 {
1393 struct qib_devdata *dd = ppd->dd;
1394 u64 set_sendctrl = 0;
1395 u64 clr_sendctrl = 0;
1396
1397 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1398 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1399 else
1400 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1401
1402 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1403 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1404 else
1405 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1406
1407 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1408 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1409 else
1410 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1411
1412 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1413 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1414 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1415 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1416 else
1417 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1418 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1419 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1420
1421 spin_lock(&dd->sendctrl_lock);
1422
1423 /* If we are draining everything, block sends first */
1424 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1425 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1426 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1427 qib_write_kreg(dd, kr_scratch, 0);
1428 }
1429
1430 ppd->p_sendctrl |= set_sendctrl;
1431 ppd->p_sendctrl &= ~clr_sendctrl;
1432
1433 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1434 qib_write_kreg_port(ppd, krp_sendctrl,
1435 ppd->p_sendctrl |
1436 SYM_MASK(SendCtrl_0, SDmaCleanup));
1437 else
1438 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1439 qib_write_kreg(dd, kr_scratch, 0);
1440
1441 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1442 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1443 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1444 qib_write_kreg(dd, kr_scratch, 0);
1445 }
1446
1447 spin_unlock(&dd->sendctrl_lock);
1448
1449 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1450 flush_fifo(ppd);
1451 }
1452
1453 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1454 {
1455 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1456 }
1457
1458 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1459 {
1460 /*
1461 * Set SendDmaLenGen and clear and set
1462 * the MSB of the generation count to enable generation checking
1463 * and load the internal generation counter.
1464 */
1465 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1466 qib_write_kreg_port(ppd, krp_senddmalengen,
1467 ppd->sdma_descq_cnt |
1468 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1469 }
1470
1471 /*
1472 * Must be called with sdma_lock held, or before init finished.
1473 */
1474 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1475 {
1476 /* Commit writes to memory and advance the tail on the chip */
1477 wmb();
1478 ppd->sdma_descq_tail = tail;
1479 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1480 }
1481
1482 /*
1483 * This is called with interrupts disabled and sdma_lock held.
1484 */
1485 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1486 {
1487 /*
1488 * Drain all FIFOs.
1489 * The hardware doesn't require this but we do it so that verbs
1490 * and user applications don't wait for link active to send stale
1491 * data.
1492 */
1493 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1494
1495 qib_sdma_7322_setlengen(ppd);
1496 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1497 ppd->sdma_head_dma[0] = 0;
1498 qib_7322_sdma_sendctrl(ppd,
1499 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1500 }
1501
1502 #define DISABLES_SDMA ( \
1503 QIB_E_P_SDMAHALT | \
1504 QIB_E_P_SDMADESCADDRMISALIGN | \
1505 QIB_E_P_SDMAMISSINGDW | \
1506 QIB_E_P_SDMADWEN | \
1507 QIB_E_P_SDMARPYTAG | \
1508 QIB_E_P_SDMA1STDESC | \
1509 QIB_E_P_SDMABASE | \
1510 QIB_E_P_SDMATAILOUTOFBOUND | \
1511 QIB_E_P_SDMAOUTOFBOUND | \
1512 QIB_E_P_SDMAGENMISMATCH)
1513
1514 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1515 {
1516 unsigned long flags;
1517 struct qib_devdata *dd = ppd->dd;
1518
1519 errs &= QIB_E_P_SDMAERRS;
1520
1521 if (errs & QIB_E_P_SDMAUNEXPDATA)
1522 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1523 ppd->port);
1524
1525 spin_lock_irqsave(&ppd->sdma_lock, flags);
1526
1527 switch (ppd->sdma_state.current_state) {
1528 case qib_sdma_state_s00_hw_down:
1529 break;
1530
1531 case qib_sdma_state_s10_hw_start_up_wait:
1532 if (errs & QIB_E_P_SDMAHALT)
1533 __qib_sdma_process_event(ppd,
1534 qib_sdma_event_e20_hw_started);
1535 break;
1536
1537 case qib_sdma_state_s20_idle:
1538 break;
1539
1540 case qib_sdma_state_s30_sw_clean_up_wait:
1541 break;
1542
1543 case qib_sdma_state_s40_hw_clean_up_wait:
1544 if (errs & QIB_E_P_SDMAHALT)
1545 __qib_sdma_process_event(ppd,
1546 qib_sdma_event_e50_hw_cleaned);
1547 break;
1548
1549 case qib_sdma_state_s50_hw_halt_wait:
1550 if (errs & QIB_E_P_SDMAHALT)
1551 __qib_sdma_process_event(ppd,
1552 qib_sdma_event_e60_hw_halted);
1553 break;
1554
1555 case qib_sdma_state_s99_running:
1556 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1557 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1558 break;
1559 }
1560
1561 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1562 }
1563
1564 /*
1565 * handle per-device errors (not per-port errors)
1566 */
1567 static noinline void handle_7322_errors(struct qib_devdata *dd)
1568 {
1569 char *msg;
1570 u64 iserr = 0;
1571 u64 errs;
1572 u64 mask;
1573 int log_idx;
1574
1575 qib_stats.sps_errints++;
1576 errs = qib_read_kreg64(dd, kr_errstatus);
1577 if (!errs) {
1578 qib_devinfo(dd->pcidev, "device error interrupt, "
1579 "but no error bits set!\n");
1580 goto done;
1581 }
1582
1583 /* don't report errors that are masked */
1584 errs &= dd->cspec->errormask;
1585 msg = dd->cspec->emsgbuf;
1586
1587 /* do these first, they are most important */
1588 if (errs & QIB_E_HARDWARE) {
1589 *msg = '\0';
1590 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1591 } else
1592 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1593 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1594 qib_inc_eeprom_err(dd, log_idx, 1);
1595
1596 if (errs & QIB_E_SPKTERRS) {
1597 qib_disarm_7322_senderrbufs(dd->pport);
1598 qib_stats.sps_txerrs++;
1599 } else if (errs & QIB_E_INVALIDADDR)
1600 qib_stats.sps_txerrs++;
1601 else if (errs & QIB_E_ARMLAUNCH) {
1602 qib_stats.sps_txerrs++;
1603 qib_disarm_7322_senderrbufs(dd->pport);
1604 }
1605 qib_write_kreg(dd, kr_errclear, errs);
1606
1607 /*
1608 * The ones we mask off are handled specially below
1609 * or above. Also mask SDMADISABLED by default as it
1610 * is too chatty.
1611 */
1612 mask = QIB_E_HARDWARE;
1613 *msg = '\0';
1614
1615 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1616 qib_7322error_msgs);
1617
1618 /*
1619 * Getting reset is a tragedy for all ports. Mark the device
1620 * _and_ the ports as "offline" in way meaningful to each.
1621 */
1622 if (errs & QIB_E_RESET) {
1623 int pidx;
1624
1625 qib_dev_err(dd, "Got reset, requires re-init "
1626 "(unload and reload driver)\n");
1627 dd->flags &= ~QIB_INITTED; /* needs re-init */
1628 /* mark as having had error */
1629 *dd->devstatusp |= QIB_STATUS_HWERROR;
1630 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1631 if (dd->pport[pidx].link_speed_supported)
1632 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1633 }
1634
1635 if (*msg && iserr)
1636 qib_dev_err(dd, "%s error\n", msg);
1637
1638 /*
1639 * If there were hdrq or egrfull errors, wake up any processes
1640 * waiting in poll. We used to try to check which contexts had
1641 * the overflow, but given the cost of that and the chip reads
1642 * to support it, it's better to just wake everybody up if we
1643 * get an overflow; waiters can poll again if it's not them.
1644 */
1645 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1646 qib_handle_urcv(dd, ~0U);
1647 if (errs & ERR_MASK(RcvEgrFullErr))
1648 qib_stats.sps_buffull++;
1649 else
1650 qib_stats.sps_hdrfull++;
1651 }
1652
1653 done:
1654 return;
1655 }
1656
1657 static void qib_error_tasklet(unsigned long data)
1658 {
1659 struct qib_devdata *dd = (struct qib_devdata *)data;
1660
1661 handle_7322_errors(dd);
1662 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1663 }
1664
1665 static void reenable_chase(unsigned long opaque)
1666 {
1667 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1668
1669 ppd->cpspec->chase_timer.expires = 0;
1670 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1671 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1672 }
1673
1674 static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow,
1675 u8 ibclt)
1676 {
1677 ppd->cpspec->chase_end = 0;
1678
1679 if (!qib_chase)
1680 return;
1681
1682 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1683 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1684 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1685 add_timer(&ppd->cpspec->chase_timer);
1686 }
1687
1688 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1689 {
1690 u8 ibclt;
1691 unsigned long tnow;
1692
1693 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1694
1695 /*
1696 * Detect and handle the state chase issue, where we can
1697 * get stuck if we are unlucky on timing on both sides of
1698 * the link. If we are, we disable, set a timer, and
1699 * then re-enable.
1700 */
1701 switch (ibclt) {
1702 case IB_7322_LT_STATE_CFGRCVFCFG:
1703 case IB_7322_LT_STATE_CFGWAITRMT:
1704 case IB_7322_LT_STATE_TXREVLANES:
1705 case IB_7322_LT_STATE_CFGENH:
1706 tnow = jiffies;
1707 if (ppd->cpspec->chase_end &&
1708 time_after(tnow, ppd->cpspec->chase_end))
1709 disable_chase(ppd, tnow, ibclt);
1710 else if (!ppd->cpspec->chase_end)
1711 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1712 break;
1713 default:
1714 ppd->cpspec->chase_end = 0;
1715 break;
1716 }
1717
1718 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1719 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1720 ibclt == IB_7322_LT_STATE_LINKUP) &&
1721 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1722 force_h1(ppd);
1723 ppd->cpspec->qdr_reforce = 1;
1724 if (!ppd->dd->cspec->r1)
1725 serdes_7322_los_enable(ppd, 0);
1726 } else if (ppd->cpspec->qdr_reforce &&
1727 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1728 (ibclt == IB_7322_LT_STATE_CFGENH ||
1729 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1730 ibclt == IB_7322_LT_STATE_LINKUP))
1731 force_h1(ppd);
1732
1733 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1734 ppd->link_speed_enabled == QIB_IB_QDR &&
1735 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1736 ibclt == IB_7322_LT_STATE_CFGENH ||
1737 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1738 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1739 adj_tx_serdes(ppd);
1740
1741 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1742 u8 ltstate = qib_7322_phys_portstate(ibcst);
1743 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1744 LinkTrainingState);
1745 if (!ppd->dd->cspec->r1 &&
1746 pibclt == IB_7322_LT_STATE_LINKUP &&
1747 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1748 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1749 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1750 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1751 /* If the link went down (but no into recovery,
1752 * turn LOS back on */
1753 serdes_7322_los_enable(ppd, 1);
1754 if (!ppd->cpspec->qdr_dfe_on &&
1755 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1756 ppd->cpspec->qdr_dfe_on = 1;
1757 ppd->cpspec->qdr_dfe_time = 0;
1758 /* On link down, reenable QDR adaptation */
1759 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1760 ppd->dd->cspec->r1 ?
1761 QDR_STATIC_ADAPT_DOWN_R1 :
1762 QDR_STATIC_ADAPT_DOWN);
1763 printk(KERN_INFO QIB_DRV_NAME
1764 " IB%u:%u re-enabled QDR adaptation "
1765 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
1766 }
1767 }
1768 }
1769
1770 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1771
1772 /*
1773 * This is per-pport error handling.
1774 * will likely get it's own MSIx interrupt (one for each port,
1775 * although just a single handler).
1776 */
1777 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1778 {
1779 char *msg;
1780 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1781 struct qib_devdata *dd = ppd->dd;
1782
1783 /* do this as soon as possible */
1784 fmask = qib_read_kreg64(dd, kr_act_fmask);
1785 if (!fmask)
1786 check_7322_rxe_status(ppd);
1787
1788 errs = qib_read_kreg_port(ppd, krp_errstatus);
1789 if (!errs)
1790 qib_devinfo(dd->pcidev,
1791 "Port%d error interrupt, but no error bits set!\n",
1792 ppd->port);
1793 if (!fmask)
1794 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1795 if (!errs)
1796 goto done;
1797
1798 msg = ppd->cpspec->epmsgbuf;
1799 *msg = '\0';
1800
1801 if (errs & ~QIB_E_P_BITSEXTANT) {
1802 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1803 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1804 if (!*msg)
1805 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1806 "no others");
1807 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1808 " errors 0x%016Lx set (and %s)\n",
1809 (errs & ~QIB_E_P_BITSEXTANT), msg);
1810 *msg = '\0';
1811 }
1812
1813 if (errs & QIB_E_P_SHDR) {
1814 u64 symptom;
1815
1816 /* determine cause, then write to clear */
1817 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1818 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1819 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1820 hdrchk_msgs);
1821 *msg = '\0';
1822 /* senderrbuf cleared in SPKTERRS below */
1823 }
1824
1825 if (errs & QIB_E_P_SPKTERRS) {
1826 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1827 !(ppd->lflags & QIBL_LINKACTIVE)) {
1828 /*
1829 * This can happen when trying to bring the link
1830 * up, but the IB link changes state at the "wrong"
1831 * time. The IB logic then complains that the packet
1832 * isn't valid. We don't want to confuse people, so
1833 * we just don't print them, except at debug
1834 */
1835 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1836 (errs & QIB_E_P_LINK_PKTERRS),
1837 qib_7322p_error_msgs);
1838 *msg = '\0';
1839 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1840 }
1841 qib_disarm_7322_senderrbufs(ppd);
1842 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1843 !(ppd->lflags & QIBL_LINKACTIVE)) {
1844 /*
1845 * This can happen when SMA is trying to bring the link
1846 * up, but the IB link changes state at the "wrong" time.
1847 * The IB logic then complains that the packet isn't
1848 * valid. We don't want to confuse people, so we just
1849 * don't print them, except at debug
1850 */
1851 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1852 qib_7322p_error_msgs);
1853 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1854 *msg = '\0';
1855 }
1856
1857 qib_write_kreg_port(ppd, krp_errclear, errs);
1858
1859 errs &= ~ignore_this_time;
1860 if (!errs)
1861 goto done;
1862
1863 if (errs & QIB_E_P_RPKTERRS)
1864 qib_stats.sps_rcverrs++;
1865 if (errs & QIB_E_P_SPKTERRS)
1866 qib_stats.sps_txerrs++;
1867
1868 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1869
1870 if (errs & QIB_E_P_SDMAERRS)
1871 sdma_7322_p_errors(ppd, errs);
1872
1873 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1874 u64 ibcs;
1875 u8 ltstate;
1876
1877 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1878 ltstate = qib_7322_phys_portstate(ibcs);
1879
1880 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1881 handle_serdes_issues(ppd, ibcs);
1882 if (!(ppd->cpspec->ibcctrl_a &
1883 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1884 /*
1885 * We got our interrupt, so init code should be
1886 * happy and not try alternatives. Now squelch
1887 * other "chatter" from link-negotiation (pre Init)
1888 */
1889 ppd->cpspec->ibcctrl_a |=
1890 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1891 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1892 ppd->cpspec->ibcctrl_a);
1893 }
1894
1895 /* Update our picture of width and speed from chip */
1896 ppd->link_width_active =
1897 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1898 IB_WIDTH_4X : IB_WIDTH_1X;
1899 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1900 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1901 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1902 QIB_IB_DDR : QIB_IB_SDR;
1903
1904 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1905 IB_PHYSPORTSTATE_DISABLED)
1906 qib_set_ib_7322_lstate(ppd, 0,
1907 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1908 else
1909 /*
1910 * Since going into a recovery state causes the link
1911 * state to go down and since recovery is transitory,
1912 * it is better if we "miss" ever seeing the link
1913 * training state go into recovery (i.e., ignore this
1914 * transition for link state special handling purposes)
1915 * without updating lastibcstat.
1916 */
1917 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1918 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1919 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1920 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1921 qib_handle_e_ibstatuschanged(ppd, ibcs);
1922 }
1923 if (*msg && iserr)
1924 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1925
1926 if (ppd->state_wanted & ppd->lflags)
1927 wake_up_interruptible(&ppd->state_wait);
1928 done:
1929 return;
1930 }
1931
1932 /* enable/disable chip from delivering interrupts */
1933 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1934 {
1935 if (enable) {
1936 if (dd->flags & QIB_BADINTR)
1937 return;
1938 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1939 /* cause any pending enabled interrupts to be re-delivered */
1940 qib_write_kreg(dd, kr_intclear, 0ULL);
1941 if (dd->cspec->num_msix_entries) {
1942 /* and same for MSIx */
1943 u64 val = qib_read_kreg64(dd, kr_intgranted);
1944 if (val)
1945 qib_write_kreg(dd, kr_intgranted, val);
1946 }
1947 } else
1948 qib_write_kreg(dd, kr_intmask, 0ULL);
1949 }
1950
1951 /*
1952 * Try to cleanup as much as possible for anything that might have gone
1953 * wrong while in freeze mode, such as pio buffers being written by user
1954 * processes (causing armlaunch), send errors due to going into freeze mode,
1955 * etc., and try to avoid causing extra interrupts while doing so.
1956 * Forcibly update the in-memory pioavail register copies after cleanup
1957 * because the chip won't do it while in freeze mode (the register values
1958 * themselves are kept correct).
1959 * Make sure that we don't lose any important interrupts by using the chip
1960 * feature that says that writing 0 to a bit in *clear that is set in
1961 * *status will cause an interrupt to be generated again (if allowed by
1962 * the *mask value).
1963 * This is in chip-specific code because of all of the register accesses,
1964 * even though the details are similar on most chips.
1965 */
1966 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1967 {
1968 int pidx;
1969
1970 /* disable error interrupts, to avoid confusion */
1971 qib_write_kreg(dd, kr_errmask, 0ULL);
1972
1973 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1974 if (dd->pport[pidx].link_speed_supported)
1975 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1976 0ULL);
1977
1978 /* also disable interrupts; errormask is sometimes overwriten */
1979 qib_7322_set_intr_state(dd, 0);
1980
1981 /* clear the freeze, and be sure chip saw it */
1982 qib_write_kreg(dd, kr_control, dd->control);
1983 qib_read_kreg32(dd, kr_scratch);
1984
1985 /*
1986 * Force new interrupt if any hwerr, error or interrupt bits are
1987 * still set, and clear "safe" send packet errors related to freeze
1988 * and cancelling sends. Re-enable error interrupts before possible
1989 * force of re-interrupt on pending interrupts.
1990 */
1991 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1992 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1993 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1994 /* We need to purge per-port errs and reset mask, too */
1995 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1996 if (!dd->pport[pidx].link_speed_supported)
1997 continue;
1998 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1999 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
2000 }
2001 qib_7322_set_intr_state(dd, 1);
2002 }
2003
2004 /* no error handling to speak of */
2005 /**
2006 * qib_7322_handle_hwerrors - display hardware errors.
2007 * @dd: the qlogic_ib device
2008 * @msg: the output buffer
2009 * @msgl: the size of the output buffer
2010 *
2011 * Use same msg buffer as regular errors to avoid excessive stack
2012 * use. Most hardware errors are catastrophic, but for right now,
2013 * we'll print them and continue. We reuse the same message buffer as
2014 * qib_handle_errors() to avoid excessive stack usage.
2015 */
2016 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2017 size_t msgl)
2018 {
2019 u64 hwerrs;
2020 u32 ctrl;
2021 int isfatal = 0;
2022
2023 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2024 if (!hwerrs)
2025 goto bail;
2026 if (hwerrs == ~0ULL) {
2027 qib_dev_err(dd, "Read of hardware error status failed "
2028 "(all bits set); ignoring\n");
2029 goto bail;
2030 }
2031 qib_stats.sps_hwerrs++;
2032
2033 /* Always clear the error status register, except BIST fail */
2034 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2035 ~HWE_MASK(PowerOnBISTFailed));
2036
2037 hwerrs &= dd->cspec->hwerrmask;
2038
2039 /* no EEPROM logging, yet */
2040
2041 if (hwerrs)
2042 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2043 "(cleared)\n", (unsigned long long) hwerrs);
2044
2045 ctrl = qib_read_kreg32(dd, kr_control);
2046 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2047 /*
2048 * No recovery yet...
2049 */
2050 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2051 dd->cspec->stay_in_freeze) {
2052 /*
2053 * If any set that we aren't ignoring only make the
2054 * complaint once, in case it's stuck or recurring,
2055 * and we get here multiple times
2056 * Force link down, so switch knows, and
2057 * LEDs are turned off.
2058 */
2059 if (dd->flags & QIB_INITTED)
2060 isfatal = 1;
2061 } else
2062 qib_7322_clear_freeze(dd);
2063 }
2064
2065 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2066 isfatal = 1;
2067 strlcpy(msg, "[Memory BIST test failed, "
2068 "InfiniPath hardware unusable]", msgl);
2069 /* ignore from now on, so disable until driver reloaded */
2070 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2071 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2072 }
2073
2074 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2075
2076 /* Ignore esoteric PLL failures et al. */
2077
2078 qib_dev_err(dd, "%s hardware error\n", msg);
2079
2080 if (isfatal && !dd->diag_client) {
2081 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2082 " usable, SN %.16s\n", dd->serial);
2083 /*
2084 * for /sys status file and user programs to print; if no
2085 * trailing brace is copied, we'll know it was truncated.
2086 */
2087 if (dd->freezemsg)
2088 snprintf(dd->freezemsg, dd->freezelen,
2089 "{%s}", msg);
2090 qib_disable_after_error(dd);
2091 }
2092 bail:;
2093 }
2094
2095 /**
2096 * qib_7322_init_hwerrors - enable hardware errors
2097 * @dd: the qlogic_ib device
2098 *
2099 * now that we have finished initializing everything that might reasonably
2100 * cause a hardware error, and cleared those errors bits as they occur,
2101 * we can enable hardware errors in the mask (potentially enabling
2102 * freeze mode), and enable hardware errors as errors (along with
2103 * everything else) in errormask
2104 */
2105 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2106 {
2107 int pidx;
2108 u64 extsval;
2109
2110 extsval = qib_read_kreg64(dd, kr_extstatus);
2111 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2112 QIB_EXTS_MEMBIST_ENDTEST)))
2113 qib_dev_err(dd, "MemBIST did not complete!\n");
2114
2115 /* never clear BIST failure, so reported on each driver load */
2116 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2117 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2118
2119 /* clear all */
2120 qib_write_kreg(dd, kr_errclear, ~0ULL);
2121 /* enable errors that are masked, at least this first time. */
2122 qib_write_kreg(dd, kr_errmask, ~0ULL);
2123 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2124 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2125 if (dd->pport[pidx].link_speed_supported)
2126 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2127 ~0ULL);
2128 }
2129
2130 /*
2131 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2132 * on chips that are count-based, rather than trigger-based. There is no
2133 * reference counting, but that's also fine, given the intended use.
2134 * Only chip-specific because it's all register accesses
2135 */
2136 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2137 {
2138 if (enable) {
2139 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2140 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2141 } else
2142 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2143 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2144 }
2145
2146 /*
2147 * Formerly took parameter <which> in pre-shifted,
2148 * pre-merged form with LinkCmd and LinkInitCmd
2149 * together, and assuming the zero was NOP.
2150 */
2151 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2152 u16 linitcmd)
2153 {
2154 u64 mod_wd;
2155 struct qib_devdata *dd = ppd->dd;
2156 unsigned long flags;
2157
2158 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2159 /*
2160 * If we are told to disable, note that so link-recovery
2161 * code does not attempt to bring us back up.
2162 * Also reset everything that we can, so we start
2163 * completely clean when re-enabled (before we
2164 * actually issue the disable to the IBC)
2165 */
2166 qib_7322_mini_pcs_reset(ppd);
2167 spin_lock_irqsave(&ppd->lflags_lock, flags);
2168 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2169 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2170 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2171 /*
2172 * Any other linkinitcmd will lead to LINKDOWN and then
2173 * to INIT (if all is well), so clear flag to let
2174 * link-recovery code attempt to bring us back up.
2175 */
2176 spin_lock_irqsave(&ppd->lflags_lock, flags);
2177 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2178 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2179 /*
2180 * Clear status change interrupt reduction so the
2181 * new state is seen.
2182 */
2183 ppd->cpspec->ibcctrl_a &=
2184 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2185 }
2186
2187 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2188 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2189
2190 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2191 mod_wd);
2192 /* write to chip to prevent back-to-back writes of ibc reg */
2193 qib_write_kreg(dd, kr_scratch, 0);
2194
2195 }
2196
2197 /*
2198 * The total RCV buffer memory is 64KB, used for both ports, and is
2199 * in units of 64 bytes (same as IB flow control credit unit).
2200 * The consumedVL unit in the same registers are in 32 byte units!
2201 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2202 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2203 * in krp_rxcreditvl15, rather than 10.
2204 */
2205 #define RCV_BUF_UNITSZ 64
2206 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2207
2208 static void set_vls(struct qib_pportdata *ppd)
2209 {
2210 int i, numvls, totcred, cred_vl, vl0extra;
2211 struct qib_devdata *dd = ppd->dd;
2212 u64 val;
2213
2214 numvls = qib_num_vls(ppd->vls_operational);
2215
2216 /*
2217 * Set up per-VL credits. Below is kluge based on these assumptions:
2218 * 1) port is disabled at the time early_init is called.
2219 * 2) give VL15 17 credits, for two max-plausible packets.
2220 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2221 */
2222 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2223 totcred = NUM_RCV_BUF_UNITS(dd);
2224 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2225 totcred -= cred_vl;
2226 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2227 cred_vl = totcred / numvls;
2228 vl0extra = totcred - cred_vl * numvls;
2229 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2230 for (i = 1; i < numvls; i++)
2231 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2232 for (; i < 8; i++) /* no buffer space for other VLs */
2233 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2234
2235 /* Notify IBC that credits need to be recalculated */
2236 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2237 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2238 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2239 qib_write_kreg(dd, kr_scratch, 0ULL);
2240 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2241 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2242
2243 for (i = 0; i < numvls; i++)
2244 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2245 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2246
2247 /* Change the number of operational VLs */
2248 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2249 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2250 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2251 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2252 qib_write_kreg(dd, kr_scratch, 0ULL);
2253 }
2254
2255 /*
2256 * The code that deals with actual SerDes is in serdes_7322_init().
2257 * Compared to the code for iba7220, it is minimal.
2258 */
2259 static int serdes_7322_init(struct qib_pportdata *ppd);
2260
2261 /**
2262 * qib_7322_bringup_serdes - bring up the serdes
2263 * @ppd: physical port on the qlogic_ib device
2264 */
2265 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2266 {
2267 struct qib_devdata *dd = ppd->dd;
2268 u64 val, guid, ibc;
2269 unsigned long flags;
2270 int ret = 0;
2271
2272 /*
2273 * SerDes model not in Pd, but still need to
2274 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2275 * eventually.
2276 */
2277 /* Put IBC in reset, sends disabled (should be in reset already) */
2278 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2279 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2280 qib_write_kreg(dd, kr_scratch, 0ULL);
2281
2282 /* ensure previous Tx parameters are not still forced */
2283 qib_write_kreg_port(ppd, krp_tx_deemph_override,
2284 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
2285 reset_tx_deemphasis_override));
2286
2287 if (qib_compat_ddr_negotiate) {
2288 ppd->cpspec->ibdeltainprog = 1;
2289 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2290 crp_ibsymbolerr);
2291 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2292 crp_iblinkerrrecov);
2293 }
2294
2295 /* flowcontrolwatermark is in units of KBytes */
2296 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2297 /*
2298 * Flow control is sent this often, even if no changes in
2299 * buffer space occur. Units are 128ns for this chip.
2300 * Set to 3usec.
2301 */
2302 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2303 /* max error tolerance */
2304 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2305 /* IB credit flow control. */
2306 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2307 /*
2308 * set initial max size pkt IBC will send, including ICRC; it's the
2309 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2310 */
2311 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2312 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2313 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2314
2315 /*
2316 * Reset the PCS interface to the serdes (and also ibc, which is still
2317 * in reset from above). Writes new value of ibcctrl_a as last step.
2318 */
2319 qib_7322_mini_pcs_reset(ppd);
2320
2321 if (!ppd->cpspec->ibcctrl_b) {
2322 unsigned lse = ppd->link_speed_enabled;
2323
2324 /*
2325 * Not on re-init after reset, establish shadow
2326 * and force initial config.
2327 */
2328 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2329 krp_ibcctrl_b);
2330 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2331 IBA7322_IBC_SPEED_DDR |
2332 IBA7322_IBC_SPEED_SDR |
2333 IBA7322_IBC_WIDTH_AUTONEG |
2334 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2335 if (lse & (lse - 1)) /* Muliple speeds enabled */
2336 ppd->cpspec->ibcctrl_b |=
2337 (lse << IBA7322_IBC_SPEED_LSB) |
2338 IBA7322_IBC_IBTA_1_2_MASK |
2339 IBA7322_IBC_MAX_SPEED_MASK;
2340 else
2341 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2342 IBA7322_IBC_SPEED_QDR |
2343 IBA7322_IBC_IBTA_1_2_MASK :
2344 (lse == QIB_IB_DDR) ?
2345 IBA7322_IBC_SPEED_DDR :
2346 IBA7322_IBC_SPEED_SDR;
2347 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2348 (IB_WIDTH_1X | IB_WIDTH_4X))
2349 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2350 else
2351 ppd->cpspec->ibcctrl_b |=
2352 ppd->link_width_enabled == IB_WIDTH_4X ?
2353 IBA7322_IBC_WIDTH_4X_ONLY :
2354 IBA7322_IBC_WIDTH_1X_ONLY;
2355
2356 /* always enable these on driver reload, not sticky */
2357 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2358 IBA7322_IBC_HRTBT_MASK);
2359 }
2360 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2361
2362 /* setup so we have more time at CFGTEST to change H1 */
2363 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2364 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2365 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2366 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2367
2368 serdes_7322_init(ppd);
2369
2370 guid = be64_to_cpu(ppd->guid);
2371 if (!guid) {
2372 if (dd->base_guid)
2373 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2374 ppd->guid = cpu_to_be64(guid);
2375 }
2376
2377 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2378 /* write to chip to prevent back-to-back writes of ibc reg */
2379 qib_write_kreg(dd, kr_scratch, 0);
2380
2381 /* Enable port */
2382 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2383 set_vls(ppd);
2384
2385 /* initially come up DISABLED, without sending anything. */
2386 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2387 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2388 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2389 qib_write_kreg(dd, kr_scratch, 0ULL);
2390 /* clear the linkinit cmds */
2391 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2392
2393 /* be paranoid against later code motion, etc. */
2394 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2395 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2396 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2397 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2398
2399 /* Also enable IBSTATUSCHG interrupt. */
2400 val = qib_read_kreg_port(ppd, krp_errmask);
2401 qib_write_kreg_port(ppd, krp_errmask,
2402 val | ERR_MASK_N(IBStatusChanged));
2403
2404 /* Always zero until we start messing with SerDes for real */
2405 return ret;
2406 }
2407
2408 /**
2409 * qib_7322_quiet_serdes - set serdes to txidle
2410 * @dd: the qlogic_ib device
2411 * Called when driver is being unloaded
2412 */
2413 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2414 {
2415 u64 val;
2416 unsigned long flags;
2417
2418 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2419
2420 spin_lock_irqsave(&ppd->lflags_lock, flags);
2421 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2422 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2423 wake_up(&ppd->cpspec->autoneg_wait);
2424 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2425 if (ppd->dd->cspec->r1)
2426 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2427
2428 ppd->cpspec->chase_end = 0;
2429 if (ppd->cpspec->chase_timer.data) /* if initted */
2430 del_timer_sync(&ppd->cpspec->chase_timer);
2431
2432 /*
2433 * Despite the name, actually disables IBC as well. Do it when
2434 * we are as sure as possible that no more packets can be
2435 * received, following the down and the PCS reset.
2436 * The actual disabling happens in qib_7322_mini_pci_reset(),
2437 * along with the PCS being reset.
2438 */
2439 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2440 qib_7322_mini_pcs_reset(ppd);
2441
2442 /*
2443 * Update the adjusted counters so the adjustment persists
2444 * across driver reload.
2445 */
2446 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2447 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2448 struct qib_devdata *dd = ppd->dd;
2449 u64 diagc;
2450
2451 /* enable counter writes */
2452 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2453 qib_write_kreg(dd, kr_hwdiagctrl,
2454 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2455
2456 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2457 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2458 if (ppd->cpspec->ibdeltainprog)
2459 val -= val - ppd->cpspec->ibsymsnap;
2460 val -= ppd->cpspec->ibsymdelta;
2461 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2462 }
2463 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2464 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2465 if (ppd->cpspec->ibdeltainprog)
2466 val -= val - ppd->cpspec->iblnkerrsnap;
2467 val -= ppd->cpspec->iblnkerrdelta;
2468 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2469 }
2470 if (ppd->cpspec->iblnkdowndelta) {
2471 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2472 val += ppd->cpspec->iblnkdowndelta;
2473 write_7322_creg_port(ppd, crp_iblinkdown, val);
2474 }
2475 /*
2476 * No need to save ibmalfdelta since IB perfcounters
2477 * are cleared on driver reload.
2478 */
2479
2480 /* and disable counter writes */
2481 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2482 }
2483 }
2484
2485 /**
2486 * qib_setup_7322_setextled - set the state of the two external LEDs
2487 * @ppd: physical port on the qlogic_ib device
2488 * @on: whether the link is up or not
2489 *
2490 * The exact combo of LEDs if on is true is determined by looking
2491 * at the ibcstatus.
2492 *
2493 * These LEDs indicate the physical and logical state of IB link.
2494 * For this chip (at least with recommended board pinouts), LED1
2495 * is Yellow (logical state) and LED2 is Green (physical state),
2496 *
2497 * Note: We try to match the Mellanox HCA LED behavior as best
2498 * we can. Green indicates physical link state is OK (something is
2499 * plugged in, and we can train).
2500 * Amber indicates the link is logically up (ACTIVE).
2501 * Mellanox further blinks the amber LED to indicate data packet
2502 * activity, but we have no hardware support for that, so it would
2503 * require waking up every 10-20 msecs and checking the counters
2504 * on the chip, and then turning the LED off if appropriate. That's
2505 * visible overhead, so not something we will do.
2506 */
2507 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2508 {
2509 struct qib_devdata *dd = ppd->dd;
2510 u64 extctl, ledblink = 0, val;
2511 unsigned long flags;
2512 int yel, grn;
2513
2514 /*
2515 * The diags use the LED to indicate diag info, so we leave
2516 * the external LED alone when the diags are running.
2517 */
2518 if (dd->diag_client)
2519 return;
2520
2521 /* Allow override of LED display for, e.g. Locating system in rack */
2522 if (ppd->led_override) {
2523 grn = (ppd->led_override & QIB_LED_PHYS);
2524 yel = (ppd->led_override & QIB_LED_LOG);
2525 } else if (on) {
2526 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2527 grn = qib_7322_phys_portstate(val) ==
2528 IB_PHYSPORTSTATE_LINKUP;
2529 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2530 } else {
2531 grn = 0;
2532 yel = 0;
2533 }
2534
2535 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2536 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2537 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2538 if (grn) {
2539 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2540 /*
2541 * Counts are in chip clock (4ns) periods.
2542 * This is 1/16 sec (66.6ms) on,
2543 * 3/16 sec (187.5 ms) off, with packets rcvd.
2544 */
2545 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2546 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2547 }
2548 if (yel)
2549 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2550 dd->cspec->extctrl = extctl;
2551 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2552 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2553
2554 if (ledblink) /* blink the LED on packet receive */
2555 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2556 }
2557
2558 /*
2559 * Disable MSIx interrupt if enabled, call generic MSIx code
2560 * to cleanup, and clear pending MSIx interrupts.
2561 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2562 */
2563 static void qib_7322_nomsix(struct qib_devdata *dd)
2564 {
2565 u64 intgranted;
2566 int n;
2567
2568 dd->cspec->main_int_mask = ~0ULL;
2569 n = dd->cspec->num_msix_entries;
2570 if (n) {
2571 int i;
2572
2573 dd->cspec->num_msix_entries = 0;
2574 for (i = 0; i < n; i++) {
2575 irq_set_affinity_hint(
2576 dd->cspec->msix_entries[i].msix.vector, NULL);
2577 free_cpumask_var(dd->cspec->msix_entries[i].mask);
2578 free_irq(dd->cspec->msix_entries[i].msix.vector,
2579 dd->cspec->msix_entries[i].arg);
2580 }
2581 qib_nomsix(dd);
2582 }
2583 /* make sure no MSIx interrupts are left pending */
2584 intgranted = qib_read_kreg64(dd, kr_intgranted);
2585 if (intgranted)
2586 qib_write_kreg(dd, kr_intgranted, intgranted);
2587 }
2588
2589 static void qib_7322_free_irq(struct qib_devdata *dd)
2590 {
2591 if (dd->cspec->irq) {
2592 free_irq(dd->cspec->irq, dd);
2593 dd->cspec->irq = 0;
2594 }
2595 qib_7322_nomsix(dd);
2596 }
2597
2598 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2599 {
2600 int i;
2601
2602 qib_7322_free_irq(dd);
2603 kfree(dd->cspec->cntrs);
2604 kfree(dd->cspec->sendchkenable);
2605 kfree(dd->cspec->sendgrhchk);
2606 kfree(dd->cspec->sendibchk);
2607 kfree(dd->cspec->msix_entries);
2608 for (i = 0; i < dd->num_pports; i++) {
2609 unsigned long flags;
2610 u32 mask = QSFP_GPIO_MOD_PRS_N |
2611 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2612
2613 kfree(dd->pport[i].cpspec->portcntrs);
2614 if (dd->flags & QIB_HAS_QSFP) {
2615 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2616 dd->cspec->gpio_mask &= ~mask;
2617 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2618 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2619 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2620 }
2621 if (dd->pport[i].ibport_data.smi_ah)
2622 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2623 }
2624 }
2625
2626 /* handle SDMA interrupts */
2627 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2628 {
2629 struct qib_pportdata *ppd0 = &dd->pport[0];
2630 struct qib_pportdata *ppd1 = &dd->pport[1];
2631 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2632 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2633 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2634 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2635
2636 if (intr0)
2637 qib_sdma_intr(ppd0);
2638 if (intr1)
2639 qib_sdma_intr(ppd1);
2640
2641 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2642 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2643 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2644 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2645 }
2646
2647 /*
2648 * Set or clear the Send buffer available interrupt enable bit.
2649 */
2650 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2651 {
2652 unsigned long flags;
2653
2654 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2655 if (needint)
2656 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2657 else
2658 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2659 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2660 qib_write_kreg(dd, kr_scratch, 0ULL);
2661 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2662 }
2663
2664 /*
2665 * Somehow got an interrupt with reserved bits set in interrupt status.
2666 * Print a message so we know it happened, then clear them.
2667 * keep mainline interrupt handler cache-friendly
2668 */
2669 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2670 {
2671 u64 kills;
2672 char msg[128];
2673
2674 kills = istat & ~QIB_I_BITSEXTANT;
2675 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2676 " %s\n", (unsigned long long) kills, msg);
2677 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2678 }
2679
2680 /* keep mainline interrupt handler cache-friendly */
2681 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2682 {
2683 u32 gpiostatus;
2684 int handled = 0;
2685 int pidx;
2686
2687 /*
2688 * Boards for this chip currently don't use GPIO interrupts,
2689 * so clear by writing GPIOstatus to GPIOclear, and complain
2690 * to developer. To avoid endless repeats, clear
2691 * the bits in the mask, since there is some kind of
2692 * programming error or chip problem.
2693 */
2694 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2695 /*
2696 * In theory, writing GPIOstatus to GPIOclear could
2697 * have a bad side-effect on some diagnostic that wanted
2698 * to poll for a status-change, but the various shadows
2699 * make that problematic at best. Diags will just suppress
2700 * all GPIO interrupts during such tests.
2701 */
2702 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2703 /*
2704 * Check for QSFP MOD_PRS changes
2705 * only works for single port if IB1 != pidx1
2706 */
2707 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2708 ++pidx) {
2709 struct qib_pportdata *ppd;
2710 struct qib_qsfp_data *qd;
2711 u32 mask;
2712 if (!dd->pport[pidx].link_speed_supported)
2713 continue;
2714 mask = QSFP_GPIO_MOD_PRS_N;
2715 ppd = dd->pport + pidx;
2716 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2717 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2718 u64 pins;
2719 qd = &ppd->cpspec->qsfp_data;
2720 gpiostatus &= ~mask;
2721 pins = qib_read_kreg64(dd, kr_extstatus);
2722 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2723 if (!(pins & mask)) {
2724 ++handled;
2725 qd->t_insert = jiffies;
2726 queue_work(ib_wq, &qd->work);
2727 }
2728 }
2729 }
2730
2731 if (gpiostatus && !handled) {
2732 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2733 u32 gpio_irq = mask & gpiostatus;
2734
2735 /*
2736 * Clear any troublemakers, and update chip from shadow
2737 */
2738 dd->cspec->gpio_mask &= ~gpio_irq;
2739 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2740 }
2741 }
2742
2743 /*
2744 * Handle errors and unusual events first, separate function
2745 * to improve cache hits for fast path interrupt handling.
2746 */
2747 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2748 {
2749 if (istat & ~QIB_I_BITSEXTANT)
2750 unknown_7322_ibits(dd, istat);
2751 if (istat & QIB_I_GPIO)
2752 unknown_7322_gpio_intr(dd);
2753 if (istat & QIB_I_C_ERROR) {
2754 qib_write_kreg(dd, kr_errmask, 0ULL);
2755 tasklet_schedule(&dd->error_tasklet);
2756 }
2757 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2758 handle_7322_p_errors(dd->rcd[0]->ppd);
2759 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2760 handle_7322_p_errors(dd->rcd[1]->ppd);
2761 }
2762
2763 /*
2764 * Dynamically adjust the rcv int timeout for a context based on incoming
2765 * packet rate.
2766 */
2767 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2768 {
2769 struct qib_devdata *dd = rcd->dd;
2770 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2771
2772 /*
2773 * Dynamically adjust idle timeout on chip
2774 * based on number of packets processed.
2775 */
2776 if (npkts < rcv_int_count && timeout > 2)
2777 timeout >>= 1;
2778 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2779 timeout = min(timeout << 1, rcv_int_timeout);
2780 else
2781 return;
2782
2783 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2784 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2785 }
2786
2787 /*
2788 * This is the main interrupt handler.
2789 * It will normally only be used for low frequency interrupts but may
2790 * have to handle all interrupts if INTx is enabled or fewer than normal
2791 * MSIx interrupts were allocated.
2792 * This routine should ignore the interrupt bits for any of the
2793 * dedicated MSIx handlers.
2794 */
2795 static irqreturn_t qib_7322intr(int irq, void *data)
2796 {
2797 struct qib_devdata *dd = data;
2798 irqreturn_t ret;
2799 u64 istat;
2800 u64 ctxtrbits;
2801 u64 rmask;
2802 unsigned i;
2803 u32 npkts;
2804
2805 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2806 /*
2807 * This return value is not great, but we do not want the
2808 * interrupt core code to remove our interrupt handler
2809 * because we don't appear to be handling an interrupt
2810 * during a chip reset.
2811 */
2812 ret = IRQ_HANDLED;
2813 goto bail;
2814 }
2815
2816 istat = qib_read_kreg64(dd, kr_intstatus);
2817
2818 if (unlikely(istat == ~0ULL)) {
2819 qib_bad_intrstatus(dd);
2820 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2821 /* don't know if it was our interrupt or not */
2822 ret = IRQ_NONE;
2823 goto bail;
2824 }
2825
2826 istat &= dd->cspec->main_int_mask;
2827 if (unlikely(!istat)) {
2828 /* already handled, or shared and not us */
2829 ret = IRQ_NONE;
2830 goto bail;
2831 }
2832
2833 qib_stats.sps_ints++;
2834 if (dd->int_counter != (u32) -1)
2835 dd->int_counter++;
2836
2837 /* handle "errors" of various kinds first, device ahead of port */
2838 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2839 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2840 INT_MASK_P(Err, 1))))
2841 unlikely_7322_intr(dd, istat);
2842
2843 /*
2844 * Clear the interrupt bits we found set, relatively early, so we
2845 * "know" know the chip will have seen this by the time we process
2846 * the queue, and will re-interrupt if necessary. The processor
2847 * itself won't take the interrupt again until we return.
2848 */
2849 qib_write_kreg(dd, kr_intclear, istat);
2850
2851 /*
2852 * Handle kernel receive queues before checking for pio buffers
2853 * available since receives can overflow; piobuf waiters can afford
2854 * a few extra cycles, since they were waiting anyway.
2855 */
2856 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2857 if (ctxtrbits) {
2858 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2859 (1ULL << QIB_I_RCVURG_LSB);
2860 for (i = 0; i < dd->first_user_ctxt; i++) {
2861 if (ctxtrbits & rmask) {
2862 ctxtrbits &= ~rmask;
2863 if (dd->rcd[i])
2864 qib_kreceive(dd->rcd[i], NULL, &npkts);
2865 }
2866 rmask <<= 1;
2867 }
2868 if (ctxtrbits) {
2869 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2870 (ctxtrbits >> QIB_I_RCVURG_LSB);
2871 qib_handle_urcv(dd, ctxtrbits);
2872 }
2873 }
2874
2875 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2876 sdma_7322_intr(dd, istat);
2877
2878 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2879 qib_ib_piobufavail(dd);
2880
2881 ret = IRQ_HANDLED;
2882 bail:
2883 return ret;
2884 }
2885
2886 /*
2887 * Dedicated receive packet available interrupt handler.
2888 */
2889 static irqreturn_t qib_7322pintr(int irq, void *data)
2890 {
2891 struct qib_ctxtdata *rcd = data;
2892 struct qib_devdata *dd = rcd->dd;
2893 u32 npkts;
2894
2895 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2896 /*
2897 * This return value is not great, but we do not want the
2898 * interrupt core code to remove our interrupt handler
2899 * because we don't appear to be handling an interrupt
2900 * during a chip reset.
2901 */
2902 return IRQ_HANDLED;
2903
2904 qib_stats.sps_ints++;
2905 if (dd->int_counter != (u32) -1)
2906 dd->int_counter++;
2907
2908 /* Clear the interrupt bit we expect to be set. */
2909 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2910 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2911
2912 qib_kreceive(rcd, NULL, &npkts);
2913
2914 return IRQ_HANDLED;
2915 }
2916
2917 /*
2918 * Dedicated Send buffer available interrupt handler.
2919 */
2920 static irqreturn_t qib_7322bufavail(int irq, void *data)
2921 {
2922 struct qib_devdata *dd = data;
2923
2924 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2925 /*
2926 * This return value is not great, but we do not want the
2927 * interrupt core code to remove our interrupt handler
2928 * because we don't appear to be handling an interrupt
2929 * during a chip reset.
2930 */
2931 return IRQ_HANDLED;
2932
2933 qib_stats.sps_ints++;
2934 if (dd->int_counter != (u32) -1)
2935 dd->int_counter++;
2936
2937 /* Clear the interrupt bit we expect to be set. */
2938 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2939
2940 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2941 if (dd->flags & QIB_INITTED)
2942 qib_ib_piobufavail(dd);
2943 else
2944 qib_wantpiobuf_7322_intr(dd, 0);
2945
2946 return IRQ_HANDLED;
2947 }
2948
2949 /*
2950 * Dedicated Send DMA interrupt handler.
2951 */
2952 static irqreturn_t sdma_intr(int irq, void *data)
2953 {
2954 struct qib_pportdata *ppd = data;
2955 struct qib_devdata *dd = ppd->dd;
2956
2957 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2958 /*
2959 * This return value is not great, but we do not want the
2960 * interrupt core code to remove our interrupt handler
2961 * because we don't appear to be handling an interrupt
2962 * during a chip reset.
2963 */
2964 return IRQ_HANDLED;
2965
2966 qib_stats.sps_ints++;
2967 if (dd->int_counter != (u32) -1)
2968 dd->int_counter++;
2969
2970 /* Clear the interrupt bit we expect to be set. */
2971 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2972 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2973 qib_sdma_intr(ppd);
2974
2975 return IRQ_HANDLED;
2976 }
2977
2978 /*
2979 * Dedicated Send DMA idle interrupt handler.
2980 */
2981 static irqreturn_t sdma_idle_intr(int irq, void *data)
2982 {
2983 struct qib_pportdata *ppd = data;
2984 struct qib_devdata *dd = ppd->dd;
2985
2986 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2987 /*
2988 * This return value is not great, but we do not want the
2989 * interrupt core code to remove our interrupt handler
2990 * because we don't appear to be handling an interrupt
2991 * during a chip reset.
2992 */
2993 return IRQ_HANDLED;
2994
2995 qib_stats.sps_ints++;
2996 if (dd->int_counter != (u32) -1)
2997 dd->int_counter++;
2998
2999 /* Clear the interrupt bit we expect to be set. */
3000 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3001 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3002 qib_sdma_intr(ppd);
3003
3004 return IRQ_HANDLED;
3005 }
3006
3007 /*
3008 * Dedicated Send DMA progress interrupt handler.
3009 */
3010 static irqreturn_t sdma_progress_intr(int irq, void *data)
3011 {
3012 struct qib_pportdata *ppd = data;
3013 struct qib_devdata *dd = ppd->dd;
3014
3015 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3016 /*
3017 * This return value is not great, but we do not want the
3018 * interrupt core code to remove our interrupt handler
3019 * because we don't appear to be handling an interrupt
3020 * during a chip reset.
3021 */
3022 return IRQ_HANDLED;
3023
3024 qib_stats.sps_ints++;
3025 if (dd->int_counter != (u32) -1)
3026 dd->int_counter++;
3027
3028 /* Clear the interrupt bit we expect to be set. */
3029 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3030 INT_MASK_P(SDmaProgress, 1) :
3031 INT_MASK_P(SDmaProgress, 0));
3032 qib_sdma_intr(ppd);
3033
3034 return IRQ_HANDLED;
3035 }
3036
3037 /*
3038 * Dedicated Send DMA cleanup interrupt handler.
3039 */
3040 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3041 {
3042 struct qib_pportdata *ppd = data;
3043 struct qib_devdata *dd = ppd->dd;
3044
3045 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3046 /*
3047 * This return value is not great, but we do not want the
3048 * interrupt core code to remove our interrupt handler
3049 * because we don't appear to be handling an interrupt
3050 * during a chip reset.
3051 */
3052 return IRQ_HANDLED;
3053
3054 qib_stats.sps_ints++;
3055 if (dd->int_counter != (u32) -1)
3056 dd->int_counter++;
3057
3058 /* Clear the interrupt bit we expect to be set. */
3059 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3060 INT_MASK_PM(SDmaCleanupDone, 1) :
3061 INT_MASK_PM(SDmaCleanupDone, 0));
3062 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3063
3064 return IRQ_HANDLED;
3065 }
3066
3067 /*
3068 * Set up our chip-specific interrupt handler.
3069 * The interrupt type has already been setup, so
3070 * we just need to do the registration and error checking.
3071 * If we are using MSIx interrupts, we may fall back to
3072 * INTx later, if the interrupt handler doesn't get called
3073 * within 1/2 second (see verify_interrupt()).
3074 */
3075 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3076 {
3077 int ret, i, msixnum;
3078 u64 redirect[6];
3079 u64 mask;
3080 const struct cpumask *local_mask;
3081 int firstcpu, secondcpu = 0, currrcvcpu = 0;
3082
3083 if (!dd->num_pports)
3084 return;
3085
3086 if (clearpend) {
3087 /*
3088 * if not switching interrupt types, be sure interrupts are
3089 * disabled, and then clear anything pending at this point,
3090 * because we are starting clean.
3091 */
3092 qib_7322_set_intr_state(dd, 0);
3093
3094 /* clear the reset error, init error/hwerror mask */
3095 qib_7322_init_hwerrors(dd);
3096
3097 /* clear any interrupt bits that might be set */
3098 qib_write_kreg(dd, kr_intclear, ~0ULL);
3099
3100 /* make sure no pending MSIx intr, and clear diag reg */
3101 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3102 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3103 }
3104
3105 if (!dd->cspec->num_msix_entries) {
3106 /* Try to get INTx interrupt */
3107 try_intx:
3108 if (!dd->pcidev->irq) {
3109 qib_dev_err(dd, "irq is 0, BIOS error? "
3110 "Interrupts won't work\n");
3111 goto bail;
3112 }
3113 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3114 IRQF_SHARED, QIB_DRV_NAME, dd);
3115 if (ret) {
3116 qib_dev_err(dd, "Couldn't setup INTx "
3117 "interrupt (irq=%d): %d\n",
3118 dd->pcidev->irq, ret);
3119 goto bail;
3120 }
3121 dd->cspec->irq = dd->pcidev->irq;
3122 dd->cspec->main_int_mask = ~0ULL;
3123 goto bail;
3124 }
3125
3126 /* Try to get MSIx interrupts */
3127 memset(redirect, 0, sizeof redirect);
3128 mask = ~0ULL;
3129 msixnum = 0;
3130 local_mask = cpumask_of_pcibus(dd->pcidev->bus);
3131 firstcpu = cpumask_first(local_mask);
3132 if (firstcpu >= nr_cpu_ids ||
3133 cpumask_weight(local_mask) == num_online_cpus()) {
3134 local_mask = topology_core_cpumask(0);
3135 firstcpu = cpumask_first(local_mask);
3136 }
3137 if (firstcpu < nr_cpu_ids) {
3138 secondcpu = cpumask_next(firstcpu, local_mask);
3139 if (secondcpu >= nr_cpu_ids)
3140 secondcpu = firstcpu;
3141 currrcvcpu = secondcpu;
3142 }
3143 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3144 irq_handler_t handler;
3145 void *arg;
3146 u64 val;
3147 int lsb, reg, sh;
3148
3149 dd->cspec->msix_entries[msixnum].
3150 name[sizeof(dd->cspec->msix_entries[msixnum].name) - 1]
3151 = '\0';
3152 if (i < ARRAY_SIZE(irq_table)) {
3153 if (irq_table[i].port) {
3154 /* skip if for a non-configured port */
3155 if (irq_table[i].port > dd->num_pports)
3156 continue;
3157 arg = dd->pport + irq_table[i].port - 1;
3158 } else
3159 arg = dd;
3160 lsb = irq_table[i].lsb;
3161 handler = irq_table[i].handler;
3162 snprintf(dd->cspec->msix_entries[msixnum].name,
3163 sizeof(dd->cspec->msix_entries[msixnum].name)
3164 - 1,
3165 QIB_DRV_NAME "%d%s", dd->unit,
3166 irq_table[i].name);
3167 } else {
3168 unsigned ctxt;
3169
3170 ctxt = i - ARRAY_SIZE(irq_table);
3171 /* per krcvq context receive interrupt */
3172 arg = dd->rcd[ctxt];
3173 if (!arg)
3174 continue;
3175 if (qib_krcvq01_no_msi && ctxt < 2)
3176 continue;
3177 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3178 handler = qib_7322pintr;
3179 snprintf(dd->cspec->msix_entries[msixnum].name,
3180 sizeof(dd->cspec->msix_entries[msixnum].name)
3181 - 1,
3182 QIB_DRV_NAME "%d (kctx)", dd->unit);
3183 }
3184 ret = request_irq(
3185 dd->cspec->msix_entries[msixnum].msix.vector,
3186 handler, 0, dd->cspec->msix_entries[msixnum].name,
3187 arg);
3188 if (ret) {
3189 /*
3190 * Shouldn't happen since the enable said we could
3191 * have as many as we are trying to setup here.
3192 */
3193 qib_dev_err(dd, "Couldn't setup MSIx "
3194 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3195 dd->cspec->msix_entries[msixnum].msix.vector,
3196 ret);
3197 qib_7322_nomsix(dd);
3198 goto try_intx;
3199 }
3200 dd->cspec->msix_entries[msixnum].arg = arg;
3201 if (lsb >= 0) {
3202 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3203 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3204 SYM_LSB(IntRedirect0, vec1);
3205 mask &= ~(1ULL << lsb);
3206 redirect[reg] |= ((u64) msixnum) << sh;
3207 }
3208 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3209 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3210 if (firstcpu < nr_cpu_ids &&
3211 zalloc_cpumask_var(
3212 &dd->cspec->msix_entries[msixnum].mask,
3213 GFP_KERNEL)) {
3214 if (handler == qib_7322pintr) {
3215 cpumask_set_cpu(currrcvcpu,
3216 dd->cspec->msix_entries[msixnum].mask);
3217 currrcvcpu = cpumask_next(currrcvcpu,
3218 local_mask);
3219 if (currrcvcpu >= nr_cpu_ids)
3220 currrcvcpu = secondcpu;
3221 } else {
3222 cpumask_set_cpu(firstcpu,
3223 dd->cspec->msix_entries[msixnum].mask);
3224 }
3225 irq_set_affinity_hint(
3226 dd->cspec->msix_entries[msixnum].msix.vector,
3227 dd->cspec->msix_entries[msixnum].mask);
3228 }
3229 msixnum++;
3230 }
3231 /* Initialize the vector mapping */
3232 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3233 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3234 dd->cspec->main_int_mask = mask;
3235 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3236 (unsigned long)dd);
3237 bail:;
3238 }
3239
3240 /**
3241 * qib_7322_boardname - fill in the board name and note features
3242 * @dd: the qlogic_ib device
3243 *
3244 * info will be based on the board revision register
3245 */
3246 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3247 {
3248 /* Will need enumeration of board-types here */
3249 char *n;
3250 u32 boardid, namelen;
3251 unsigned features = DUAL_PORT_CAP;
3252
3253 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3254
3255 switch (boardid) {
3256 case 0:
3257 n = "InfiniPath_QLE7342_Emulation";
3258 break;
3259 case 1:
3260 n = "InfiniPath_QLE7340";
3261 dd->flags |= QIB_HAS_QSFP;
3262 features = PORT_SPD_CAP;
3263 break;
3264 case 2:
3265 n = "InfiniPath_QLE7342";
3266 dd->flags |= QIB_HAS_QSFP;
3267 break;
3268 case 3:
3269 n = "InfiniPath_QMI7342";
3270 break;
3271 case 4:
3272 n = "InfiniPath_Unsupported7342";
3273 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3274 features = 0;
3275 break;
3276 case BOARD_QMH7342:
3277 n = "InfiniPath_QMH7342";
3278 features = 0x24;
3279 break;
3280 case BOARD_QME7342:
3281 n = "InfiniPath_QME7342";
3282 break;
3283 case 8:
3284 n = "InfiniPath_QME7362";
3285 dd->flags |= QIB_HAS_QSFP;
3286 break;
3287 case 15:
3288 n = "InfiniPath_QLE7342_TEST";
3289 dd->flags |= QIB_HAS_QSFP;
3290 break;
3291 default:
3292 n = "InfiniPath_QLE73xy_UNKNOWN";
3293 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3294 break;
3295 }
3296 dd->board_atten = 1; /* index into txdds_Xdr */
3297
3298 namelen = strlen(n) + 1;
3299 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3300 if (!dd->boardname)
3301 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3302 else
3303 snprintf(dd->boardname, namelen, "%s", n);
3304
3305 snprintf(dd->boardversion, sizeof(dd->boardversion),
3306 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3307 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3308 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3309 dd->majrev, dd->minrev,
3310 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3311
3312 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3313 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3314 " by module parameter\n", dd->unit);
3315 features &= PORT_SPD_CAP;
3316 }
3317
3318 return features;
3319 }
3320
3321 /*
3322 * This routine sleeps, so it can only be called from user context, not
3323 * from interrupt context.
3324 */
3325 static int qib_do_7322_reset(struct qib_devdata *dd)
3326 {
3327 u64 val;
3328 u64 *msix_vecsave;
3329 int i, msix_entries, ret = 1;
3330 u16 cmdval;
3331 u8 int_line, clinesz;
3332 unsigned long flags;
3333
3334 /* Use dev_err so it shows up in logs, etc. */
3335 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3336
3337 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3338
3339 msix_entries = dd->cspec->num_msix_entries;
3340
3341 /* no interrupts till re-initted */
3342 qib_7322_set_intr_state(dd, 0);
3343
3344 if (msix_entries) {
3345 qib_7322_nomsix(dd);
3346 /* can be up to 512 bytes, too big for stack */
3347 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3348 sizeof(u64), GFP_KERNEL);
3349 if (!msix_vecsave)
3350 qib_dev_err(dd, "No mem to save MSIx data\n");
3351 } else
3352 msix_vecsave = NULL;
3353
3354 /*
3355 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3356 * info that is set up by the BIOS, so we have to save and restore
3357 * it ourselves. There is some risk something could change it,
3358 * after we save it, but since we have disabled the MSIx, it
3359 * shouldn't be touched...
3360 */
3361 for (i = 0; i < msix_entries; i++) {
3362 u64 vecaddr, vecdata;
3363 vecaddr = qib_read_kreg64(dd, 2 * i +
3364 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3365 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3366 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3367 if (msix_vecsave) {
3368 msix_vecsave[2 * i] = vecaddr;
3369 /* save it without the masked bit set */
3370 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3371 }
3372 }
3373
3374 dd->pport->cpspec->ibdeltainprog = 0;
3375 dd->pport->cpspec->ibsymdelta = 0;
3376 dd->pport->cpspec->iblnkerrdelta = 0;
3377 dd->pport->cpspec->ibmalfdelta = 0;
3378 dd->int_counter = 0; /* so we check interrupts work again */
3379
3380 /*
3381 * Keep chip from being accessed until we are ready. Use
3382 * writeq() directly, to allow the write even though QIB_PRESENT
3383 * isn't set.
3384 */
3385 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3386 dd->flags |= QIB_DOING_RESET;
3387 val = dd->control | QLOGIC_IB_C_RESET;
3388 writeq(val, &dd->kregbase[kr_control]);
3389
3390 for (i = 1; i <= 5; i++) {
3391 /*
3392 * Allow MBIST, etc. to complete; longer on each retry.
3393 * We sometimes get machine checks from bus timeout if no
3394 * response, so for now, make it *really* long.
3395 */
3396 msleep(1000 + (1 + i) * 3000);
3397
3398 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3399
3400 /*
3401 * Use readq directly, so we don't need to mark it as PRESENT
3402 * until we get a successful indication that all is well.
3403 */
3404 val = readq(&dd->kregbase[kr_revision]);
3405 if (val == dd->revision)
3406 break;
3407 if (i == 5) {
3408 qib_dev_err(dd, "Failed to initialize after reset, "
3409 "unusable\n");
3410 ret = 0;
3411 goto bail;
3412 }
3413 }
3414
3415 dd->flags |= QIB_PRESENT; /* it's back */
3416
3417 if (msix_entries) {
3418 /* restore the MSIx vector address and data if saved above */
3419 for (i = 0; i < msix_entries; i++) {
3420 dd->cspec->msix_entries[i].msix.entry = i;
3421 if (!msix_vecsave || !msix_vecsave[2 * i])
3422 continue;
3423 qib_write_kreg(dd, 2 * i +
3424 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3425 msix_vecsave[2 * i]);
3426 qib_write_kreg(dd, 1 + 2 * i +
3427 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3428 msix_vecsave[1 + 2 * i]);
3429 }
3430 }
3431
3432 /* initialize the remaining registers. */
3433 for (i = 0; i < dd->num_pports; ++i)
3434 write_7322_init_portregs(&dd->pport[i]);
3435 write_7322_initregs(dd);
3436
3437 if (qib_pcie_params(dd, dd->lbus_width,
3438 &dd->cspec->num_msix_entries,
3439 dd->cspec->msix_entries))
3440 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3441 "continuing anyway\n");
3442
3443 qib_setup_7322_interrupt(dd, 1);
3444
3445 for (i = 0; i < dd->num_pports; ++i) {
3446 struct qib_pportdata *ppd = &dd->pport[i];
3447
3448 spin_lock_irqsave(&ppd->lflags_lock, flags);
3449 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3450 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3451 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3452 }
3453
3454 bail:
3455 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3456 kfree(msix_vecsave);
3457 return ret;
3458 }
3459
3460 /**
3461 * qib_7322_put_tid - write a TID to the chip
3462 * @dd: the qlogic_ib device
3463 * @tidptr: pointer to the expected TID (in chip) to update
3464 * @tidtype: 0 for eager, 1 for expected
3465 * @pa: physical address of in memory buffer; tidinvalid if freeing
3466 */
3467 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3468 u32 type, unsigned long pa)
3469 {
3470 if (!(dd->flags & QIB_PRESENT))
3471 return;
3472 if (pa != dd->tidinvalid) {
3473 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3474
3475 /* paranoia checks */
3476 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3477 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3478 pa);
3479 return;
3480 }
3481 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3482 qib_dev_err(dd, "Physical page address 0x%lx "
3483 "larger than supported\n", pa);
3484 return;
3485 }
3486
3487 if (type == RCVHQ_RCV_TYPE_EAGER)
3488 chippa |= dd->tidtemplate;
3489 else /* for now, always full 4KB page */
3490 chippa |= IBA7322_TID_SZ_4K;
3491 pa = chippa;
3492 }
3493 writeq(pa, tidptr);
3494 mmiowb();
3495 }
3496
3497 /**
3498 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3499 * @dd: the qlogic_ib device
3500 * @ctxt: the ctxt
3501 *
3502 * clear all TID entries for a ctxt, expected and eager.
3503 * Used from qib_close().
3504 */
3505 static void qib_7322_clear_tids(struct qib_devdata *dd,
3506 struct qib_ctxtdata *rcd)
3507 {
3508 u64 __iomem *tidbase;
3509 unsigned long tidinv;
3510 u32 ctxt;
3511 int i;
3512
3513 if (!dd->kregbase || !rcd)
3514 return;
3515
3516 ctxt = rcd->ctxt;
3517
3518 tidinv = dd->tidinvalid;
3519 tidbase = (u64 __iomem *)
3520 ((char __iomem *) dd->kregbase +
3521 dd->rcvtidbase +
3522 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3523
3524 for (i = 0; i < dd->rcvtidcnt; i++)
3525 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3526 tidinv);
3527
3528 tidbase = (u64 __iomem *)
3529 ((char __iomem *) dd->kregbase +
3530 dd->rcvegrbase +
3531 rcd->rcvegr_tid_base * sizeof(*tidbase));
3532
3533 for (i = 0; i < rcd->rcvegrcnt; i++)
3534 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3535 tidinv);
3536 }
3537
3538 /**
3539 * qib_7322_tidtemplate - setup constants for TID updates
3540 * @dd: the qlogic_ib device
3541 *
3542 * We setup stuff that we use a lot, to avoid calculating each time
3543 */
3544 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3545 {
3546 /*
3547 * For now, we always allocate 4KB buffers (at init) so we can
3548 * receive max size packets. We may want a module parameter to
3549 * specify 2KB or 4KB and/or make it per port instead of per device
3550 * for those who want to reduce memory footprint. Note that the
3551 * rcvhdrentsize size must be large enough to hold the largest
3552 * IB header (currently 96 bytes) that we expect to handle (plus of
3553 * course the 2 dwords of RHF).
3554 */
3555 if (dd->rcvegrbufsize == 2048)
3556 dd->tidtemplate = IBA7322_TID_SZ_2K;
3557 else if (dd->rcvegrbufsize == 4096)
3558 dd->tidtemplate = IBA7322_TID_SZ_4K;
3559 dd->tidinvalid = 0;
3560 }
3561
3562 /**
3563 * qib_init_7322_get_base_info - set chip-specific flags for user code
3564 * @rcd: the qlogic_ib ctxt
3565 * @kbase: qib_base_info pointer
3566 *
3567 * We set the PCIE flag because the lower bandwidth on PCIe vs
3568 * HyperTransport can affect some user packet algorithims.
3569 */
3570
3571 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3572 struct qib_base_info *kinfo)
3573 {
3574 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3575 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3576 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3577 if (rcd->dd->cspec->r1)
3578 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3579 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3580 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3581
3582 return 0;
3583 }
3584
3585 static struct qib_message_header *
3586 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3587 {
3588 u32 offset = qib_hdrget_offset(rhf_addr);
3589
3590 return (struct qib_message_header *)
3591 (rhf_addr - dd->rhf_offset + offset);
3592 }
3593
3594 /*
3595 * Configure number of contexts.
3596 */
3597 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3598 {
3599 unsigned long flags;
3600 u32 nchipctxts;
3601
3602 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3603 dd->cspec->numctxts = nchipctxts;
3604 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3605 dd->first_user_ctxt = NUM_IB_PORTS +
3606 (qib_n_krcv_queues - 1) * dd->num_pports;
3607 if (dd->first_user_ctxt > nchipctxts)
3608 dd->first_user_ctxt = nchipctxts;
3609 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3610 } else {
3611 dd->first_user_ctxt = NUM_IB_PORTS;
3612 dd->n_krcv_queues = 1;
3613 }
3614
3615 if (!qib_cfgctxts) {
3616 int nctxts = dd->first_user_ctxt + num_online_cpus();
3617
3618 if (nctxts <= 6)
3619 dd->ctxtcnt = 6;
3620 else if (nctxts <= 10)
3621 dd->ctxtcnt = 10;
3622 else if (nctxts <= nchipctxts)
3623 dd->ctxtcnt = nchipctxts;
3624 } else if (qib_cfgctxts < dd->num_pports)
3625 dd->ctxtcnt = dd->num_pports;
3626 else if (qib_cfgctxts <= nchipctxts)
3627 dd->ctxtcnt = qib_cfgctxts;
3628 if (!dd->ctxtcnt) /* none of the above, set to max */
3629 dd->ctxtcnt = nchipctxts;
3630
3631 /*
3632 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3633 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3634 * Lock to be paranoid about later motion, etc.
3635 */
3636 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3637 if (dd->ctxtcnt > 10)
3638 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3639 else if (dd->ctxtcnt > 6)
3640 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3641 /* else configure for default 6 receive ctxts */
3642
3643 /* The XRC opcode is 5. */
3644 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3645
3646 /*
3647 * RcvCtrl *must* be written here so that the
3648 * chip understands how to change rcvegrcnt below.
3649 */
3650 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3651 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3652
3653 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3654 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3655 if (qib_rcvhdrcnt)
3656 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3657 else
3658 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt,
3659 dd->num_pports > 1 ? 1024U : 2048U);
3660 }
3661
3662 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3663 {
3664
3665 int lsb, ret = 0;
3666 u64 maskr; /* right-justified mask */
3667
3668 switch (which) {
3669
3670 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3671 ret = ppd->link_width_enabled;
3672 goto done;
3673
3674 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3675 ret = ppd->link_width_active;
3676 goto done;
3677
3678 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3679 ret = ppd->link_speed_enabled;
3680 goto done;
3681
3682 case QIB_IB_CFG_SPD: /* Get current Link spd */
3683 ret = ppd->link_speed_active;
3684 goto done;
3685
3686 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3687 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3688 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3689 break;
3690
3691 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3692 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3693 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3694 break;
3695
3696 case QIB_IB_CFG_LINKLATENCY:
3697 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3698 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3699 goto done;
3700
3701 case QIB_IB_CFG_OP_VLS:
3702 ret = ppd->vls_operational;
3703 goto done;
3704
3705 case QIB_IB_CFG_VL_HIGH_CAP:
3706 ret = 16;
3707 goto done;
3708
3709 case QIB_IB_CFG_VL_LOW_CAP:
3710 ret = 16;
3711 goto done;
3712
3713 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3714 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3715 OverrunThreshold);
3716 goto done;
3717
3718 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3719 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3720 PhyerrThreshold);
3721 goto done;
3722
3723 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3724 /* will only take effect when the link state changes */
3725 ret = (ppd->cpspec->ibcctrl_a &
3726 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3727 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3728 goto done;
3729
3730 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3731 lsb = IBA7322_IBC_HRTBT_LSB;
3732 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3733 break;
3734
3735 case QIB_IB_CFG_PMA_TICKS:
3736 /*
3737 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3738 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3739 */
3740 if (ppd->link_speed_active == QIB_IB_QDR)
3741 ret = 3;
3742 else if (ppd->link_speed_active == QIB_IB_DDR)
3743 ret = 1;
3744 else
3745 ret = 0;
3746 goto done;
3747
3748 default:
3749 ret = -EINVAL;
3750 goto done;
3751 }
3752 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3753 done:
3754 return ret;
3755 }
3756
3757 /*
3758 * Below again cribbed liberally from older version. Do not lean
3759 * heavily on it.
3760 */
3761 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3762 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3763 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3764
3765 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3766 {
3767 struct qib_devdata *dd = ppd->dd;
3768 u64 maskr; /* right-justified mask */
3769 int lsb, ret = 0;
3770 u16 lcmd, licmd;
3771 unsigned long flags;
3772
3773 switch (which) {
3774 case QIB_IB_CFG_LIDLMC:
3775 /*
3776 * Set LID and LMC. Combined to avoid possible hazard
3777 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3778 */
3779 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3780 maskr = IBA7322_IBC_DLIDLMC_MASK;
3781 /*
3782 * For header-checking, the SLID in the packet will
3783 * be masked with SendIBSLMCMask, and compared
3784 * with SendIBSLIDAssignMask. Make sure we do not
3785 * set any bits not covered by the mask, or we get
3786 * false-positives.
3787 */
3788 qib_write_kreg_port(ppd, krp_sendslid,
3789 val & (val >> 16) & SendIBSLIDAssignMask);
3790 qib_write_kreg_port(ppd, krp_sendslidmask,
3791 (val >> 16) & SendIBSLMCMask);
3792 break;
3793
3794 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3795 ppd->link_width_enabled = val;
3796 /* convert IB value to chip register value */
3797 if (val == IB_WIDTH_1X)
3798 val = 0;
3799 else if (val == IB_WIDTH_4X)
3800 val = 1;
3801 else
3802 val = 3;
3803 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3804 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3805 break;
3806
3807 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3808 /*
3809 * As with width, only write the actual register if the
3810 * link is currently down, otherwise takes effect on next
3811 * link change. Since setting is being explicitly requested
3812 * (via MAD or sysfs), clear autoneg failure status if speed
3813 * autoneg is enabled.
3814 */
3815 ppd->link_speed_enabled = val;
3816 val <<= IBA7322_IBC_SPEED_LSB;
3817 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3818 IBA7322_IBC_MAX_SPEED_MASK;
3819 if (val & (val - 1)) {
3820 /* Muliple speeds enabled */
3821 val |= IBA7322_IBC_IBTA_1_2_MASK |
3822 IBA7322_IBC_MAX_SPEED_MASK;
3823 spin_lock_irqsave(&ppd->lflags_lock, flags);
3824 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3825 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3826 } else if (val & IBA7322_IBC_SPEED_QDR)
3827 val |= IBA7322_IBC_IBTA_1_2_MASK;
3828 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3829 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3830 break;
3831
3832 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3833 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3834 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3835 break;
3836
3837 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3838 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3839 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3840 break;
3841
3842 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3843 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3844 OverrunThreshold);
3845 if (maskr != val) {
3846 ppd->cpspec->ibcctrl_a &=
3847 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3848 ppd->cpspec->ibcctrl_a |= (u64) val <<
3849 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3850 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3851 ppd->cpspec->ibcctrl_a);
3852 qib_write_kreg(dd, kr_scratch, 0ULL);
3853 }
3854 goto bail;
3855
3856 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3857 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3858 PhyerrThreshold);
3859 if (maskr != val) {
3860 ppd->cpspec->ibcctrl_a &=
3861 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3862 ppd->cpspec->ibcctrl_a |= (u64) val <<
3863 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3864 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3865 ppd->cpspec->ibcctrl_a);
3866 qib_write_kreg(dd, kr_scratch, 0ULL);
3867 }
3868 goto bail;
3869
3870 case QIB_IB_CFG_PKEYS: /* update pkeys */
3871 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3872 ((u64) ppd->pkeys[2] << 32) |
3873 ((u64) ppd->pkeys[3] << 48);
3874 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3875 goto bail;
3876
3877 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3878 /* will only take effect when the link state changes */
3879 if (val == IB_LINKINITCMD_POLL)
3880 ppd->cpspec->ibcctrl_a &=
3881 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3882 else /* SLEEP */
3883 ppd->cpspec->ibcctrl_a |=
3884 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3885 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3886 qib_write_kreg(dd, kr_scratch, 0ULL);
3887 goto bail;
3888
3889 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3890 /*
3891 * Update our housekeeping variables, and set IBC max
3892 * size, same as init code; max IBC is max we allow in
3893 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3894 * Set even if it's unchanged, print debug message only
3895 * on changes.
3896 */
3897 val = (ppd->ibmaxlen >> 2) + 1;
3898 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3899 ppd->cpspec->ibcctrl_a |= (u64)val <<
3900 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3901 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3902 ppd->cpspec->ibcctrl_a);
3903 qib_write_kreg(dd, kr_scratch, 0ULL);
3904 goto bail;
3905
3906 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3907 switch (val & 0xffff0000) {
3908 case IB_LINKCMD_DOWN:
3909 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3910 ppd->cpspec->ibmalfusesnap = 1;
3911 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3912 crp_errlink);
3913 if (!ppd->cpspec->ibdeltainprog &&
3914 qib_compat_ddr_negotiate) {
3915 ppd->cpspec->ibdeltainprog = 1;
3916 ppd->cpspec->ibsymsnap =
3917 read_7322_creg32_port(ppd,
3918 crp_ibsymbolerr);
3919 ppd->cpspec->iblnkerrsnap =
3920 read_7322_creg32_port(ppd,
3921 crp_iblinkerrrecov);
3922 }
3923 break;
3924
3925 case IB_LINKCMD_ARMED:
3926 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3927 if (ppd->cpspec->ibmalfusesnap) {
3928 ppd->cpspec->ibmalfusesnap = 0;
3929 ppd->cpspec->ibmalfdelta +=
3930 read_7322_creg32_port(ppd,
3931 crp_errlink) -
3932 ppd->cpspec->ibmalfsnap;
3933 }
3934 break;
3935
3936 case IB_LINKCMD_ACTIVE:
3937 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3938 break;
3939
3940 default:
3941 ret = -EINVAL;
3942 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3943 goto bail;
3944 }
3945 switch (val & 0xffff) {
3946 case IB_LINKINITCMD_NOP:
3947 licmd = 0;
3948 break;
3949
3950 case IB_LINKINITCMD_POLL:
3951 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3952 break;
3953
3954 case IB_LINKINITCMD_SLEEP:
3955 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3956 break;
3957
3958 case IB_LINKINITCMD_DISABLE:
3959 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3960 ppd->cpspec->chase_end = 0;
3961 /*
3962 * stop state chase counter and timer, if running.
3963 * wait forpending timer, but don't clear .data (ppd)!
3964 */
3965 if (ppd->cpspec->chase_timer.expires) {
3966 del_timer_sync(&ppd->cpspec->chase_timer);
3967 ppd->cpspec->chase_timer.expires = 0;
3968 }
3969 break;
3970
3971 default:
3972 ret = -EINVAL;
3973 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3974 val & 0xffff);
3975 goto bail;
3976 }
3977 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3978 goto bail;
3979
3980 case QIB_IB_CFG_OP_VLS:
3981 if (ppd->vls_operational != val) {
3982 ppd->vls_operational = val;
3983 set_vls(ppd);
3984 }
3985 goto bail;
3986
3987 case QIB_IB_CFG_VL_HIGH_LIMIT:
3988 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3989 goto bail;
3990
3991 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3992 if (val > 3) {
3993 ret = -EINVAL;
3994 goto bail;
3995 }
3996 lsb = IBA7322_IBC_HRTBT_LSB;
3997 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3998 break;
3999
4000 case QIB_IB_CFG_PORT:
4001 /* val is the port number of the switch we are connected to. */
4002 if (ppd->dd->cspec->r1) {
4003 cancel_delayed_work(&ppd->cpspec->ipg_work);
4004 ppd->cpspec->ipg_tries = 0;
4005 }
4006 goto bail;
4007
4008 default:
4009 ret = -EINVAL;
4010 goto bail;
4011 }
4012 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
4013 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4014 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4015 qib_write_kreg(dd, kr_scratch, 0);
4016 bail:
4017 return ret;
4018 }
4019
4020 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
4021 {
4022 int ret = 0;
4023 u64 val, ctrlb;
4024
4025 /* only IBC loopback, may add serdes and xgxs loopbacks later */
4026 if (!strncmp(what, "ibc", 3)) {
4027 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
4028 Loopback);
4029 val = 0; /* disable heart beat, so link will come up */
4030 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
4031 ppd->dd->unit, ppd->port);
4032 } else if (!strncmp(what, "off", 3)) {
4033 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
4034 Loopback);
4035 /* enable heart beat again */
4036 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
4037 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
4038 "(normal)\n", ppd->dd->unit, ppd->port);
4039 } else
4040 ret = -EINVAL;
4041 if (!ret) {
4042 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4043 ppd->cpspec->ibcctrl_a);
4044 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
4045 << IBA7322_IBC_HRTBT_LSB);
4046 ppd->cpspec->ibcctrl_b = ctrlb | val;
4047 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4048 ppd->cpspec->ibcctrl_b);
4049 qib_write_kreg(ppd->dd, kr_scratch, 0);
4050 }
4051 return ret;
4052 }
4053
4054 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4055 struct ib_vl_weight_elem *vl)
4056 {
4057 unsigned i;
4058
4059 for (i = 0; i < 16; i++, regno++, vl++) {
4060 u32 val = qib_read_kreg_port(ppd, regno);
4061
4062 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4063 SYM_RMASK(LowPriority0_0, VirtualLane);
4064 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4065 SYM_RMASK(LowPriority0_0, Weight);
4066 }
4067 }
4068
4069 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4070 struct ib_vl_weight_elem *vl)
4071 {
4072 unsigned i;
4073
4074 for (i = 0; i < 16; i++, regno++, vl++) {
4075 u64 val;
4076
4077 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4078 SYM_LSB(LowPriority0_0, VirtualLane)) |
4079 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4080 SYM_LSB(LowPriority0_0, Weight));
4081 qib_write_kreg_port(ppd, regno, val);
4082 }
4083 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4084 struct qib_devdata *dd = ppd->dd;
4085 unsigned long flags;
4086
4087 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4088 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4089 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4090 qib_write_kreg(dd, kr_scratch, 0);
4091 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4092 }
4093 }
4094
4095 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4096 {
4097 switch (which) {
4098 case QIB_IB_TBL_VL_HIGH_ARB:
4099 get_vl_weights(ppd, krp_highprio_0, t);
4100 break;
4101
4102 case QIB_IB_TBL_VL_LOW_ARB:
4103 get_vl_weights(ppd, krp_lowprio_0, t);
4104 break;
4105
4106 default:
4107 return -EINVAL;
4108 }
4109 return 0;
4110 }
4111
4112 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4113 {
4114 switch (which) {
4115 case QIB_IB_TBL_VL_HIGH_ARB:
4116 set_vl_weights(ppd, krp_highprio_0, t);
4117 break;
4118
4119 case QIB_IB_TBL_VL_LOW_ARB:
4120 set_vl_weights(ppd, krp_lowprio_0, t);
4121 break;
4122
4123 default:
4124 return -EINVAL;
4125 }
4126 return 0;
4127 }
4128
4129 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4130 u32 updegr, u32 egrhd, u32 npkts)
4131 {
4132 /*
4133 * Need to write timeout register before updating rcvhdrhead to ensure
4134 * that the timer is enabled on reception of a packet.
4135 */
4136 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4137 adjust_rcv_timeout(rcd, npkts);
4138 if (updegr)
4139 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4140 mmiowb();
4141 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4142 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4143 mmiowb();
4144 }
4145
4146 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4147 {
4148 u32 head, tail;
4149
4150 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4151 if (rcd->rcvhdrtail_kvaddr)
4152 tail = qib_get_rcvhdrtail(rcd);
4153 else
4154 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4155 return head == tail;
4156 }
4157
4158 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4159 QIB_RCVCTRL_CTXT_DIS | \
4160 QIB_RCVCTRL_TIDFLOW_ENB | \
4161 QIB_RCVCTRL_TIDFLOW_DIS | \
4162 QIB_RCVCTRL_TAILUPD_ENB | \
4163 QIB_RCVCTRL_TAILUPD_DIS | \
4164 QIB_RCVCTRL_INTRAVAIL_ENB | \
4165 QIB_RCVCTRL_INTRAVAIL_DIS | \
4166 QIB_RCVCTRL_BP_ENB | \
4167 QIB_RCVCTRL_BP_DIS)
4168
4169 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4170 QIB_RCVCTRL_CTXT_DIS | \
4171 QIB_RCVCTRL_PKEY_DIS | \
4172 QIB_RCVCTRL_PKEY_ENB)
4173
4174 /*
4175 * Modify the RCVCTRL register in chip-specific way. This
4176 * is a function because bit positions and (future) register
4177 * location is chip-specifc, but the needed operations are
4178 * generic. <op> is a bit-mask because we often want to
4179 * do multiple modifications.
4180 */
4181 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4182 int ctxt)
4183 {
4184 struct qib_devdata *dd = ppd->dd;
4185 struct qib_ctxtdata *rcd;
4186 u64 mask, val;
4187 unsigned long flags;
4188
4189 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4190
4191 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4192 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4193 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4194 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4195 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4196 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4197 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4198 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4199 if (op & QIB_RCVCTRL_PKEY_ENB)
4200 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4201 if (op & QIB_RCVCTRL_PKEY_DIS)
4202 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4203 if (ctxt < 0) {
4204 mask = (1ULL << dd->ctxtcnt) - 1;
4205 rcd = NULL;
4206 } else {
4207 mask = (1ULL << ctxt);
4208 rcd = dd->rcd[ctxt];
4209 }
4210 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4211 ppd->p_rcvctrl |=
4212 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4213 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4214 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4215 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4216 }
4217 /* Write these registers before the context is enabled. */
4218 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4219 rcd->rcvhdrqtailaddr_phys);
4220 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4221 rcd->rcvhdrq_phys);
4222 rcd->seq_cnt = 1;
4223 }
4224 if (op & QIB_RCVCTRL_CTXT_DIS)
4225 ppd->p_rcvctrl &=
4226 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4227 if (op & QIB_RCVCTRL_BP_ENB)
4228 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4229 if (op & QIB_RCVCTRL_BP_DIS)
4230 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4231 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4232 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4233 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4234 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4235 /*
4236 * Decide which registers to write depending on the ops enabled.
4237 * Special case is "flush" (no bits set at all)
4238 * which needs to write both.
4239 */
4240 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4241 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4242 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4243 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4244 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4245 /*
4246 * Init the context registers also; if we were
4247 * disabled, tail and head should both be zero
4248 * already from the enable, but since we don't
4249 * know, we have to do it explicitly.
4250 */
4251 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4252 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4253
4254 /* be sure enabling write seen; hd/tl should be 0 */
4255 (void) qib_read_kreg32(dd, kr_scratch);
4256 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4257 dd->rcd[ctxt]->head = val;
4258 /* If kctxt, interrupt on next receive. */
4259 if (ctxt < dd->first_user_ctxt)
4260 val |= dd->rhdrhead_intr_off;
4261 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4262 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4263 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4264 /* arm rcv interrupt */
4265 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4266 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4267 }
4268 if (op & QIB_RCVCTRL_CTXT_DIS) {
4269 unsigned f;
4270
4271 /* Now that the context is disabled, clear these registers. */
4272 if (ctxt >= 0) {
4273 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4274 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4275 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4276 qib_write_ureg(dd, ur_rcvflowtable + f,
4277 TIDFLOW_ERRBITS, ctxt);
4278 } else {
4279 unsigned i;
4280
4281 for (i = 0; i < dd->cfgctxts; i++) {
4282 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4283 i, 0);
4284 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4285 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4286 qib_write_ureg(dd, ur_rcvflowtable + f,
4287 TIDFLOW_ERRBITS, i);
4288 }
4289 }
4290 }
4291 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4292 }
4293
4294 /*
4295 * Modify the SENDCTRL register in chip-specific way. This
4296 * is a function where there are multiple such registers with
4297 * slightly different layouts.
4298 * The chip doesn't allow back-to-back sendctrl writes, so write
4299 * the scratch register after writing sendctrl.
4300 *
4301 * Which register is written depends on the operation.
4302 * Most operate on the common register, while
4303 * SEND_ENB and SEND_DIS operate on the per-port ones.
4304 * SEND_ENB is included in common because it can change SPCL_TRIG
4305 */
4306 #define SENDCTRL_COMMON_MODS (\
4307 QIB_SENDCTRL_CLEAR | \
4308 QIB_SENDCTRL_AVAIL_DIS | \
4309 QIB_SENDCTRL_AVAIL_ENB | \
4310 QIB_SENDCTRL_AVAIL_BLIP | \
4311 QIB_SENDCTRL_DISARM | \
4312 QIB_SENDCTRL_DISARM_ALL | \
4313 QIB_SENDCTRL_SEND_ENB)
4314
4315 #define SENDCTRL_PORT_MODS (\
4316 QIB_SENDCTRL_CLEAR | \
4317 QIB_SENDCTRL_SEND_ENB | \
4318 QIB_SENDCTRL_SEND_DIS | \
4319 QIB_SENDCTRL_FLUSH)
4320
4321 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4322 {
4323 struct qib_devdata *dd = ppd->dd;
4324 u64 tmp_dd_sendctrl;
4325 unsigned long flags;
4326
4327 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4328
4329 /* First the dd ones that are "sticky", saved in shadow */
4330 if (op & QIB_SENDCTRL_CLEAR)
4331 dd->sendctrl = 0;
4332 if (op & QIB_SENDCTRL_AVAIL_DIS)
4333 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4334 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4335 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4336 if (dd->flags & QIB_USE_SPCL_TRIG)
4337 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4338 }
4339
4340 /* Then the ppd ones that are "sticky", saved in shadow */
4341 if (op & QIB_SENDCTRL_SEND_DIS)
4342 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4343 else if (op & QIB_SENDCTRL_SEND_ENB)
4344 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4345
4346 if (op & QIB_SENDCTRL_DISARM_ALL) {
4347 u32 i, last;
4348
4349 tmp_dd_sendctrl = dd->sendctrl;
4350 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4351 /*
4352 * Disarm any buffers that are not yet launched,
4353 * disabling updates until done.
4354 */
4355 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4356 for (i = 0; i < last; i++) {
4357 qib_write_kreg(dd, kr_sendctrl,
4358 tmp_dd_sendctrl |
4359 SYM_MASK(SendCtrl, Disarm) | i);
4360 qib_write_kreg(dd, kr_scratch, 0);
4361 }
4362 }
4363
4364 if (op & QIB_SENDCTRL_FLUSH) {
4365 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4366
4367 /*
4368 * Now drain all the fifos. The Abort bit should never be
4369 * needed, so for now, at least, we don't use it.
4370 */
4371 tmp_ppd_sendctrl |=
4372 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4373 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4374 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4375 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4376 qib_write_kreg(dd, kr_scratch, 0);
4377 }
4378
4379 tmp_dd_sendctrl = dd->sendctrl;
4380
4381 if (op & QIB_SENDCTRL_DISARM)
4382 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4383 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4384 SYM_LSB(SendCtrl, DisarmSendBuf));
4385 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4386 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4387 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4388
4389 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4390 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4391 qib_write_kreg(dd, kr_scratch, 0);
4392 }
4393
4394 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4395 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4396 qib_write_kreg(dd, kr_scratch, 0);
4397 }
4398
4399 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4400 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4401 qib_write_kreg(dd, kr_scratch, 0);
4402 }
4403
4404 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4405
4406 if (op & QIB_SENDCTRL_FLUSH) {
4407 u32 v;
4408 /*
4409 * ensure writes have hit chip, then do a few
4410 * more reads, to allow DMA of pioavail registers
4411 * to occur, so in-memory copy is in sync with
4412 * the chip. Not always safe to sleep.
4413 */
4414 v = qib_read_kreg32(dd, kr_scratch);
4415 qib_write_kreg(dd, kr_scratch, v);
4416 v = qib_read_kreg32(dd, kr_scratch);
4417 qib_write_kreg(dd, kr_scratch, v);
4418 qib_read_kreg32(dd, kr_scratch);
4419 }
4420 }
4421
4422 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4423 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4424 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4425
4426 /**
4427 * qib_portcntr_7322 - read a per-port chip counter
4428 * @ppd: the qlogic_ib pport
4429 * @creg: the counter to read (not a chip offset)
4430 */
4431 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4432 {
4433 struct qib_devdata *dd = ppd->dd;
4434 u64 ret = 0ULL;
4435 u16 creg;
4436 /* 0xffff for unimplemented or synthesized counters */
4437 static const u32 xlator[] = {
4438 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4439 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4440 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4441 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4442 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4443 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4444 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4445 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4446 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4447 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4448 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4449 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4450 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4451 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4452 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4453 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4454 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4455 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4456 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4457 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4458 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4459 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4460 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4461 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4462 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4463 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4464 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4465 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4466 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4467 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4468 /*
4469 * the next 3 aren't really counters, but were implemented
4470 * as counters in older chips, so still get accessed as
4471 * though they were counters from this code.
4472 */
4473 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4474 [QIBPORTCNTR_PSSTART] = krp_psstart,
4475 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4476 /* pseudo-counter, summed for all ports */
4477 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4478 };
4479
4480 if (reg >= ARRAY_SIZE(xlator)) {
4481 qib_devinfo(ppd->dd->pcidev,
4482 "Unimplemented portcounter %u\n", reg);
4483 goto done;
4484 }
4485 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4486
4487 /* handle non-counters and special cases first */
4488 if (reg == QIBPORTCNTR_KHDROVFL) {
4489 int i;
4490
4491 /* sum over all kernel contexts (skip if mini_init) */
4492 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4493 struct qib_ctxtdata *rcd = dd->rcd[i];
4494
4495 if (!rcd || rcd->ppd != ppd)
4496 continue;
4497 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4498 }
4499 goto done;
4500 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4501 /*
4502 * Used as part of the synthesis of port_rcv_errors
4503 * in the verbs code for IBTA counters. Not needed for 7322,
4504 * because all the errors are already counted by other cntrs.
4505 */
4506 goto done;
4507 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4508 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4509 /* were counters in older chips, now per-port kernel regs */
4510 ret = qib_read_kreg_port(ppd, creg);
4511 goto done;
4512 }
4513
4514 /*
4515 * Only fast increment counters are 64 bits; use 32 bit reads to
4516 * avoid two independent reads when on Opteron.
4517 */
4518 if (xlator[reg] & _PORT_64BIT_FLAG)
4519 ret = read_7322_creg_port(ppd, creg);
4520 else
4521 ret = read_7322_creg32_port(ppd, creg);
4522 if (creg == crp_ibsymbolerr) {
4523 if (ppd->cpspec->ibdeltainprog)
4524 ret -= ret - ppd->cpspec->ibsymsnap;
4525 ret -= ppd->cpspec->ibsymdelta;
4526 } else if (creg == crp_iblinkerrrecov) {
4527 if (ppd->cpspec->ibdeltainprog)
4528 ret -= ret - ppd->cpspec->iblnkerrsnap;
4529 ret -= ppd->cpspec->iblnkerrdelta;
4530 } else if (creg == crp_errlink)
4531 ret -= ppd->cpspec->ibmalfdelta;
4532 else if (creg == crp_iblinkdown)
4533 ret += ppd->cpspec->iblnkdowndelta;
4534 done:
4535 return ret;
4536 }
4537
4538 /*
4539 * Device counter names (not port-specific), one line per stat,
4540 * single string. Used by utilities like ipathstats to print the stats
4541 * in a way which works for different versions of drivers, without changing
4542 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4543 * display by utility.
4544 * Non-error counters are first.
4545 * Start of "error" conters is indicated by a leading "E " on the first
4546 * "error" counter, and doesn't count in label length.
4547 * The EgrOvfl list needs to be last so we truncate them at the configured
4548 * context count for the device.
4549 * cntr7322indices contains the corresponding register indices.
4550 */
4551 static const char cntr7322names[] =
4552 "Interrupts\n"
4553 "HostBusStall\n"
4554 "E RxTIDFull\n"
4555 "RxTIDInvalid\n"
4556 "RxTIDFloDrop\n" /* 7322 only */
4557 "Ctxt0EgrOvfl\n"
4558 "Ctxt1EgrOvfl\n"
4559 "Ctxt2EgrOvfl\n"
4560 "Ctxt3EgrOvfl\n"
4561 "Ctxt4EgrOvfl\n"
4562 "Ctxt5EgrOvfl\n"
4563 "Ctxt6EgrOvfl\n"
4564 "Ctxt7EgrOvfl\n"
4565 "Ctxt8EgrOvfl\n"
4566 "Ctxt9EgrOvfl\n"
4567 "Ctx10EgrOvfl\n"
4568 "Ctx11EgrOvfl\n"
4569 "Ctx12EgrOvfl\n"
4570 "Ctx13EgrOvfl\n"
4571 "Ctx14EgrOvfl\n"
4572 "Ctx15EgrOvfl\n"
4573 "Ctx16EgrOvfl\n"
4574 "Ctx17EgrOvfl\n"
4575 ;
4576
4577 static const u32 cntr7322indices[] = {
4578 cr_lbint | _PORT_64BIT_FLAG,
4579 cr_lbstall | _PORT_64BIT_FLAG,
4580 cr_tidfull,
4581 cr_tidinvalid,
4582 cr_rxtidflowdrop,
4583 cr_base_egrovfl + 0,
4584 cr_base_egrovfl + 1,
4585 cr_base_egrovfl + 2,
4586 cr_base_egrovfl + 3,
4587 cr_base_egrovfl + 4,
4588 cr_base_egrovfl + 5,
4589 cr_base_egrovfl + 6,
4590 cr_base_egrovfl + 7,
4591 cr_base_egrovfl + 8,
4592 cr_base_egrovfl + 9,
4593 cr_base_egrovfl + 10,
4594 cr_base_egrovfl + 11,
4595 cr_base_egrovfl + 12,
4596 cr_base_egrovfl + 13,
4597 cr_base_egrovfl + 14,
4598 cr_base_egrovfl + 15,
4599 cr_base_egrovfl + 16,
4600 cr_base_egrovfl + 17,
4601 };
4602
4603 /*
4604 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4605 * portcntr7322indices is somewhat complicated by some registers needing
4606 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4607 */
4608 static const char portcntr7322names[] =
4609 "TxPkt\n"
4610 "TxFlowPkt\n"
4611 "TxWords\n"
4612 "RxPkt\n"
4613 "RxFlowPkt\n"
4614 "RxWords\n"
4615 "TxFlowStall\n"
4616 "TxDmaDesc\n" /* 7220 and 7322-only */
4617 "E RxDlidFltr\n" /* 7220 and 7322-only */
4618 "IBStatusChng\n"
4619 "IBLinkDown\n"
4620 "IBLnkRecov\n"
4621 "IBRxLinkErr\n"
4622 "IBSymbolErr\n"
4623 "RxLLIErr\n"
4624 "RxBadFormat\n"
4625 "RxBadLen\n"
4626 "RxBufOvrfl\n"
4627 "RxEBP\n"
4628 "RxFlowCtlErr\n"
4629 "RxICRCerr\n"
4630 "RxLPCRCerr\n"
4631 "RxVCRCerr\n"
4632 "RxInvalLen\n"
4633 "RxInvalPKey\n"
4634 "RxPktDropped\n"
4635 "TxBadLength\n"
4636 "TxDropped\n"
4637 "TxInvalLen\n"
4638 "TxUnderrun\n"
4639 "TxUnsupVL\n"
4640 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4641 "RxVL15Drop\n"
4642 "RxVlErr\n"
4643 "XcessBufOvfl\n"
4644 "RxQPBadCtxt\n" /* 7322-only from here down */
4645 "TXBadHeader\n"
4646 ;
4647
4648 static const u32 portcntr7322indices[] = {
4649 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4650 crp_pktsendflow,
4651 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4652 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4653 crp_pktrcvflowctrl,
4654 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4655 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4656 crp_txsdmadesc | _PORT_64BIT_FLAG,
4657 crp_rxdlidfltr,
4658 crp_ibstatuschange,
4659 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4660 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4661 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4662 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4663 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4664 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4665 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4666 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4667 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4668 crp_rcvflowctrlviol,
4669 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4670 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4671 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4672 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4673 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4674 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4675 crp_txminmaxlenerr,
4676 crp_txdroppedpkt,
4677 crp_txlenerr,
4678 crp_txunderrun,
4679 crp_txunsupvl,
4680 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4681 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4682 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4683 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4684 crp_rxqpinvalidctxt,
4685 crp_txhdrerr,
4686 };
4687
4688 /* do all the setup to make the counter reads efficient later */
4689 static void init_7322_cntrnames(struct qib_devdata *dd)
4690 {
4691 int i, j = 0;
4692 char *s;
4693
4694 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4695 i++) {
4696 /* we always have at least one counter before the egrovfl */
4697 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4698 j = 1;
4699 s = strchr(s + 1, '\n');
4700 if (s && j)
4701 j++;
4702 }
4703 dd->cspec->ncntrs = i;
4704 if (!s)
4705 /* full list; size is without terminating null */
4706 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4707 else
4708 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4709 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4710 * sizeof(u64), GFP_KERNEL);
4711 if (!dd->cspec->cntrs)
4712 qib_dev_err(dd, "Failed allocation for counters\n");
4713
4714 for (i = 0, s = (char *)portcntr7322names; s; i++)
4715 s = strchr(s + 1, '\n');
4716 dd->cspec->nportcntrs = i - 1;
4717 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4718 for (i = 0; i < dd->num_pports; ++i) {
4719 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4720 * sizeof(u64), GFP_KERNEL);
4721 if (!dd->pport[i].cpspec->portcntrs)
4722 qib_dev_err(dd, "Failed allocation for"
4723 " portcounters\n");
4724 }
4725 }
4726
4727 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4728 u64 **cntrp)
4729 {
4730 u32 ret;
4731
4732 if (namep) {
4733 ret = dd->cspec->cntrnamelen;
4734 if (pos >= ret)
4735 ret = 0; /* final read after getting everything */
4736 else
4737 *namep = (char *) cntr7322names;
4738 } else {
4739 u64 *cntr = dd->cspec->cntrs;
4740 int i;
4741
4742 ret = dd->cspec->ncntrs * sizeof(u64);
4743 if (!cntr || pos >= ret) {
4744 /* everything read, or couldn't get memory */
4745 ret = 0;
4746 goto done;
4747 }
4748 *cntrp = cntr;
4749 for (i = 0; i < dd->cspec->ncntrs; i++)
4750 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4751 *cntr++ = read_7322_creg(dd,
4752 cntr7322indices[i] &
4753 _PORT_CNTR_IDXMASK);
4754 else
4755 *cntr++ = read_7322_creg32(dd,
4756 cntr7322indices[i]);
4757 }
4758 done:
4759 return ret;
4760 }
4761
4762 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4763 char **namep, u64 **cntrp)
4764 {
4765 u32 ret;
4766
4767 if (namep) {
4768 ret = dd->cspec->portcntrnamelen;
4769 if (pos >= ret)
4770 ret = 0; /* final read after getting everything */
4771 else
4772 *namep = (char *)portcntr7322names;
4773 } else {
4774 struct qib_pportdata *ppd = &dd->pport[port];
4775 u64 *cntr = ppd->cpspec->portcntrs;
4776 int i;
4777
4778 ret = dd->cspec->nportcntrs * sizeof(u64);
4779 if (!cntr || pos >= ret) {
4780 /* everything read, or couldn't get memory */
4781 ret = 0;
4782 goto done;
4783 }
4784 *cntrp = cntr;
4785 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4786 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4787 *cntr++ = qib_portcntr_7322(ppd,
4788 portcntr7322indices[i] &
4789 _PORT_CNTR_IDXMASK);
4790 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4791 *cntr++ = read_7322_creg_port(ppd,
4792 portcntr7322indices[i] &
4793 _PORT_CNTR_IDXMASK);
4794 else
4795 *cntr++ = read_7322_creg32_port(ppd,
4796 portcntr7322indices[i]);
4797 }
4798 }
4799 done:
4800 return ret;
4801 }
4802
4803 /**
4804 * qib_get_7322_faststats - get word counters from chip before they overflow
4805 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4806 *
4807 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4808 * real purpose of this function is to maintain the notion of
4809 * "active time", which in turn is only logged into the eeprom,
4810 * which we don;t have, yet, for 7322-based boards.
4811 *
4812 * called from add_timer
4813 */
4814 static void qib_get_7322_faststats(unsigned long opaque)
4815 {
4816 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4817 struct qib_pportdata *ppd;
4818 unsigned long flags;
4819 u64 traffic_wds;
4820 int pidx;
4821
4822 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4823 ppd = dd->pport + pidx;
4824
4825 /*
4826 * If port isn't enabled or not operational ports, or
4827 * diags is running (can cause memory diags to fail)
4828 * skip this port this time.
4829 */
4830 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4831 || dd->diag_client)
4832 continue;
4833
4834 /*
4835 * Maintain an activity timer, based on traffic
4836 * exceeding a threshold, so we need to check the word-counts
4837 * even if they are 64-bit.
4838 */
4839 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4840 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4841 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4842 traffic_wds -= ppd->dd->traffic_wds;
4843 ppd->dd->traffic_wds += traffic_wds;
4844 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4845 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4846 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4847 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4848 QIB_IB_QDR) &&
4849 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4850 QIBL_LINKACTIVE)) &&
4851 ppd->cpspec->qdr_dfe_time &&
4852 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) {
4853 ppd->cpspec->qdr_dfe_on = 0;
4854
4855 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4856 ppd->dd->cspec->r1 ?
4857 QDR_STATIC_ADAPT_INIT_R1 :
4858 QDR_STATIC_ADAPT_INIT);
4859 force_h1(ppd);
4860 }
4861 }
4862 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4863 }
4864
4865 /*
4866 * If we were using MSIx, try to fallback to INTx.
4867 */
4868 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4869 {
4870 if (!dd->cspec->num_msix_entries)
4871 return 0; /* already using INTx */
4872
4873 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4874 " trying INTx interrupts\n");
4875 qib_7322_nomsix(dd);
4876 qib_enable_intx(dd->pcidev);
4877 qib_setup_7322_interrupt(dd, 0);
4878 return 1;
4879 }
4880
4881 /*
4882 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4883 * than resetting the IBC or external link state, and useful in some
4884 * cases to cause some retraining. To do this right, we reset IBC
4885 * as well, then return to previous state (which may be still in reset)
4886 * NOTE: some callers of this "know" this writes the current value
4887 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4888 * check all callers.
4889 */
4890 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4891 {
4892 u64 val;
4893 struct qib_devdata *dd = ppd->dd;
4894 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4895 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4896 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4897
4898 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4899 qib_write_kreg(dd, kr_hwerrmask,
4900 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4901 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4902 ppd->cpspec->ibcctrl_a &
4903 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4904
4905 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4906 qib_read_kreg32(dd, kr_scratch);
4907 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4908 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4909 qib_write_kreg(dd, kr_scratch, 0ULL);
4910 qib_write_kreg(dd, kr_hwerrclear,
4911 SYM_MASK(HwErrClear, statusValidNoEopClear));
4912 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4913 }
4914
4915 /*
4916 * This code for non-IBTA-compliant IB speed negotiation is only known to
4917 * work for the SDR to DDR transition, and only between an HCA and a switch
4918 * with recent firmware. It is based on observed heuristics, rather than
4919 * actual knowledge of the non-compliant speed negotiation.
4920 * It has a number of hard-coded fields, since the hope is to rewrite this
4921 * when a spec is available on how the negoation is intended to work.
4922 */
4923 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4924 u32 dcnt, u32 *data)
4925 {
4926 int i;
4927 u64 pbc;
4928 u32 __iomem *piobuf;
4929 u32 pnum, control, len;
4930 struct qib_devdata *dd = ppd->dd;
4931
4932 i = 0;
4933 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4934 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4935 pbc = ((u64) control << 32) | len;
4936 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4937 if (i++ > 15)
4938 return;
4939 udelay(2);
4940 }
4941 /* disable header check on this packet, since it can't be valid */
4942 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4943 writeq(pbc, piobuf);
4944 qib_flush_wc();
4945 qib_pio_copy(piobuf + 2, hdr, 7);
4946 qib_pio_copy(piobuf + 9, data, dcnt);
4947 if (dd->flags & QIB_USE_SPCL_TRIG) {
4948 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4949
4950 qib_flush_wc();
4951 __raw_writel(0xaebecede, piobuf + spcl_off);
4952 }
4953 qib_flush_wc();
4954 qib_sendbuf_done(dd, pnum);
4955 /* and re-enable hdr check */
4956 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4957 }
4958
4959 /*
4960 * _start packet gets sent twice at start, _done gets sent twice at end
4961 */
4962 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4963 {
4964 struct qib_devdata *dd = ppd->dd;
4965 static u32 swapped;
4966 u32 dw, i, hcnt, dcnt, *data;
4967 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4968 static u32 madpayload_start[0x40] = {
4969 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4970 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4971 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4972 };
4973 static u32 madpayload_done[0x40] = {
4974 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4975 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4976 0x40000001, 0x1388, 0x15e, /* rest 0's */
4977 };
4978
4979 dcnt = ARRAY_SIZE(madpayload_start);
4980 hcnt = ARRAY_SIZE(hdr);
4981 if (!swapped) {
4982 /* for maintainability, do it at runtime */
4983 for (i = 0; i < hcnt; i++) {
4984 dw = (__force u32) cpu_to_be32(hdr[i]);
4985 hdr[i] = dw;
4986 }
4987 for (i = 0; i < dcnt; i++) {
4988 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4989 madpayload_start[i] = dw;
4990 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4991 madpayload_done[i] = dw;
4992 }
4993 swapped = 1;
4994 }
4995
4996 data = which ? madpayload_done : madpayload_start;
4997
4998 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4999 qib_read_kreg64(dd, kr_scratch);
5000 udelay(2);
5001 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5002 qib_read_kreg64(dd, kr_scratch);
5003 udelay(2);
5004 }
5005
5006 /*
5007 * Do the absolute minimum to cause an IB speed change, and make it
5008 * ready, but don't actually trigger the change. The caller will
5009 * do that when ready (if link is in Polling training state, it will
5010 * happen immediately, otherwise when link next goes down)
5011 *
5012 * This routine should only be used as part of the DDR autonegotation
5013 * code for devices that are not compliant with IB 1.2 (or code that
5014 * fixes things up for same).
5015 *
5016 * When link has gone down, and autoneg enabled, or autoneg has
5017 * failed and we give up until next time we set both speeds, and
5018 * then we want IBTA enabled as well as "use max enabled speed.
5019 */
5020 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
5021 {
5022 u64 newctrlb;
5023 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
5024 IBA7322_IBC_IBTA_1_2_MASK |
5025 IBA7322_IBC_MAX_SPEED_MASK);
5026
5027 if (speed & (speed - 1)) /* multiple speeds */
5028 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
5029 IBA7322_IBC_IBTA_1_2_MASK |
5030 IBA7322_IBC_MAX_SPEED_MASK;
5031 else
5032 newctrlb |= speed == QIB_IB_QDR ?
5033 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
5034 ((speed == QIB_IB_DDR ?
5035 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
5036
5037 if (newctrlb == ppd->cpspec->ibcctrl_b)
5038 return;
5039
5040 ppd->cpspec->ibcctrl_b = newctrlb;
5041 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
5042 qib_write_kreg(ppd->dd, kr_scratch, 0);
5043 }
5044
5045 /*
5046 * This routine is only used when we are not talking to another
5047 * IB 1.2-compliant device that we think can do DDR.
5048 * (This includes all existing switch chips as of Oct 2007.)
5049 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5050 */
5051 static void try_7322_autoneg(struct qib_pportdata *ppd)
5052 {
5053 unsigned long flags;
5054
5055 spin_lock_irqsave(&ppd->lflags_lock, flags);
5056 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5057 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5058 qib_autoneg_7322_send(ppd, 0);
5059 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5060 qib_7322_mini_pcs_reset(ppd);
5061 /* 2 msec is minimum length of a poll cycle */
5062 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5063 msecs_to_jiffies(2));
5064 }
5065
5066 /*
5067 * Handle the empirically determined mechanism for auto-negotiation
5068 * of DDR speed with switches.
5069 */
5070 static void autoneg_7322_work(struct work_struct *work)
5071 {
5072 struct qib_pportdata *ppd;
5073 struct qib_devdata *dd;
5074 u64 startms;
5075 u32 i;
5076 unsigned long flags;
5077
5078 ppd = container_of(work, struct qib_chippport_specific,
5079 autoneg_work.work)->ppd;
5080 dd = ppd->dd;
5081
5082 startms = jiffies_to_msecs(jiffies);
5083
5084 /*
5085 * Busy wait for this first part, it should be at most a
5086 * few hundred usec, since we scheduled ourselves for 2msec.
5087 */
5088 for (i = 0; i < 25; i++) {
5089 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5090 == IB_7322_LT_STATE_POLLQUIET) {
5091 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5092 break;
5093 }
5094 udelay(100);
5095 }
5096
5097 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5098 goto done; /* we got there early or told to stop */
5099
5100 /* we expect this to timeout */
5101 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5102 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5103 msecs_to_jiffies(90)))
5104 goto done;
5105 qib_7322_mini_pcs_reset(ppd);
5106
5107 /* we expect this to timeout */
5108 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5109 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5110 msecs_to_jiffies(1700)))
5111 goto done;
5112 qib_7322_mini_pcs_reset(ppd);
5113
5114 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5115
5116 /*
5117 * Wait up to 250 msec for link to train and get to INIT at DDR;
5118 * this should terminate early.
5119 */
5120 wait_event_timeout(ppd->cpspec->autoneg_wait,
5121 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5122 msecs_to_jiffies(250));
5123 done:
5124 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5125 spin_lock_irqsave(&ppd->lflags_lock, flags);
5126 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5127 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5128 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5129 ppd->cpspec->autoneg_tries = 0;
5130 }
5131 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5132 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5133 }
5134 }
5135
5136 /*
5137 * This routine is used to request IPG set in the QLogic switch.
5138 * Only called if r1.
5139 */
5140 static void try_7322_ipg(struct qib_pportdata *ppd)
5141 {
5142 struct qib_ibport *ibp = &ppd->ibport_data;
5143 struct ib_mad_send_buf *send_buf;
5144 struct ib_mad_agent *agent;
5145 struct ib_smp *smp;
5146 unsigned delay;
5147 int ret;
5148
5149 agent = ibp->send_agent;
5150 if (!agent)
5151 goto retry;
5152
5153 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5154 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5155 if (IS_ERR(send_buf))
5156 goto retry;
5157
5158 if (!ibp->smi_ah) {
5159 struct ib_ah_attr attr;
5160 struct ib_ah *ah;
5161
5162 memset(&attr, 0, sizeof attr);
5163 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5164 attr.port_num = ppd->port;
5165 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5166 if (IS_ERR(ah))
5167 ret = -EINVAL;
5168 else {
5169 send_buf->ah = ah;
5170 ibp->smi_ah = to_iah(ah);
5171 ret = 0;
5172 }
5173 } else {
5174 send_buf->ah = &ibp->smi_ah->ibah;
5175 ret = 0;
5176 }
5177
5178 smp = send_buf->mad;
5179 smp->base_version = IB_MGMT_BASE_VERSION;
5180 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5181 smp->class_version = 1;
5182 smp->method = IB_MGMT_METHOD_SEND;
5183 smp->hop_cnt = 1;
5184 smp->attr_id = QIB_VENDOR_IPG;
5185 smp->attr_mod = 0;
5186
5187 if (!ret)
5188 ret = ib_post_send_mad(send_buf, NULL);
5189 if (ret)
5190 ib_free_send_mad(send_buf);
5191 retry:
5192 delay = 2 << ppd->cpspec->ipg_tries;
5193 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5194 msecs_to_jiffies(delay));
5195 }
5196
5197 /*
5198 * Timeout handler for setting IPG.
5199 * Only called if r1.
5200 */
5201 static void ipg_7322_work(struct work_struct *work)
5202 {
5203 struct qib_pportdata *ppd;
5204
5205 ppd = container_of(work, struct qib_chippport_specific,
5206 ipg_work.work)->ppd;
5207 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5208 && ++ppd->cpspec->ipg_tries <= 10)
5209 try_7322_ipg(ppd);
5210 }
5211
5212 static u32 qib_7322_iblink_state(u64 ibcs)
5213 {
5214 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5215
5216 switch (state) {
5217 case IB_7322_L_STATE_INIT:
5218 state = IB_PORT_INIT;
5219 break;
5220 case IB_7322_L_STATE_ARM:
5221 state = IB_PORT_ARMED;
5222 break;
5223 case IB_7322_L_STATE_ACTIVE:
5224 /* fall through */
5225 case IB_7322_L_STATE_ACT_DEFER:
5226 state = IB_PORT_ACTIVE;
5227 break;
5228 default: /* fall through */
5229 case IB_7322_L_STATE_DOWN:
5230 state = IB_PORT_DOWN;
5231 break;
5232 }
5233 return state;
5234 }
5235
5236 /* returns the IBTA port state, rather than the IBC link training state */
5237 static u8 qib_7322_phys_portstate(u64 ibcs)
5238 {
5239 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5240 return qib_7322_physportstate[state];
5241 }
5242
5243 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5244 {
5245 int ret = 0, symadj = 0;
5246 unsigned long flags;
5247 int mult;
5248
5249 spin_lock_irqsave(&ppd->lflags_lock, flags);
5250 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5251 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5252
5253 /* Update our picture of width and speed from chip */
5254 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5255 ppd->link_speed_active = QIB_IB_QDR;
5256 mult = 4;
5257 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5258 ppd->link_speed_active = QIB_IB_DDR;
5259 mult = 2;
5260 } else {
5261 ppd->link_speed_active = QIB_IB_SDR;
5262 mult = 1;
5263 }
5264 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5265 ppd->link_width_active = IB_WIDTH_4X;
5266 mult *= 4;
5267 } else
5268 ppd->link_width_active = IB_WIDTH_1X;
5269 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5270
5271 if (!ibup) {
5272 u64 clr;
5273
5274 /* Link went down. */
5275 /* do IPG MAD again after linkdown, even if last time failed */
5276 ppd->cpspec->ipg_tries = 0;
5277 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5278 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5279 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5280 if (clr)
5281 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5282 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5283 QIBL_IB_AUTONEG_INPROG)))
5284 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5285 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5286 struct qib_qsfp_data *qd =
5287 &ppd->cpspec->qsfp_data;
5288 /* unlock the Tx settings, speed may change */
5289 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5290 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5291 reset_tx_deemphasis_override));
5292 qib_cancel_sends(ppd);
5293 /* on link down, ensure sane pcs state */
5294 qib_7322_mini_pcs_reset(ppd);
5295 /* schedule the qsfp refresh which should turn the link
5296 off */
5297 if (ppd->dd->flags & QIB_HAS_QSFP) {
5298 qd->t_insert = jiffies;
5299 queue_work(ib_wq, &qd->work);
5300 }
5301 spin_lock_irqsave(&ppd->sdma_lock, flags);
5302 if (__qib_sdma_running(ppd))
5303 __qib_sdma_process_event(ppd,
5304 qib_sdma_event_e70_go_idle);
5305 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5306 }
5307 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5308 if (clr == ppd->cpspec->iblnkdownsnap)
5309 ppd->cpspec->iblnkdowndelta++;
5310 } else {
5311 if (qib_compat_ddr_negotiate &&
5312 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5313 QIBL_IB_AUTONEG_INPROG)) &&
5314 ppd->link_speed_active == QIB_IB_SDR &&
5315 (ppd->link_speed_enabled & QIB_IB_DDR)
5316 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5317 /* we are SDR, and auto-negotiation enabled */
5318 ++ppd->cpspec->autoneg_tries;
5319 if (!ppd->cpspec->ibdeltainprog) {
5320 ppd->cpspec->ibdeltainprog = 1;
5321 ppd->cpspec->ibsymdelta +=
5322 read_7322_creg32_port(ppd,
5323 crp_ibsymbolerr) -
5324 ppd->cpspec->ibsymsnap;
5325 ppd->cpspec->iblnkerrdelta +=
5326 read_7322_creg32_port(ppd,
5327 crp_iblinkerrrecov) -
5328 ppd->cpspec->iblnkerrsnap;
5329 }
5330 try_7322_autoneg(ppd);
5331 ret = 1; /* no other IB status change processing */
5332 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5333 ppd->link_speed_active == QIB_IB_SDR) {
5334 qib_autoneg_7322_send(ppd, 1);
5335 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5336 qib_7322_mini_pcs_reset(ppd);
5337 udelay(2);
5338 ret = 1; /* no other IB status change processing */
5339 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5340 (ppd->link_speed_active & QIB_IB_DDR)) {
5341 spin_lock_irqsave(&ppd->lflags_lock, flags);
5342 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5343 QIBL_IB_AUTONEG_FAILED);
5344 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5345 ppd->cpspec->autoneg_tries = 0;
5346 /* re-enable SDR, for next link down */
5347 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5348 wake_up(&ppd->cpspec->autoneg_wait);
5349 symadj = 1;
5350 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5351 /*
5352 * Clear autoneg failure flag, and do setup
5353 * so we'll try next time link goes down and
5354 * back to INIT (possibly connected to a
5355 * different device).
5356 */
5357 spin_lock_irqsave(&ppd->lflags_lock, flags);
5358 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5359 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5360 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5361 symadj = 1;
5362 }
5363 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5364 symadj = 1;
5365 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5366 try_7322_ipg(ppd);
5367 if (!ppd->cpspec->recovery_init)
5368 setup_7322_link_recovery(ppd, 0);
5369 ppd->cpspec->qdr_dfe_time = jiffies +
5370 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5371 }
5372 ppd->cpspec->ibmalfusesnap = 0;
5373 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5374 crp_errlink);
5375 }
5376 if (symadj) {
5377 ppd->cpspec->iblnkdownsnap =
5378 read_7322_creg32_port(ppd, crp_iblinkdown);
5379 if (ppd->cpspec->ibdeltainprog) {
5380 ppd->cpspec->ibdeltainprog = 0;
5381 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5382 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5383 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5384 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5385 }
5386 } else if (!ibup && qib_compat_ddr_negotiate &&
5387 !ppd->cpspec->ibdeltainprog &&
5388 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5389 ppd->cpspec->ibdeltainprog = 1;
5390 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5391 crp_ibsymbolerr);
5392 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5393 crp_iblinkerrrecov);
5394 }
5395
5396 if (!ret)
5397 qib_setup_7322_setextled(ppd, ibup);
5398 return ret;
5399 }
5400
5401 /*
5402 * Does read/modify/write to appropriate registers to
5403 * set output and direction bits selected by mask.
5404 * these are in their canonical postions (e.g. lsb of
5405 * dir will end up in D48 of extctrl on existing chips).
5406 * returns contents of GP Inputs.
5407 */
5408 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5409 {
5410 u64 read_val, new_out;
5411 unsigned long flags;
5412
5413 if (mask) {
5414 /* some bits being written, lock access to GPIO */
5415 dir &= mask;
5416 out &= mask;
5417 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5418 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5419 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5420 new_out = (dd->cspec->gpio_out & ~mask) | out;
5421
5422 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5423 qib_write_kreg(dd, kr_gpio_out, new_out);
5424 dd->cspec->gpio_out = new_out;
5425 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5426 }
5427 /*
5428 * It is unlikely that a read at this time would get valid
5429 * data on a pin whose direction line was set in the same
5430 * call to this function. We include the read here because
5431 * that allows us to potentially combine a change on one pin with
5432 * a read on another, and because the old code did something like
5433 * this.
5434 */
5435 read_val = qib_read_kreg64(dd, kr_extstatus);
5436 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5437 }
5438
5439 /* Enable writes to config EEPROM, if possible. Returns previous state */
5440 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5441 {
5442 int prev_wen;
5443 u32 mask;
5444
5445 mask = 1 << QIB_EEPROM_WEN_NUM;
5446 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5447 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5448
5449 return prev_wen & 1;
5450 }
5451
5452 /*
5453 * Read fundamental info we need to use the chip. These are
5454 * the registers that describe chip capabilities, and are
5455 * saved in shadow registers.
5456 */
5457 static void get_7322_chip_params(struct qib_devdata *dd)
5458 {
5459 u64 val;
5460 u32 piobufs;
5461 int mtu;
5462
5463 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5464
5465 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5466
5467 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5468 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5469 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5470 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5471 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5472
5473 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5474 dd->piobcnt2k = val & ~0U;
5475 dd->piobcnt4k = val >> 32;
5476 val = qib_read_kreg64(dd, kr_sendpiosize);
5477 dd->piosize2k = val & ~0U;
5478 dd->piosize4k = val >> 32;
5479
5480 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5481 if (mtu == -1)
5482 mtu = QIB_DEFAULT_MTU;
5483 dd->pport[0].ibmtu = (u32)mtu;
5484 dd->pport[1].ibmtu = (u32)mtu;
5485
5486 /* these may be adjusted in init_chip_wc_pat() */
5487 dd->pio2kbase = (u32 __iomem *)
5488 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5489 dd->pio4kbase = (u32 __iomem *)
5490 ((char __iomem *) dd->kregbase +
5491 (dd->piobufbase >> 32));
5492 /*
5493 * 4K buffers take 2 pages; we use roundup just to be
5494 * paranoid; we calculate it once here, rather than on
5495 * ever buf allocate
5496 */
5497 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5498
5499 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5500
5501 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5502 (sizeof(u64) * BITS_PER_BYTE / 2);
5503 }
5504
5505 /*
5506 * The chip base addresses in cspec and cpspec have to be set
5507 * after possible init_chip_wc_pat(), rather than in
5508 * get_7322_chip_params(), so split out as separate function
5509 */
5510 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5511 {
5512 u32 cregbase;
5513 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5514
5515 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5516 (char __iomem *)dd->kregbase);
5517
5518 dd->egrtidbase = (u64 __iomem *)
5519 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5520
5521 /* port registers are defined as relative to base of chip */
5522 dd->pport[0].cpspec->kpregbase =
5523 (u64 __iomem *)((char __iomem *)dd->kregbase);
5524 dd->pport[1].cpspec->kpregbase =
5525 (u64 __iomem *)(dd->palign +
5526 (char __iomem *)dd->kregbase);
5527 dd->pport[0].cpspec->cpregbase =
5528 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5529 kr_counterregbase) + (char __iomem *)dd->kregbase);
5530 dd->pport[1].cpspec->cpregbase =
5531 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5532 kr_counterregbase) + (char __iomem *)dd->kregbase);
5533 }
5534
5535 /*
5536 * This is a fairly special-purpose observer, so we only support
5537 * the port-specific parts of SendCtrl
5538 */
5539
5540 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5541 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5542 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5543 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5544 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5545 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5546 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5547
5548 static int sendctrl_hook(struct qib_devdata *dd,
5549 const struct diag_observer *op, u32 offs,
5550 u64 *data, u64 mask, int only_32)
5551 {
5552 unsigned long flags;
5553 unsigned idx;
5554 unsigned pidx;
5555 struct qib_pportdata *ppd = NULL;
5556 u64 local_data, all_bits;
5557
5558 /*
5559 * The fixed correspondence between Physical ports and pports is
5560 * severed. We need to hunt for the ppd that corresponds
5561 * to the offset we got. And we have to do that without admitting
5562 * we know the stride, apparently.
5563 */
5564 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5565 u64 __iomem *psptr;
5566 u32 psoffs;
5567
5568 ppd = dd->pport + pidx;
5569 if (!ppd->cpspec->kpregbase)
5570 continue;
5571
5572 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5573 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5574 if (psoffs == offs)
5575 break;
5576 }
5577
5578 /* If pport is not being managed by driver, just avoid shadows. */
5579 if (pidx >= dd->num_pports)
5580 ppd = NULL;
5581
5582 /* In any case, "idx" is flat index in kreg space */
5583 idx = offs / sizeof(u64);
5584
5585 all_bits = ~0ULL;
5586 if (only_32)
5587 all_bits >>= 32;
5588
5589 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5590 if (!ppd || (mask & all_bits) != all_bits) {
5591 /*
5592 * At least some mask bits are zero, so we need
5593 * to read. The judgement call is whether from
5594 * reg or shadow. First-cut: read reg, and complain
5595 * if any bits which should be shadowed are different
5596 * from their shadowed value.
5597 */
5598 if (only_32)
5599 local_data = (u64)qib_read_kreg32(dd, idx);
5600 else
5601 local_data = qib_read_kreg64(dd, idx);
5602 *data = (local_data & ~mask) | (*data & mask);
5603 }
5604 if (mask) {
5605 /*
5606 * At least some mask bits are one, so we need
5607 * to write, but only shadow some bits.
5608 */
5609 u64 sval, tval; /* Shadowed, transient */
5610
5611 /*
5612 * New shadow val is bits we don't want to touch,
5613 * ORed with bits we do, that are intended for shadow.
5614 */
5615 if (ppd) {
5616 sval = ppd->p_sendctrl & ~mask;
5617 sval |= *data & SENDCTRL_SHADOWED & mask;
5618 ppd->p_sendctrl = sval;
5619 } else
5620 sval = *data & SENDCTRL_SHADOWED & mask;
5621 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5622 qib_write_kreg(dd, idx, tval);
5623 qib_write_kreg(dd, kr_scratch, 0Ull);
5624 }
5625 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5626 return only_32 ? 4 : 8;
5627 }
5628
5629 static const struct diag_observer sendctrl_0_observer = {
5630 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5631 KREG_IDX(SendCtrl_0) * sizeof(u64)
5632 };
5633
5634 static const struct diag_observer sendctrl_1_observer = {
5635 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5636 KREG_IDX(SendCtrl_1) * sizeof(u64)
5637 };
5638
5639 static ushort sdma_fetch_prio = 8;
5640 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5641 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5642
5643 /* Besides logging QSFP events, we set appropriate TxDDS values */
5644 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5645
5646 static void qsfp_7322_event(struct work_struct *work)
5647 {
5648 struct qib_qsfp_data *qd;
5649 struct qib_pportdata *ppd;
5650 unsigned long pwrup;
5651 unsigned long flags;
5652 int ret;
5653 u32 le2;
5654
5655 qd = container_of(work, struct qib_qsfp_data, work);
5656 ppd = qd->ppd;
5657 pwrup = qd->t_insert +
5658 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC);
5659
5660 /* Delay for 20 msecs to allow ModPrs resistor to setup */
5661 mdelay(QSFP_MODPRS_LAG_MSEC);
5662
5663 if (!qib_qsfp_mod_present(ppd)) {
5664 ppd->cpspec->qsfp_data.modpresent = 0;
5665 /* Set the physical link to disabled */
5666 qib_set_ib_7322_lstate(ppd, 0,
5667 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
5668 spin_lock_irqsave(&ppd->lflags_lock, flags);
5669 ppd->lflags &= ~QIBL_LINKV;
5670 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5671 } else {
5672 /*
5673 * Some QSFP's not only do not respond until the full power-up
5674 * time, but may behave badly if we try. So hold off responding
5675 * to insertion.
5676 */
5677 while (1) {
5678 if (time_is_before_jiffies(pwrup))
5679 break;
5680 msleep(20);
5681 }
5682
5683 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5684
5685 /*
5686 * Need to change LE2 back to defaults if we couldn't
5687 * read the cable type (to handle cable swaps), so do this
5688 * even on failure to read cable information. We don't
5689 * get here for QME, so IS_QME check not needed here.
5690 */
5691 if (!ret && !ppd->dd->cspec->r1) {
5692 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
5693 le2 = LE2_QME;
5694 else if (qd->cache.atten[1] >= qib_long_atten &&
5695 QSFP_IS_CU(qd->cache.tech))
5696 le2 = LE2_5m;
5697 else
5698 le2 = LE2_DEFAULT;
5699 } else
5700 le2 = LE2_DEFAULT;
5701 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5702 /*
5703 * We always change parameteters, since we can choose
5704 * values for cables without eeproms, and the cable may have
5705 * changed from a cable with full or partial eeprom content
5706 * to one with partial or no content.
5707 */
5708 init_txdds_table(ppd, 0);
5709 /* The physical link is being re-enabled only when the
5710 * previous state was DISABLED and the VALID bit is not
5711 * set. This should only happen when the cable has been
5712 * physically pulled. */
5713 if (!ppd->cpspec->qsfp_data.modpresent &&
5714 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) {
5715 ppd->cpspec->qsfp_data.modpresent = 1;
5716 qib_set_ib_7322_lstate(ppd, 0,
5717 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5718 spin_lock_irqsave(&ppd->lflags_lock, flags);
5719 ppd->lflags |= QIBL_LINKV;
5720 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5721 }
5722 }
5723 }
5724
5725 /*
5726 * There is little we can do but complain to the user if QSFP
5727 * initialization fails.
5728 */
5729 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5730 {
5731 unsigned long flags;
5732 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5733 struct qib_devdata *dd = ppd->dd;
5734 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5735
5736 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5737 qd->ppd = ppd;
5738 qib_qsfp_init(qd, qsfp_7322_event);
5739 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5740 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5741 dd->cspec->gpio_mask |= mod_prs_bit;
5742 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5743 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5744 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5745 }
5746
5747 /*
5748 * called at device initialization time, and also if the txselect
5749 * module parameter is changed. This is used for cables that don't
5750 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5751 * We initialize to the default, then if there is a specific
5752 * unit,port match, we use that (and set it immediately, for the
5753 * current speed, if the link is at INIT or better).
5754 * String format is "default# unit#,port#=# ... u,p=#", separators must
5755 * be a SPACE character. A newline terminates. The u,p=# tuples may
5756 * optionally have "u,p=#,#", where the final # is the H1 value
5757 * The last specific match is used (actually, all are used, but last
5758 * one is the one that winds up set); if none at all, fall back on default.
5759 */
5760 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5761 {
5762 char *nxt, *str;
5763 u32 pidx, unit, port, deflt, h1;
5764 unsigned long val;
5765 int any = 0, seth1;
5766 int txdds_size;
5767
5768 str = txselect_list;
5769
5770 /* default number is validated in setup_txselect() */
5771 deflt = simple_strtoul(str, &nxt, 0);
5772 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5773 dd->pport[pidx].cpspec->no_eep = deflt;
5774
5775 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5776 if (IS_QME(dd) || IS_QMH(dd))
5777 txdds_size += TXDDS_MFG_SZ;
5778
5779 while (*nxt && nxt[1]) {
5780 str = ++nxt;
5781 unit = simple_strtoul(str, &nxt, 0);
5782 if (nxt == str || !*nxt || *nxt != ',') {
5783 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5784 ;
5785 continue;
5786 }
5787 str = ++nxt;
5788 port = simple_strtoul(str, &nxt, 0);
5789 if (nxt == str || *nxt != '=') {
5790 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5791 ;
5792 continue;
5793 }
5794 str = ++nxt;
5795 val = simple_strtoul(str, &nxt, 0);
5796 if (nxt == str) {
5797 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5798 ;
5799 continue;
5800 }
5801 if (val >= txdds_size)
5802 continue;
5803 seth1 = 0;
5804 h1 = 0; /* gcc thinks it might be used uninitted */
5805 if (*nxt == ',' && nxt[1]) {
5806 str = ++nxt;
5807 h1 = (u32)simple_strtoul(str, &nxt, 0);
5808 if (nxt == str)
5809 while (*nxt && *nxt++ != ' ') /* skip */
5810 ;
5811 else
5812 seth1 = 1;
5813 }
5814 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5815 ++pidx) {
5816 struct qib_pportdata *ppd = &dd->pport[pidx];
5817
5818 if (ppd->port != port || !ppd->link_speed_supported)
5819 continue;
5820 ppd->cpspec->no_eep = val;
5821 if (seth1)
5822 ppd->cpspec->h1_val = h1;
5823 /* now change the IBC and serdes, overriding generic */
5824 init_txdds_table(ppd, 1);
5825 /* Re-enable the physical state machine on mezz boards
5826 * now that the correct settings have been set.
5827 * QSFP boards are handles by the QSFP event handler */
5828 if (IS_QMH(dd) || IS_QME(dd))
5829 qib_set_ib_7322_lstate(ppd, 0,
5830 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5831 any++;
5832 }
5833 if (*nxt == '\n')
5834 break; /* done */
5835 }
5836 if (change && !any) {
5837 /* no specific setting, use the default.
5838 * Change the IBC and serdes, but since it's
5839 * general, don't override specific settings.
5840 */
5841 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5842 if (dd->pport[pidx].link_speed_supported)
5843 init_txdds_table(&dd->pport[pidx], 0);
5844 }
5845 }
5846
5847 /* handle the txselect parameter changing */
5848 static int setup_txselect(const char *str, struct kernel_param *kp)
5849 {
5850 struct qib_devdata *dd;
5851 unsigned long val;
5852 char *n;
5853 if (strlen(str) >= MAX_ATTEN_LEN) {
5854 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5855 "too long\n");
5856 return -ENOSPC;
5857 }
5858 val = simple_strtoul(str, &n, 0);
5859 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5860 TXDDS_MFG_SZ)) {
5861 printk(KERN_INFO QIB_DRV_NAME
5862 "txselect_values must start with a number < %d\n",
5863 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5864 return -EINVAL;
5865 }
5866 strcpy(txselect_list, str);
5867
5868 list_for_each_entry(dd, &qib_dev_list, list)
5869 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5870 set_no_qsfp_atten(dd, 1);
5871 return 0;
5872 }
5873
5874 /*
5875 * Write the final few registers that depend on some of the
5876 * init setup. Done late in init, just before bringing up
5877 * the serdes.
5878 */
5879 static int qib_late_7322_initreg(struct qib_devdata *dd)
5880 {
5881 int ret = 0, n;
5882 u64 val;
5883
5884 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5885 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5886 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5887 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5888 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5889 if (val != dd->pioavailregs_phys) {
5890 qib_dev_err(dd, "Catastrophic software error, "
5891 "SendPIOAvailAddr written as %lx, "
5892 "read back as %llx\n",
5893 (unsigned long) dd->pioavailregs_phys,
5894 (unsigned long long) val);
5895 ret = -EINVAL;
5896 }
5897
5898 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5899 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5900 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5901 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5902
5903 qib_register_observer(dd, &sendctrl_0_observer);
5904 qib_register_observer(dd, &sendctrl_1_observer);
5905
5906 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5907 qib_write_kreg(dd, kr_control, dd->control);
5908 /*
5909 * Set SendDmaFetchPriority and init Tx params, including
5910 * QSFP handler on boards that have QSFP.
5911 * First set our default attenuation entry for cables that
5912 * don't have valid attenuation.
5913 */
5914 set_no_qsfp_atten(dd, 0);
5915 for (n = 0; n < dd->num_pports; ++n) {
5916 struct qib_pportdata *ppd = dd->pport + n;
5917
5918 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5919 sdma_fetch_prio & 0xf);
5920 /* Initialize qsfp if present on board. */
5921 if (dd->flags & QIB_HAS_QSFP)
5922 qib_init_7322_qsfp(ppd);
5923 }
5924 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5925 qib_write_kreg(dd, kr_control, dd->control);
5926
5927 return ret;
5928 }
5929
5930 /* per IB port errors. */
5931 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5932 MASK_ACROSS(8, 15))
5933 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5934 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5935 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5936 MASK_ACROSS(0, 11))
5937
5938 /*
5939 * Write the initialization per-port registers that need to be done at
5940 * driver load and after reset completes (i.e., that aren't done as part
5941 * of other init procedures called from qib_init.c).
5942 * Some of these should be redundant on reset, but play safe.
5943 */
5944 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5945 {
5946 u64 val;
5947 int i;
5948
5949 if (!ppd->link_speed_supported) {
5950 /* no buffer credits for this port */
5951 for (i = 1; i < 8; i++)
5952 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5953 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5954 qib_write_kreg(ppd->dd, kr_scratch, 0);
5955 return;
5956 }
5957
5958 /*
5959 * Set the number of supported virtual lanes in IBC,
5960 * for flow control packet handling on unsupported VLs
5961 */
5962 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5963 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5964 val |= (u64)(ppd->vls_supported - 1) <<
5965 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5966 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5967
5968 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5969
5970 /* enable tx header checking */
5971 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5972 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5973 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5974
5975 qib_write_kreg_port(ppd, krp_ncmodectrl,
5976 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5977
5978 /*
5979 * Unconditionally clear the bufmask bits. If SDMA is
5980 * enabled, we'll set them appropriately later.
5981 */
5982 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5983 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5984 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5985 if (ppd->dd->cspec->r1)
5986 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5987 }
5988
5989 /*
5990 * Write the initialization per-device registers that need to be done at
5991 * driver load and after reset completes (i.e., that aren't done as part
5992 * of other init procedures called from qib_init.c). Also write per-port
5993 * registers that are affected by overall device config, such as QP mapping
5994 * Some of these should be redundant on reset, but play safe.
5995 */
5996 static void write_7322_initregs(struct qib_devdata *dd)
5997 {
5998 struct qib_pportdata *ppd;
5999 int i, pidx;
6000 u64 val;
6001
6002 /* Set Multicast QPs received by port 2 to map to context one. */
6003 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
6004
6005 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
6006 unsigned n, regno;
6007 unsigned long flags;
6008
6009 if (dd->n_krcv_queues < 2 ||
6010 !dd->pport[pidx].link_speed_supported)
6011 continue;
6012
6013 ppd = &dd->pport[pidx];
6014
6015 /* be paranoid against later code motion, etc. */
6016 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
6017 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
6018 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
6019
6020 /* Initialize QP to context mapping */
6021 regno = krp_rcvqpmaptable;
6022 val = 0;
6023 if (dd->num_pports > 1)
6024 n = dd->first_user_ctxt / dd->num_pports;
6025 else
6026 n = dd->first_user_ctxt - 1;
6027 for (i = 0; i < 32; ) {
6028 unsigned ctxt;
6029
6030 if (dd->num_pports > 1)
6031 ctxt = (i % n) * dd->num_pports + pidx;
6032 else if (i % n)
6033 ctxt = (i % n) + 1;
6034 else
6035 ctxt = ppd->hw_pidx;
6036 val |= ctxt << (5 * (i % 6));
6037 i++;
6038 if (i % 6 == 0) {
6039 qib_write_kreg_port(ppd, regno, val);
6040 val = 0;
6041 regno++;
6042 }
6043 }
6044 qib_write_kreg_port(ppd, regno, val);
6045 }
6046
6047 /*
6048 * Setup up interrupt mitigation for kernel contexts, but
6049 * not user contexts (user contexts use interrupts when
6050 * stalled waiting for any packet, so want those interrupts
6051 * right away).
6052 */
6053 for (i = 0; i < dd->first_user_ctxt; i++) {
6054 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6055 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6056 }
6057
6058 /*
6059 * Initialize as (disabled) rcvflow tables. Application code
6060 * will setup each flow as it uses the flow.
6061 * Doesn't clear any of the error bits that might be set.
6062 */
6063 val = TIDFLOW_ERRBITS; /* these are W1C */
6064 for (i = 0; i < dd->cfgctxts; i++) {
6065 int flow;
6066 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6067 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6068 }
6069
6070 /*
6071 * dual cards init to dual port recovery, single port cards to
6072 * the one port. Dual port cards may later adjust to 1 port,
6073 * and then back to dual port if both ports are connected
6074 * */
6075 if (dd->num_pports)
6076 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6077 }
6078
6079 static int qib_init_7322_variables(struct qib_devdata *dd)
6080 {
6081 struct qib_pportdata *ppd;
6082 unsigned features, pidx, sbufcnt;
6083 int ret, mtu;
6084 u32 sbufs, updthresh;
6085
6086 /* pport structs are contiguous, allocated after devdata */
6087 ppd = (struct qib_pportdata *)(dd + 1);
6088 dd->pport = ppd;
6089 ppd[0].dd = dd;
6090 ppd[1].dd = dd;
6091
6092 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6093
6094 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6095 ppd[1].cpspec = &ppd[0].cpspec[1];
6096 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6097 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6098
6099 spin_lock_init(&dd->cspec->rcvmod_lock);
6100 spin_lock_init(&dd->cspec->gpio_lock);
6101
6102 /* we haven't yet set QIB_PRESENT, so use read directly */
6103 dd->revision = readq(&dd->kregbase[kr_revision]);
6104
6105 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6106 qib_dev_err(dd, "Revision register read failure, "
6107 "giving up initialization\n");
6108 ret = -ENODEV;
6109 goto bail;
6110 }
6111 dd->flags |= QIB_PRESENT; /* now register routines work */
6112
6113 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6114 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6115 dd->cspec->r1 = dd->minrev == 1;
6116
6117 get_7322_chip_params(dd);
6118 features = qib_7322_boardname(dd);
6119
6120 /* now that piobcnt2k and 4k set, we can allocate these */
6121 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6122 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6123 sbufcnt /= BITS_PER_LONG;
6124 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6125 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6126 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6127 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6128 dd->cspec->sendibchk = kmalloc(sbufcnt *
6129 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6130 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6131 !dd->cspec->sendibchk) {
6132 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6133 ret = -ENOMEM;
6134 goto bail;
6135 }
6136
6137 ppd = dd->pport;
6138
6139 /*
6140 * GPIO bits for TWSI data and clock,
6141 * used for serial EEPROM.
6142 */
6143 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6144 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6145 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6146
6147 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6148 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6149 QIB_HAS_THRESH_UPDATE |
6150 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6151 dd->flags |= qib_special_trigger ?
6152 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6153
6154 /*
6155 * Setup initial values. These may change when PAT is enabled, but
6156 * we need these to do initial chip register accesses.
6157 */
6158 qib_7322_set_baseaddrs(dd);
6159
6160 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6161 if (mtu == -1)
6162 mtu = QIB_DEFAULT_MTU;
6163
6164 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6165 /* all hwerrors become interrupts, unless special purposed */
6166 dd->cspec->hwerrmask = ~0ULL;
6167 /* link_recovery setup causes these errors, so ignore them,
6168 * other than clearing them when they occur */
6169 dd->cspec->hwerrmask &=
6170 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6171 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6172 HWE_MASK(LATriggered));
6173
6174 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6175 struct qib_chippport_specific *cp = ppd->cpspec;
6176 ppd->link_speed_supported = features & PORT_SPD_CAP;
6177 features >>= PORT_SPD_CAP_SHIFT;
6178 if (!ppd->link_speed_supported) {
6179 /* single port mode (7340, or configured) */
6180 dd->skip_kctxt_mask |= 1 << pidx;
6181 if (pidx == 0) {
6182 /* Make sure port is disabled. */
6183 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6184 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6185 ppd[0] = ppd[1];
6186 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6187 IBSerdesPClkNotDetectMask_0)
6188 | SYM_MASK(HwErrMask,
6189 SDmaMemReadErrMask_0));
6190 dd->cspec->int_enable_mask &= ~(
6191 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6192 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6193 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6194 SYM_MASK(IntMask, SDmaIntMask_0) |
6195 SYM_MASK(IntMask, ErrIntMask_0) |
6196 SYM_MASK(IntMask, SendDoneIntMask_0));
6197 } else {
6198 /* Make sure port is disabled. */
6199 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6200 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6201 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6202 IBSerdesPClkNotDetectMask_1)
6203 | SYM_MASK(HwErrMask,
6204 SDmaMemReadErrMask_1));
6205 dd->cspec->int_enable_mask &= ~(
6206 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6207 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6208 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6209 SYM_MASK(IntMask, SDmaIntMask_1) |
6210 SYM_MASK(IntMask, ErrIntMask_1) |
6211 SYM_MASK(IntMask, SendDoneIntMask_1));
6212 }
6213 continue;
6214 }
6215
6216 dd->num_pports++;
6217 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6218
6219 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6220 ppd->link_width_enabled = IB_WIDTH_4X;
6221 ppd->link_speed_enabled = ppd->link_speed_supported;
6222 /*
6223 * Set the initial values to reasonable default, will be set
6224 * for real when link is up.
6225 */
6226 ppd->link_width_active = IB_WIDTH_4X;
6227 ppd->link_speed_active = QIB_IB_SDR;
6228 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6229 switch (qib_num_cfg_vls) {
6230 case 1:
6231 ppd->vls_supported = IB_VL_VL0;
6232 break;
6233 case 2:
6234 ppd->vls_supported = IB_VL_VL0_1;
6235 break;
6236 default:
6237 qib_devinfo(dd->pcidev,
6238 "Invalid num_vls %u, using 4 VLs\n",
6239 qib_num_cfg_vls);
6240 qib_num_cfg_vls = 4;
6241 /* fall through */
6242 case 4:
6243 ppd->vls_supported = IB_VL_VL0_3;
6244 break;
6245 case 8:
6246 if (mtu <= 2048)
6247 ppd->vls_supported = IB_VL_VL0_7;
6248 else {
6249 qib_devinfo(dd->pcidev,
6250 "Invalid num_vls %u for MTU %d "
6251 ", using 4 VLs\n",
6252 qib_num_cfg_vls, mtu);
6253 ppd->vls_supported = IB_VL_VL0_3;
6254 qib_num_cfg_vls = 4;
6255 }
6256 break;
6257 }
6258 ppd->vls_operational = ppd->vls_supported;
6259
6260 init_waitqueue_head(&cp->autoneg_wait);
6261 INIT_DELAYED_WORK(&cp->autoneg_work,
6262 autoneg_7322_work);
6263 if (ppd->dd->cspec->r1)
6264 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6265
6266 /*
6267 * For Mez and similar cards, no qsfp info, so do
6268 * the "cable info" setup here. Can be overridden
6269 * in adapter-specific routines.
6270 */
6271 if (!(dd->flags & QIB_HAS_QSFP)) {
6272 if (!IS_QMH(dd) && !IS_QME(dd))
6273 qib_devinfo(dd->pcidev, "IB%u:%u: "
6274 "Unknown mezzanine card type\n",
6275 dd->unit, ppd->port);
6276 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6277 /*
6278 * Choose center value as default tx serdes setting
6279 * until changed through module parameter.
6280 */
6281 ppd->cpspec->no_eep = IS_QMH(dd) ?
6282 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6283 } else
6284 cp->h1_val = H1_FORCE_VAL;
6285
6286 /* Avoid writes to chip for mini_init */
6287 if (!qib_mini_init)
6288 write_7322_init_portregs(ppd);
6289
6290 init_timer(&cp->chase_timer);
6291 cp->chase_timer.function = reenable_chase;
6292 cp->chase_timer.data = (unsigned long)ppd;
6293
6294 ppd++;
6295 }
6296
6297 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6298 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6299 dd->rcvhdrsize = qib_rcvhdrsize ?
6300 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6301 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6302
6303 /* we always allocate at least 2048 bytes for eager buffers */
6304 dd->rcvegrbufsize = max(mtu, 2048);
6305 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
6306 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
6307
6308 qib_7322_tidtemplate(dd);
6309
6310 /*
6311 * We can request a receive interrupt for 1 or
6312 * more packets from current offset.
6313 */
6314 dd->rhdrhead_intr_off =
6315 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6316
6317 /* setup the stats timer; the add_timer is done at end of init */
6318 init_timer(&dd->stats_timer);
6319 dd->stats_timer.function = qib_get_7322_faststats;
6320 dd->stats_timer.data = (unsigned long) dd;
6321
6322 dd->ureg_align = 0x10000; /* 64KB alignment */
6323
6324 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6325
6326 qib_7322_config_ctxts(dd);
6327 qib_set_ctxtcnt(dd);
6328
6329 if (qib_wc_pat) {
6330 resource_size_t vl15off;
6331 /*
6332 * We do not set WC on the VL15 buffers to avoid
6333 * a rare problem with unaligned writes from
6334 * interrupt-flushed store buffers, so we need
6335 * to map those separately here. We can't solve
6336 * this for the rarely used mtrr case.
6337 */
6338 ret = init_chip_wc_pat(dd, 0);
6339 if (ret)
6340 goto bail;
6341
6342 /* vl15 buffers start just after the 4k buffers */
6343 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6344 dd->piobcnt4k * dd->align4k;
6345 dd->piovl15base = ioremap_nocache(vl15off,
6346 NUM_VL15_BUFS * dd->align4k);
6347 if (!dd->piovl15base)
6348 goto bail;
6349 }
6350 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6351
6352 ret = 0;
6353 if (qib_mini_init)
6354 goto bail;
6355 if (!dd->num_pports) {
6356 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6357 goto bail; /* no error, so can still figure out why err */
6358 }
6359
6360 write_7322_initregs(dd);
6361 ret = qib_create_ctxts(dd);
6362 init_7322_cntrnames(dd);
6363
6364 updthresh = 8U; /* update threshold */
6365
6366 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6367 * reserve the update threshold amount for other kernel use, such
6368 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6369 * unless we aren't enabling SDMA, in which case we want to use
6370 * all the 4k bufs for the kernel.
6371 * if this was less than the update threshold, we could wait
6372 * a long time for an update. Coded this way because we
6373 * sometimes change the update threshold for various reasons,
6374 * and we want this to remain robust.
6375 */
6376 if (dd->flags & QIB_HAS_SEND_DMA) {
6377 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6378 sbufs = updthresh > 3 ? updthresh : 3;
6379 } else {
6380 dd->cspec->sdmabufcnt = 0;
6381 sbufs = dd->piobcnt4k;
6382 }
6383 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6384 dd->cspec->sdmabufcnt;
6385 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6386 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6387 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6388 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6389
6390 /*
6391 * If we have 16 user contexts, we will have 7 sbufs
6392 * per context, so reduce the update threshold to match. We
6393 * want to update before we actually run out, at low pbufs/ctxt
6394 * so give ourselves some margin.
6395 */
6396 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6397 updthresh = dd->pbufsctxt - 2;
6398 dd->cspec->updthresh_dflt = updthresh;
6399 dd->cspec->updthresh = updthresh;
6400
6401 /* before full enable, no interrupts, no locking needed */
6402 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6403 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6404 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6405
6406 dd->psxmitwait_supported = 1;
6407 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6408 bail:
6409 if (!dd->ctxtcnt)
6410 dd->ctxtcnt = 1; /* for other initialization code */
6411
6412 return ret;
6413 }
6414
6415 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6416 u32 *pbufnum)
6417 {
6418 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6419 struct qib_devdata *dd = ppd->dd;
6420
6421 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6422 if (pbc & PBC_7322_VL15_SEND) {
6423 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6424 last = first;
6425 } else {
6426 if ((plen + 1) > dd->piosize2kmax_dwords)
6427 first = dd->piobcnt2k;
6428 else
6429 first = 0;
6430 last = dd->cspec->lastbuf_for_pio;
6431 }
6432 return qib_getsendbuf_range(dd, pbufnum, first, last);
6433 }
6434
6435 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6436 u32 start)
6437 {
6438 qib_write_kreg_port(ppd, krp_psinterval, intv);
6439 qib_write_kreg_port(ppd, krp_psstart, start);
6440 }
6441
6442 /*
6443 * Must be called with sdma_lock held, or before init finished.
6444 */
6445 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6446 {
6447 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6448 }
6449
6450 static struct sdma_set_state_action sdma_7322_action_table[] = {
6451 [qib_sdma_state_s00_hw_down] = {
6452 .go_s99_running_tofalse = 1,
6453 .op_enable = 0,
6454 .op_intenable = 0,
6455 .op_halt = 0,
6456 .op_drain = 0,
6457 },
6458 [qib_sdma_state_s10_hw_start_up_wait] = {
6459 .op_enable = 0,
6460 .op_intenable = 1,
6461 .op_halt = 1,
6462 .op_drain = 0,
6463 },
6464 [qib_sdma_state_s20_idle] = {
6465 .op_enable = 1,
6466 .op_intenable = 1,
6467 .op_halt = 1,
6468 .op_drain = 0,
6469 },
6470 [qib_sdma_state_s30_sw_clean_up_wait] = {
6471 .op_enable = 0,
6472 .op_intenable = 1,
6473 .op_halt = 1,
6474 .op_drain = 0,
6475 },
6476 [qib_sdma_state_s40_hw_clean_up_wait] = {
6477 .op_enable = 1,
6478 .op_intenable = 1,
6479 .op_halt = 1,
6480 .op_drain = 0,
6481 },
6482 [qib_sdma_state_s50_hw_halt_wait] = {
6483 .op_enable = 1,
6484 .op_intenable = 1,
6485 .op_halt = 1,
6486 .op_drain = 1,
6487 },
6488 [qib_sdma_state_s99_running] = {
6489 .op_enable = 1,
6490 .op_intenable = 1,
6491 .op_halt = 0,
6492 .op_drain = 0,
6493 .go_s99_running_totrue = 1,
6494 },
6495 };
6496
6497 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6498 {
6499 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6500 }
6501
6502 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6503 {
6504 struct qib_devdata *dd = ppd->dd;
6505 unsigned lastbuf, erstbuf;
6506 u64 senddmabufmask[3] = { 0 };
6507 int n, ret = 0;
6508
6509 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6510 qib_sdma_7322_setlengen(ppd);
6511 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6512 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6513 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6514 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6515
6516 if (dd->num_pports)
6517 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6518 else
6519 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6520 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6521 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6522 dd->cspec->sdmabufcnt);
6523 lastbuf = erstbuf + n;
6524
6525 ppd->sdma_state.first_sendbuf = erstbuf;
6526 ppd->sdma_state.last_sendbuf = lastbuf;
6527 for (; erstbuf < lastbuf; ++erstbuf) {
6528 unsigned word = erstbuf / BITS_PER_LONG;
6529 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6530
6531 BUG_ON(word >= 3);
6532 senddmabufmask[word] |= 1ULL << bit;
6533 }
6534 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6535 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6536 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6537 return ret;
6538 }
6539
6540 /* sdma_lock must be held */
6541 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6542 {
6543 struct qib_devdata *dd = ppd->dd;
6544 int sane;
6545 int use_dmahead;
6546 u16 swhead;
6547 u16 swtail;
6548 u16 cnt;
6549 u16 hwhead;
6550
6551 use_dmahead = __qib_sdma_running(ppd) &&
6552 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6553 retry:
6554 hwhead = use_dmahead ?
6555 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6556 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6557
6558 swhead = ppd->sdma_descq_head;
6559 swtail = ppd->sdma_descq_tail;
6560 cnt = ppd->sdma_descq_cnt;
6561
6562 if (swhead < swtail)
6563 /* not wrapped */
6564 sane = (hwhead >= swhead) & (hwhead <= swtail);
6565 else if (swhead > swtail)
6566 /* wrapped around */
6567 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6568 (hwhead <= swtail);
6569 else
6570 /* empty */
6571 sane = (hwhead == swhead);
6572
6573 if (unlikely(!sane)) {
6574 if (use_dmahead) {
6575 /* try one more time, directly from the register */
6576 use_dmahead = 0;
6577 goto retry;
6578 }
6579 /* proceed as if no progress */
6580 hwhead = swhead;
6581 }
6582
6583 return hwhead;
6584 }
6585
6586 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6587 {
6588 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6589
6590 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6591 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6592 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6593 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6594 }
6595
6596 /*
6597 * Compute the amount of delay before sending the next packet if the
6598 * port's send rate differs from the static rate set for the QP.
6599 * The delay affects the next packet and the amount of the delay is
6600 * based on the length of the this packet.
6601 */
6602 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6603 u8 srate, u8 vl)
6604 {
6605 u8 snd_mult = ppd->delay_mult;
6606 u8 rcv_mult = ib_rate_to_delay[srate];
6607 u32 ret;
6608
6609 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6610
6611 /* Indicate VL15, else set the VL in the control word */
6612 if (vl == 15)
6613 ret |= PBC_7322_VL15_SEND_CTRL;
6614 else
6615 ret |= vl << PBC_VL_NUM_LSB;
6616 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6617
6618 return ret;
6619 }
6620
6621 /*
6622 * Enable the per-port VL15 send buffers for use.
6623 * They follow the rest of the buffers, without a config parameter.
6624 * This was in initregs, but that is done before the shadow
6625 * is set up, and this has to be done after the shadow is
6626 * set up.
6627 */
6628 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6629 {
6630 unsigned vl15bufs;
6631
6632 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6633 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6634 TXCHK_CHG_TYPE_KERN, NULL);
6635 }
6636
6637 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6638 {
6639 if (rcd->ctxt < NUM_IB_PORTS) {
6640 if (rcd->dd->num_pports > 1) {
6641 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6642 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6643 } else {
6644 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6645 rcd->rcvegr_tid_base = 0;
6646 }
6647 } else {
6648 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6649 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6650 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6651 }
6652 }
6653
6654 #define QTXSLEEPS 5000
6655 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6656 u32 len, u32 which, struct qib_ctxtdata *rcd)
6657 {
6658 int i;
6659 const int last = start + len - 1;
6660 const int lastr = last / BITS_PER_LONG;
6661 u32 sleeps = 0;
6662 int wait = rcd != NULL;
6663 unsigned long flags;
6664
6665 while (wait) {
6666 unsigned long shadow;
6667 int cstart, previ = -1;
6668
6669 /*
6670 * when flipping from kernel to user, we can't change
6671 * the checking type if the buffer is allocated to the
6672 * driver. It's OK the other direction, because it's
6673 * from close, and we have just disarm'ed all the
6674 * buffers. All the kernel to kernel changes are also
6675 * OK.
6676 */
6677 for (cstart = start; cstart <= last; cstart++) {
6678 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6679 / BITS_PER_LONG;
6680 if (i != previ) {
6681 shadow = (unsigned long)
6682 le64_to_cpu(dd->pioavailregs_dma[i]);
6683 previ = i;
6684 }
6685 if (test_bit(((2 * cstart) +
6686 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6687 % BITS_PER_LONG, &shadow))
6688 break;
6689 }
6690
6691 if (cstart > last)
6692 break;
6693
6694 if (sleeps == QTXSLEEPS)
6695 break;
6696 /* make sure we see an updated copy next time around */
6697 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6698 sleeps++;
6699 msleep(20);
6700 }
6701
6702 switch (which) {
6703 case TXCHK_CHG_TYPE_DIS1:
6704 /*
6705 * disable checking on a range; used by diags; just
6706 * one buffer, but still written generically
6707 */
6708 for (i = start; i <= last; i++)
6709 clear_bit(i, dd->cspec->sendchkenable);
6710 break;
6711
6712 case TXCHK_CHG_TYPE_ENAB1:
6713 /*
6714 * (re)enable checking on a range; used by diags; just
6715 * one buffer, but still written generically; read
6716 * scratch to be sure buffer actually triggered, not
6717 * just flushed from processor.
6718 */
6719 qib_read_kreg32(dd, kr_scratch);
6720 for (i = start; i <= last; i++)
6721 set_bit(i, dd->cspec->sendchkenable);
6722 break;
6723
6724 case TXCHK_CHG_TYPE_KERN:
6725 /* usable by kernel */
6726 for (i = start; i <= last; i++) {
6727 set_bit(i, dd->cspec->sendibchk);
6728 clear_bit(i, dd->cspec->sendgrhchk);
6729 }
6730 spin_lock_irqsave(&dd->uctxt_lock, flags);
6731 /* see if we need to raise avail update threshold */
6732 for (i = dd->first_user_ctxt;
6733 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6734 && i < dd->cfgctxts; i++)
6735 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6736 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6737 < dd->cspec->updthresh_dflt)
6738 break;
6739 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6740 if (i == dd->cfgctxts) {
6741 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6742 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6743 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6744 dd->sendctrl |= (dd->cspec->updthresh &
6745 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6746 SYM_LSB(SendCtrl, AvailUpdThld);
6747 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6748 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6749 }
6750 break;
6751
6752 case TXCHK_CHG_TYPE_USER:
6753 /* for user process */
6754 for (i = start; i <= last; i++) {
6755 clear_bit(i, dd->cspec->sendibchk);
6756 set_bit(i, dd->cspec->sendgrhchk);
6757 }
6758 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6759 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6760 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6761 dd->cspec->updthresh = (rcd->piocnt /
6762 rcd->subctxt_cnt) - 1;
6763 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6764 dd->sendctrl |= (dd->cspec->updthresh &
6765 SYM_RMASK(SendCtrl, AvailUpdThld))
6766 << SYM_LSB(SendCtrl, AvailUpdThld);
6767 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6768 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6769 } else
6770 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6771 break;
6772
6773 default:
6774 break;
6775 }
6776
6777 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6778 qib_write_kreg(dd, kr_sendcheckmask + i,
6779 dd->cspec->sendchkenable[i]);
6780
6781 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6782 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6783 dd->cspec->sendgrhchk[i]);
6784 qib_write_kreg(dd, kr_sendibpktmask + i,
6785 dd->cspec->sendibchk[i]);
6786 }
6787
6788 /*
6789 * Be sure whatever we did was seen by the chip and acted upon,
6790 * before we return. Mostly important for which >= 2.
6791 */
6792 qib_read_kreg32(dd, kr_scratch);
6793 }
6794
6795
6796 /* useful for trigger analyzers, etc. */
6797 static void writescratch(struct qib_devdata *dd, u32 val)
6798 {
6799 qib_write_kreg(dd, kr_scratch, val);
6800 }
6801
6802 /* Dummy for now, use chip regs soon */
6803 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6804 {
6805 return -ENXIO;
6806 }
6807
6808 /**
6809 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6810 * @dev: the pci_dev for qlogic_ib device
6811 * @ent: pci_device_id struct for this dev
6812 *
6813 * Also allocates, inits, and returns the devdata struct for this
6814 * device instance
6815 *
6816 * This is global, and is called directly at init to set up the
6817 * chip-specific function pointers for later use.
6818 */
6819 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6820 const struct pci_device_id *ent)
6821 {
6822 struct qib_devdata *dd;
6823 int ret, i;
6824 u32 tabsize, actual_cnt = 0;
6825
6826 dd = qib_alloc_devdata(pdev,
6827 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6828 sizeof(struct qib_chip_specific) +
6829 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6830 if (IS_ERR(dd))
6831 goto bail;
6832
6833 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6834 dd->f_cleanup = qib_setup_7322_cleanup;
6835 dd->f_clear_tids = qib_7322_clear_tids;
6836 dd->f_free_irq = qib_7322_free_irq;
6837 dd->f_get_base_info = qib_7322_get_base_info;
6838 dd->f_get_msgheader = qib_7322_get_msgheader;
6839 dd->f_getsendbuf = qib_7322_getsendbuf;
6840 dd->f_gpio_mod = gpio_7322_mod;
6841 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6842 dd->f_hdrqempty = qib_7322_hdrqempty;
6843 dd->f_ib_updown = qib_7322_ib_updown;
6844 dd->f_init_ctxt = qib_7322_init_ctxt;
6845 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6846 dd->f_intr_fallback = qib_7322_intr_fallback;
6847 dd->f_late_initreg = qib_late_7322_initreg;
6848 dd->f_setpbc_control = qib_7322_setpbc_control;
6849 dd->f_portcntr = qib_portcntr_7322;
6850 dd->f_put_tid = qib_7322_put_tid;
6851 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6852 dd->f_rcvctrl = rcvctrl_7322_mod;
6853 dd->f_read_cntrs = qib_read_7322cntrs;
6854 dd->f_read_portcntrs = qib_read_7322portcntrs;
6855 dd->f_reset = qib_do_7322_reset;
6856 dd->f_init_sdma_regs = init_sdma_7322_regs;
6857 dd->f_sdma_busy = qib_sdma_7322_busy;
6858 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6859 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6860 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6861 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6862 dd->f_sendctrl = sendctrl_7322_mod;
6863 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6864 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6865 dd->f_iblink_state = qib_7322_iblink_state;
6866 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6867 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6868 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6869 dd->f_set_ib_loopback = qib_7322_set_loopback;
6870 dd->f_get_ib_table = qib_7322_get_ib_table;
6871 dd->f_set_ib_table = qib_7322_set_ib_table;
6872 dd->f_set_intr_state = qib_7322_set_intr_state;
6873 dd->f_setextled = qib_setup_7322_setextled;
6874 dd->f_txchk_change = qib_7322_txchk_change;
6875 dd->f_update_usrhead = qib_update_7322_usrhead;
6876 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6877 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6878 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6879 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6880 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6881 dd->f_writescratch = writescratch;
6882 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6883 /*
6884 * Do remaining PCIe setup and save PCIe values in dd.
6885 * Any error printing is already done by the init code.
6886 * On return, we have the chip mapped, but chip registers
6887 * are not set up until start of qib_init_7322_variables.
6888 */
6889 ret = qib_pcie_ddinit(dd, pdev, ent);
6890 if (ret < 0)
6891 goto bail_free;
6892
6893 /* initialize chip-specific variables */
6894 ret = qib_init_7322_variables(dd);
6895 if (ret)
6896 goto bail_cleanup;
6897
6898 if (qib_mini_init || !dd->num_pports)
6899 goto bail;
6900
6901 /*
6902 * Determine number of vectors we want; depends on port count
6903 * and number of configured kernel receive queues actually used.
6904 * Should also depend on whether sdma is enabled or not, but
6905 * that's such a rare testing case it's not worth worrying about.
6906 */
6907 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6908 for (i = 0; i < tabsize; i++)
6909 if ((i < ARRAY_SIZE(irq_table) &&
6910 irq_table[i].port <= dd->num_pports) ||
6911 (i >= ARRAY_SIZE(irq_table) &&
6912 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6913 actual_cnt++;
6914 /* reduce by ctxt's < 2 */
6915 if (qib_krcvq01_no_msi)
6916 actual_cnt -= dd->num_pports;
6917
6918 tabsize = actual_cnt;
6919 dd->cspec->msix_entries = kmalloc(tabsize *
6920 sizeof(struct qib_msix_entry), GFP_KERNEL);
6921 if (!dd->cspec->msix_entries) {
6922 qib_dev_err(dd, "No memory for MSIx table\n");
6923 tabsize = 0;
6924 }
6925 for (i = 0; i < tabsize; i++)
6926 dd->cspec->msix_entries[i].msix.entry = i;
6927
6928 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6929 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6930 "continuing anyway\n");
6931 /* may be less than we wanted, if not enough available */
6932 dd->cspec->num_msix_entries = tabsize;
6933
6934 /* setup interrupt handler */
6935 qib_setup_7322_interrupt(dd, 1);
6936
6937 /* clear diagctrl register, in case diags were running and crashed */
6938 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6939
6940 goto bail;
6941
6942 bail_cleanup:
6943 qib_pcie_ddcleanup(dd);
6944 bail_free:
6945 qib_free_devdata(dd);
6946 dd = ERR_PTR(ret);
6947 bail:
6948 return dd;
6949 }
6950
6951 /*
6952 * Set the table entry at the specified index from the table specifed.
6953 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6954 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6955 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6956 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6957 */
6958 #define DDS_ENT_AMP_LSB 14
6959 #define DDS_ENT_MAIN_LSB 9
6960 #define DDS_ENT_POST_LSB 5
6961 #define DDS_ENT_PRE_XTRA_LSB 3
6962 #define DDS_ENT_PRE_LSB 0
6963
6964 /*
6965 * Set one entry in the TxDDS table for spec'd port
6966 * ridx picks one of the entries, while tp points
6967 * to the appropriate table entry.
6968 */
6969 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6970 const struct txdds_ent *tp)
6971 {
6972 struct qib_devdata *dd = ppd->dd;
6973 u32 pack_ent;
6974 int regidx;
6975
6976 /* Get correct offset in chip-space, and in source table */
6977 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6978 /*
6979 * We do not use qib_write_kreg_port() because it was intended
6980 * only for registers in the lower "port specific" pages.
6981 * So do index calculation by hand.
6982 */
6983 if (ppd->hw_pidx)
6984 regidx += (dd->palign / sizeof(u64));
6985
6986 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6987 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6988 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6989 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6990 qib_write_kreg(dd, regidx, pack_ent);
6991 /* Prevent back-to-back writes by hitting scratch */
6992 qib_write_kreg(ppd->dd, kr_scratch, 0);
6993 }
6994
6995 static const struct vendor_txdds_ent vendor_txdds[] = {
6996 { /* Amphenol 1m 30awg NoEq */
6997 { 0x41, 0x50, 0x48 }, "584470002 ",
6998 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6999 },
7000 { /* Amphenol 3m 28awg NoEq */
7001 { 0x41, 0x50, 0x48 }, "584470004 ",
7002 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
7003 },
7004 { /* Finisar 3m OM2 Optical */
7005 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
7006 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
7007 },
7008 { /* Finisar 30m OM2 Optical */
7009 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
7010 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
7011 },
7012 { /* Finisar Default OM2 Optical */
7013 { 0x00, 0x90, 0x65 }, NULL,
7014 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
7015 },
7016 { /* Gore 1m 30awg NoEq */
7017 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
7018 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
7019 },
7020 { /* Gore 2m 30awg NoEq */
7021 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
7022 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
7023 },
7024 { /* Gore 1m 28awg NoEq */
7025 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
7026 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
7027 },
7028 { /* Gore 3m 28awg NoEq */
7029 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
7030 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
7031 },
7032 { /* Gore 5m 24awg Eq */
7033 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
7034 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
7035 },
7036 { /* Gore 7m 24awg Eq */
7037 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7038 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
7039 },
7040 { /* Gore 5m 26awg Eq */
7041 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7042 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
7043 },
7044 { /* Gore 7m 26awg Eq */
7045 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7046 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7047 },
7048 { /* Intersil 12m 24awg Active */
7049 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7050 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7051 },
7052 { /* Intersil 10m 28awg Active */
7053 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7054 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7055 },
7056 { /* Intersil 7m 30awg Active */
7057 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7058 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7059 },
7060 { /* Intersil 5m 32awg Active */
7061 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7062 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7063 },
7064 { /* Intersil Default Active */
7065 { 0x00, 0x30, 0xB4 }, NULL,
7066 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7067 },
7068 { /* Luxtera 20m Active Optical */
7069 { 0x00, 0x25, 0x63 }, NULL,
7070 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7071 },
7072 { /* Molex 1M Cu loopback */
7073 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7074 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7075 },
7076 { /* Molex 2m 28awg NoEq */
7077 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7078 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7079 },
7080 };
7081
7082 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7083 /* amp, pre, main, post */
7084 { 2, 2, 15, 6 }, /* Loopback */
7085 { 0, 0, 0, 1 }, /* 2 dB */
7086 { 0, 0, 0, 2 }, /* 3 dB */
7087 { 0, 0, 0, 3 }, /* 4 dB */
7088 { 0, 0, 0, 4 }, /* 5 dB */
7089 { 0, 0, 0, 5 }, /* 6 dB */
7090 { 0, 0, 0, 6 }, /* 7 dB */
7091 { 0, 0, 0, 7 }, /* 8 dB */
7092 { 0, 0, 0, 8 }, /* 9 dB */
7093 { 0, 0, 0, 9 }, /* 10 dB */
7094 { 0, 0, 0, 10 }, /* 11 dB */
7095 { 0, 0, 0, 11 }, /* 12 dB */
7096 { 0, 0, 0, 12 }, /* 13 dB */
7097 { 0, 0, 0, 13 }, /* 14 dB */
7098 { 0, 0, 0, 14 }, /* 15 dB */
7099 { 0, 0, 0, 15 }, /* 16 dB */
7100 };
7101
7102 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7103 /* amp, pre, main, post */
7104 { 2, 2, 15, 6 }, /* Loopback */
7105 { 0, 0, 0, 8 }, /* 2 dB */
7106 { 0, 0, 0, 8 }, /* 3 dB */
7107 { 0, 0, 0, 9 }, /* 4 dB */
7108 { 0, 0, 0, 9 }, /* 5 dB */
7109 { 0, 0, 0, 10 }, /* 6 dB */
7110 { 0, 0, 0, 10 }, /* 7 dB */
7111 { 0, 0, 0, 11 }, /* 8 dB */
7112 { 0, 0, 0, 11 }, /* 9 dB */
7113 { 0, 0, 0, 12 }, /* 10 dB */
7114 { 0, 0, 0, 12 }, /* 11 dB */
7115 { 0, 0, 0, 13 }, /* 12 dB */
7116 { 0, 0, 0, 13 }, /* 13 dB */
7117 { 0, 0, 0, 14 }, /* 14 dB */
7118 { 0, 0, 0, 14 }, /* 15 dB */
7119 { 0, 0, 0, 15 }, /* 16 dB */
7120 };
7121
7122 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7123 /* amp, pre, main, post */
7124 { 2, 2, 15, 6 }, /* Loopback */
7125 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7126 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
7127 { 0, 1, 0, 11 }, /* 4 dB */
7128 { 0, 1, 0, 13 }, /* 5 dB */
7129 { 0, 1, 0, 15 }, /* 6 dB */
7130 { 0, 1, 3, 15 }, /* 7 dB */
7131 { 0, 1, 7, 15 }, /* 8 dB */
7132 { 0, 1, 7, 15 }, /* 9 dB */
7133 { 0, 1, 8, 15 }, /* 10 dB */
7134 { 0, 1, 9, 15 }, /* 11 dB */
7135 { 0, 1, 10, 15 }, /* 12 dB */
7136 { 0, 2, 6, 15 }, /* 13 dB */
7137 { 0, 2, 7, 15 }, /* 14 dB */
7138 { 0, 2, 8, 15 }, /* 15 dB */
7139 { 0, 2, 9, 15 }, /* 16 dB */
7140 };
7141
7142 /*
7143 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7144 * These are mostly used for mez cards going through connectors
7145 * and backplane traces, but can be used to add other "unusual"
7146 * table values as well.
7147 */
7148 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7149 /* amp, pre, main, post */
7150 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7151 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7152 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7153 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7154 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7155 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7156 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7157 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7158 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7159 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7160 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7161 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7162 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7163 };
7164
7165 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7166 /* amp, pre, main, post */
7167 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7168 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7169 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7170 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7171 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7172 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7173 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7174 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7175 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7176 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7177 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7178 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7179 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7180 };
7181
7182 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7183 /* amp, pre, main, post */
7184 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7185 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7186 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7187 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7188 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7189 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7190 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7191 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7192 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7193 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7194 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7195 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7196 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7197 };
7198
7199 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7200 /* amp, pre, main, post */
7201 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7202 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7203 };
7204
7205 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7206 unsigned atten)
7207 {
7208 /*
7209 * The attenuation table starts at 2dB for entry 1,
7210 * with entry 0 being the loopback entry.
7211 */
7212 if (atten <= 2)
7213 atten = 1;
7214 else if (atten > TXDDS_TABLE_SZ)
7215 atten = TXDDS_TABLE_SZ - 1;
7216 else
7217 atten--;
7218 return txdds + atten;
7219 }
7220
7221 /*
7222 * if override is set, the module parameter txselect has a value
7223 * for this specific port, so use it, rather than our normal mechanism.
7224 */
7225 static void find_best_ent(struct qib_pportdata *ppd,
7226 const struct txdds_ent **sdr_dds,
7227 const struct txdds_ent **ddr_dds,
7228 const struct txdds_ent **qdr_dds, int override)
7229 {
7230 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7231 int idx;
7232
7233 /* Search table of known cables */
7234 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7235 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7236
7237 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7238 (!v->partnum ||
7239 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7240 *sdr_dds = &v->sdr;
7241 *ddr_dds = &v->ddr;
7242 *qdr_dds = &v->qdr;
7243 return;
7244 }
7245 }
7246
7247 /* Active cables don't have attenuation so we only set SERDES
7248 * settings to account for the attenuation of the board traces. */
7249 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7250 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7251 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7252 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7253 return;
7254 }
7255
7256 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7257 qd->atten[1])) {
7258 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7259 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7260 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7261 return;
7262 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7263 /*
7264 * If we have no (or incomplete) data from the cable
7265 * EEPROM, or no QSFP, or override is set, use the
7266 * module parameter value to index into the attentuation
7267 * table.
7268 */
7269 idx = ppd->cpspec->no_eep;
7270 *sdr_dds = &txdds_sdr[idx];
7271 *ddr_dds = &txdds_ddr[idx];
7272 *qdr_dds = &txdds_qdr[idx];
7273 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7274 /* similar to above, but index into the "extra" table. */
7275 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7276 *sdr_dds = &txdds_extra_sdr[idx];
7277 *ddr_dds = &txdds_extra_ddr[idx];
7278 *qdr_dds = &txdds_extra_qdr[idx];
7279 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7280 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7281 TXDDS_MFG_SZ)) {
7282 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7283 printk(KERN_INFO QIB_DRV_NAME
7284 " IB%u:%u use idx %u into txdds_mfg\n",
7285 ppd->dd->unit, ppd->port, idx);
7286 *sdr_dds = &txdds_extra_mfg[idx];
7287 *ddr_dds = &txdds_extra_mfg[idx];
7288 *qdr_dds = &txdds_extra_mfg[idx];
7289 } else {
7290 /* this shouldn't happen, it's range checked */
7291 *sdr_dds = txdds_sdr + qib_long_atten;
7292 *ddr_dds = txdds_ddr + qib_long_atten;
7293 *qdr_dds = txdds_qdr + qib_long_atten;
7294 }
7295 }
7296
7297 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7298 {
7299 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7300 struct txdds_ent *dds;
7301 int idx;
7302 int single_ent = 0;
7303
7304 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7305
7306 /* for mez cards or override, use the selected value for all entries */
7307 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7308 single_ent = 1;
7309
7310 /* Fill in the first entry with the best entry found. */
7311 set_txdds(ppd, 0, sdr_dds);
7312 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7313 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7314 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7315 QIBL_LINKACTIVE)) {
7316 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7317 QIB_IB_QDR ? qdr_dds :
7318 (ppd->link_speed_active ==
7319 QIB_IB_DDR ? ddr_dds : sdr_dds));
7320 write_tx_serdes_param(ppd, dds);
7321 }
7322
7323 /* Fill in the remaining entries with the default table values. */
7324 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7325 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7326 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7327 single_ent ? ddr_dds : txdds_ddr + idx);
7328 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7329 single_ent ? qdr_dds : txdds_qdr + idx);
7330 }
7331 }
7332
7333 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7334 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7335 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7336 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7337 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7338 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7339 #define AHB_TRANS_TRIES 10
7340
7341 /*
7342 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7343 * 5=subsystem which is why most calls have "chan + chan >> 1"
7344 * for the channel argument.
7345 */
7346 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7347 u32 data, u32 mask)
7348 {
7349 u32 rd_data, wr_data, sz_mask;
7350 u64 trans, acc, prev_acc;
7351 u32 ret = 0xBAD0BAD;
7352 int tries;
7353
7354 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7355 /* From this point on, make sure we return access */
7356 acc = (quad << 1) | 1;
7357 qib_write_kreg(dd, KR_AHB_ACC, acc);
7358
7359 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7360 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7361 if (trans & AHB_TRANS_RDY)
7362 break;
7363 }
7364 if (tries >= AHB_TRANS_TRIES) {
7365 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7366 goto bail;
7367 }
7368
7369 /* If mask is not all 1s, we need to read, but different SerDes
7370 * entities have different sizes
7371 */
7372 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7373 wr_data = data & mask & sz_mask;
7374 if ((~mask & sz_mask) != 0) {
7375 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7376 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7377
7378 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7379 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7380 if (trans & AHB_TRANS_RDY)
7381 break;
7382 }
7383 if (tries >= AHB_TRANS_TRIES) {
7384 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7385 AHB_TRANS_TRIES);
7386 goto bail;
7387 }
7388 /* Re-read in case host split reads and read data first */
7389 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7390 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7391 wr_data |= (rd_data & ~mask & sz_mask);
7392 }
7393
7394 /* If mask is not zero, we need to write. */
7395 if (mask & sz_mask) {
7396 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7397 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7398 trans |= AHB_WR;
7399 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7400
7401 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7402 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7403 if (trans & AHB_TRANS_RDY)
7404 break;
7405 }
7406 if (tries >= AHB_TRANS_TRIES) {
7407 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7408 AHB_TRANS_TRIES);
7409 goto bail;
7410 }
7411 }
7412 ret = wr_data;
7413 bail:
7414 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7415 return ret;
7416 }
7417
7418 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7419 unsigned mask)
7420 {
7421 struct qib_devdata *dd = ppd->dd;
7422 int chan;
7423 u32 rbc;
7424
7425 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7426 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7427 data, mask);
7428 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7429 addr, 0, 0);
7430 }
7431 }
7432
7433 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7434 {
7435 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7436 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7437
7438 if (enable && !state) {
7439 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS on\n",
7440 ppd->dd->unit, ppd->port);
7441 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7442 } else if (!enable && state) {
7443 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS off\n",
7444 ppd->dd->unit, ppd->port);
7445 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7446 }
7447 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7448 }
7449
7450 static int serdes_7322_init(struct qib_pportdata *ppd)
7451 {
7452 int ret = 0;
7453 if (ppd->dd->cspec->r1)
7454 ret = serdes_7322_init_old(ppd);
7455 else
7456 ret = serdes_7322_init_new(ppd);
7457 return ret;
7458 }
7459
7460 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7461 {
7462 u32 le_val;
7463
7464 /*
7465 * Initialize the Tx DDS tables. Also done every QSFP event,
7466 * for adapters with QSFP
7467 */
7468 init_txdds_table(ppd, 0);
7469
7470 /* ensure no tx overrides from earlier driver loads */
7471 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7472 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7473 reset_tx_deemphasis_override));
7474
7475 /* Patch some SerDes defaults to "Better for IB" */
7476 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7477 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7478
7479 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7480 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7481 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7482 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7483
7484 /* May be overridden in qsfp_7322_event */
7485 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7486 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7487
7488 /* enable LE1 adaptation for all but QME, which is disabled */
7489 le_val = IS_QME(ppd->dd) ? 0 : 1;
7490 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7491
7492 /* Clear cmode-override, may be set from older driver */
7493 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7494
7495 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7496 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7497
7498 /* setup LoS params; these are subsystem, so chan == 5 */
7499 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7500 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7501 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7502 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7503 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7504
7505 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7506 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7507 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7508 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7509 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7510
7511 /* LoS filter select enabled */
7512 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7513
7514 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7515 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7516 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7517 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7518
7519 serdes_7322_los_enable(ppd, 1);
7520
7521 /* rxbistena; set 0 to avoid effects of it switch later */
7522 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7523
7524 /* Configure 4 DFE taps, and only they adapt */
7525 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7526
7527 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7528 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7529 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7530
7531 /*
7532 * Set receive adaptation mode. SDR and DDR adaptation are
7533 * always on, and QDR is initially enabled; later disabled.
7534 */
7535 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7536 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7537 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7538 ppd->dd->cspec->r1 ?
7539 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7540 ppd->cpspec->qdr_dfe_on = 1;
7541
7542 /* FLoop LOS gate: PPM filter enabled */
7543 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7544
7545 /* rx offset center enabled */
7546 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7547
7548 if (!ppd->dd->cspec->r1) {
7549 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7550 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7551 }
7552
7553 /* Set the frequency loop bandwidth to 15 */
7554 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7555
7556 return 0;
7557 }
7558
7559 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7560 {
7561 unsigned long tend;
7562 u32 le_val, rxcaldone;
7563 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7564
7565 /* Clear cmode-override, may be set from older driver */
7566 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7567
7568 /* ensure no tx overrides from earlier driver loads */
7569 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7570 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7571 reset_tx_deemphasis_override));
7572
7573 /* START OF LSI SUGGESTED SERDES BRINGUP */
7574 /* Reset - Calibration Setup */
7575 /* Stop DFE adaptaion */
7576 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7577 /* Disable LE1 */
7578 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7579 /* Disable autoadapt for LE1 */
7580 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7581 /* Disable LE2 */
7582 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7583 /* Disable VGA */
7584 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7585 /* Disable AFE Offset Cancel */
7586 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7587 /* Disable Timing Loop */
7588 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7589 /* Disable Frequency Loop */
7590 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7591 /* Disable Baseline Wander Correction */
7592 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7593 /* Disable RX Calibration */
7594 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7595 /* Disable RX Offset Calibration */
7596 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7597 /* Select BB CDR */
7598 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7599 /* CDR Step Size */
7600 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7601 /* Enable phase Calibration */
7602 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7603 /* DFE Bandwidth [2:14-12] */
7604 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7605 /* DFE Config (4 taps only) */
7606 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7607 /* Gain Loop Bandwidth */
7608 if (!ppd->dd->cspec->r1) {
7609 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7610 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7611 } else {
7612 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7613 }
7614 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7615 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7616 /* Data Rate Select [5:7-6] (leave as default) */
7617 /* RX Parallel Word Width [3:10-8] (leave as default) */
7618
7619 /* RX REST */
7620 /* Single- or Multi-channel reset */
7621 /* RX Analog reset */
7622 /* RX Digital reset */
7623 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7624 msleep(20);
7625 /* RX Analog reset */
7626 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7627 msleep(20);
7628 /* RX Digital reset */
7629 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7630 msleep(20);
7631
7632 /* setup LoS params; these are subsystem, so chan == 5 */
7633 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7634 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7635 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7636 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7637 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7638
7639 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7640 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7641 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7642 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7643 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7644
7645 /* LoS filter select enabled */
7646 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7647
7648 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7649 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7650 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7651 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7652
7653 /* Turn on LOS on initial SERDES init */
7654 serdes_7322_los_enable(ppd, 1);
7655 /* FLoop LOS gate: PPM filter enabled */
7656 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7657
7658 /* RX LATCH CALIBRATION */
7659 /* Enable Eyefinder Phase Calibration latch */
7660 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7661 /* Enable RX Offset Calibration latch */
7662 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7663 msleep(20);
7664 /* Start Calibration */
7665 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7666 tend = jiffies + msecs_to_jiffies(500);
7667 while (chan_done && !time_is_before_jiffies(tend)) {
7668 msleep(20);
7669 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7670 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7671 (chan + (chan >> 1)),
7672 25, 0, 0);
7673 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7674 (~chan_done & (1 << chan)) == 0)
7675 chan_done &= ~(1 << chan);
7676 }
7677 }
7678 if (chan_done) {
7679 printk(KERN_INFO QIB_DRV_NAME
7680 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7681 IBSD(ppd->hw_pidx), chan_done);
7682 } else {
7683 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7684 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7685 (chan + (chan >> 1)),
7686 25, 0, 0);
7687 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7688 printk(KERN_INFO QIB_DRV_NAME
7689 " Serdes %d chan %d calibration "
7690 "failed\n", IBSD(ppd->hw_pidx), chan);
7691 }
7692 }
7693
7694 /* Turn off Calibration */
7695 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7696 msleep(20);
7697
7698 /* BRING RX UP */
7699 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7700 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7701 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7702 /* Set LE2 Loop bandwidth */
7703 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7704 /* Enable LE2 */
7705 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7706 msleep(20);
7707 /* Enable H0 only */
7708 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7709 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7710 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7711 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7712 /* Enable VGA */
7713 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7714 msleep(20);
7715 /* Set Frequency Loop Bandwidth */
7716 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
7717 /* Enable Frequency Loop */
7718 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7719 /* Set Timing Loop Bandwidth */
7720 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7721 /* Enable Timing Loop */
7722 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7723 msleep(50);
7724 /* Enable DFE
7725 * Set receive adaptation mode. SDR and DDR adaptation are
7726 * always on, and QDR is initially enabled; later disabled.
7727 */
7728 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7729 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7730 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7731 ppd->dd->cspec->r1 ?
7732 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7733 ppd->cpspec->qdr_dfe_on = 1;
7734 /* Disable LE1 */
7735 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7736 /* Disable auto adapt for LE1 */
7737 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7738 msleep(20);
7739 /* Enable AFE Offset Cancel */
7740 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7741 /* Enable Baseline Wander Correction */
7742 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7743 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7744 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7745 /* VGA output common mode */
7746 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7747
7748 /*
7749 * Initialize the Tx DDS tables. Also done every QSFP event,
7750 * for adapters with QSFP
7751 */
7752 init_txdds_table(ppd, 0);
7753
7754 return 0;
7755 }
7756
7757 /* start adjust QMH serdes parameters */
7758
7759 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7760 {
7761 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7762 9, code << 9, 0x3f << 9);
7763 }
7764
7765 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7766 int enable, u32 tapenable)
7767 {
7768 if (enable)
7769 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7770 1, 3 << 10, 0x1f << 10);
7771 else
7772 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7773 1, 0, 0x1f << 10);
7774 }
7775
7776 /* Set clock to 1, 0, 1, 0 */
7777 static void clock_man(struct qib_pportdata *ppd, int chan)
7778 {
7779 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7780 4, 0x4000, 0x4000);
7781 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7782 4, 0, 0x4000);
7783 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7784 4, 0x4000, 0x4000);
7785 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7786 4, 0, 0x4000);
7787 }
7788
7789 /*
7790 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7791 * The caller must pass the settings appropriate for the current speed,
7792 * or not care if they are correct for the current speed.
7793 */
7794 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7795 struct txdds_ent *txdds)
7796 {
7797 u64 deemph;
7798
7799 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7800 /* field names for amp, main, post, pre, respectively */
7801 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7802 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7803 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7804 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7805
7806 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7807 tx_override_deemphasis_select);
7808 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7809 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7810 txampcntl_d2a);
7811 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7812 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7813 txc0_ena);
7814 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7815 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7816 txcp1_ena);
7817 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7818 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7819 txcn1_ena);
7820 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7821 }
7822
7823 /*
7824 * Set the parameters for mez cards on link bounce, so they are
7825 * always exactly what was requested. Similar logic to init_txdds
7826 * but does just the serdes.
7827 */
7828 static void adj_tx_serdes(struct qib_pportdata *ppd)
7829 {
7830 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7831 struct txdds_ent *dds;
7832
7833 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7834 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7835 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7836 ddr_dds : sdr_dds));
7837 write_tx_serdes_param(ppd, dds);
7838 }
7839
7840 /* set QDR forced value for H1, if needed */
7841 static void force_h1(struct qib_pportdata *ppd)
7842 {
7843 int chan;
7844
7845 ppd->cpspec->qdr_reforce = 0;
7846 if (!ppd->dd->cspec->r1)
7847 return;
7848
7849 for (chan = 0; chan < SERDES_CHANS; chan++) {
7850 set_man_mode_h1(ppd, chan, 1, 0);
7851 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7852 clock_man(ppd, chan);
7853 set_man_mode_h1(ppd, chan, 0, 0);
7854 }
7855 }
7856
7857 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7858 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7859
7860 #define R_OPCODE_LSB 3
7861 #define R_OP_NOP 0
7862 #define R_OP_SHIFT 2
7863 #define R_OP_UPDATE 3
7864 #define R_TDI_LSB 2
7865 #define R_TDO_LSB 1
7866 #define R_RDY 1
7867
7868 static int qib_r_grab(struct qib_devdata *dd)
7869 {
7870 u64 val;
7871 val = SJA_EN;
7872 qib_write_kreg(dd, kr_r_access, val);
7873 qib_read_kreg32(dd, kr_scratch);
7874 return 0;
7875 }
7876
7877 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7878 * returns the current state of R_TDO
7879 */
7880 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7881 {
7882 u64 val;
7883 int timeout;
7884 for (timeout = 0; timeout < 100 ; ++timeout) {
7885 val = qib_read_kreg32(dd, kr_r_access);
7886 if (val & R_RDY)
7887 return (val >> R_TDO_LSB) & 1;
7888 }
7889 return -1;
7890 }
7891
7892 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7893 int len, u8 *inp, u8 *outp)
7894 {
7895 u64 valbase, val;
7896 int ret, pos;
7897
7898 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7899 (R_OP_SHIFT << R_OPCODE_LSB);
7900 ret = qib_r_wait_for_rdy(dd);
7901 if (ret < 0)
7902 goto bail;
7903 for (pos = 0; pos < len; ++pos) {
7904 val = valbase;
7905 if (outp) {
7906 outp[pos >> 3] &= ~(1 << (pos & 7));
7907 outp[pos >> 3] |= (ret << (pos & 7));
7908 }
7909 if (inp) {
7910 int tdi = inp[pos >> 3] >> (pos & 7);
7911 val |= ((tdi & 1) << R_TDI_LSB);
7912 }
7913 qib_write_kreg(dd, kr_r_access, val);
7914 qib_read_kreg32(dd, kr_scratch);
7915 ret = qib_r_wait_for_rdy(dd);
7916 if (ret < 0)
7917 break;
7918 }
7919 /* Restore to NOP between operations. */
7920 val = SJA_EN | (bisten << BISTEN_LSB);
7921 qib_write_kreg(dd, kr_r_access, val);
7922 qib_read_kreg32(dd, kr_scratch);
7923 ret = qib_r_wait_for_rdy(dd);
7924
7925 if (ret >= 0)
7926 ret = pos;
7927 bail:
7928 return ret;
7929 }
7930
7931 static int qib_r_update(struct qib_devdata *dd, int bisten)
7932 {
7933 u64 val;
7934 int ret;
7935
7936 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7937 ret = qib_r_wait_for_rdy(dd);
7938 if (ret >= 0) {
7939 qib_write_kreg(dd, kr_r_access, val);
7940 qib_read_kreg32(dd, kr_scratch);
7941 }
7942 return ret;
7943 }
7944
7945 #define BISTEN_PORT_SEL 15
7946 #define LEN_PORT_SEL 625
7947 #define BISTEN_AT 17
7948 #define LEN_AT 156
7949 #define BISTEN_ETM 16
7950 #define LEN_ETM 632
7951
7952 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7953
7954 /* these are common for all IB port use cases. */
7955 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7956 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7957 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7958 };
7959 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7961 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7962 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7963 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7964 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7965 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7966 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7967 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7968 };
7969 static u8 at[BIT2BYTE(LEN_AT)] = {
7970 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7971 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7972 };
7973
7974 /* used for IB1 or IB2, only one in use */
7975 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7976 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7978 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7979 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7981 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7982 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7983 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7984 };
7985
7986 /* used when both IB1 and IB2 are in use */
7987 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7989 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7990 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7991 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7992 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7993 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7994 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7995 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7996 };
7997
7998 /* used when only IB1 is in use */
7999 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
8000 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8001 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8002 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8003 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8004 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8005 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8006 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8007 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8008 };
8009
8010 /* used when only IB2 is in use */
8011 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
8012 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
8013 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
8014 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8015 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
8016 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
8017 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8018 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
8019 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
8020 };
8021
8022 /* used when both IB1 and IB2 are in use */
8023 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
8024 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
8025 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
8026 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8027 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
8028 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
8029 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
8030 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
8031 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
8032 };
8033
8034 /*
8035 * Do setup to properly handle IB link recovery; if port is zero, we
8036 * are initializing to cover both ports; otherwise we are initializing
8037 * to cover a single port card, or the port has reached INIT and we may
8038 * need to switch coverage types.
8039 */
8040 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
8041 {
8042 u8 *portsel, *etm;
8043 struct qib_devdata *dd = ppd->dd;
8044
8045 if (!ppd->dd->cspec->r1)
8046 return;
8047 if (!both) {
8048 dd->cspec->recovery_ports_initted++;
8049 ppd->cpspec->recovery_init = 1;
8050 }
8051 if (!both && dd->cspec->recovery_ports_initted == 1) {
8052 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
8053 etm = atetm_1port;
8054 } else {
8055 portsel = portsel_2port;
8056 etm = atetm_2port;
8057 }
8058
8059 if (qib_r_grab(dd) < 0 ||
8060 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
8061 qib_r_update(dd, BISTEN_ETM) < 0 ||
8062 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
8063 qib_r_update(dd, BISTEN_AT) < 0 ||
8064 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
8065 portsel, NULL) < 0 ||
8066 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
8067 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
8068 qib_r_update(dd, BISTEN_AT) < 0 ||
8069 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
8070 qib_r_update(dd, BISTEN_ETM) < 0)
8071 qib_dev_err(dd, "Failed IB link recovery setup\n");
8072 }
8073
8074 static void check_7322_rxe_status(struct qib_pportdata *ppd)
8075 {
8076 struct qib_devdata *dd = ppd->dd;
8077 u64 fmask;
8078
8079 if (dd->cspec->recovery_ports_initted != 1)
8080 return; /* rest doesn't apply to dualport */
8081 qib_write_kreg(dd, kr_control, dd->control |
8082 SYM_MASK(Control, FreezeMode));
8083 (void)qib_read_kreg64(dd, kr_scratch);
8084 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
8085 fmask = qib_read_kreg64(dd, kr_act_fmask);
8086 if (!fmask) {
8087 /*
8088 * require a powercycle before we'll work again, and make
8089 * sure we get no more interrupts, and don't turn off
8090 * freeze.
8091 */
8092 ppd->dd->cspec->stay_in_freeze = 1;
8093 qib_7322_set_intr_state(ppd->dd, 0);
8094 qib_write_kreg(dd, kr_fmask, 0ULL);
8095 qib_dev_err(dd, "HCA unusable until powercycled\n");
8096 return; /* eventually reset */
8097 }
8098
8099 qib_write_kreg(ppd->dd, kr_hwerrclear,
8100 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8101
8102 /* don't do the full clear_freeze(), not needed for this */
8103 qib_write_kreg(dd, kr_control, dd->control);
8104 qib_read_kreg32(dd, kr_scratch);
8105 /* take IBC out of reset */
8106 if (ppd->link_speed_supported) {
8107 ppd->cpspec->ibcctrl_a &=
8108 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8109 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8110 ppd->cpspec->ibcctrl_a);
8111 qib_read_kreg32(dd, kr_scratch);
8112 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8113 qib_set_ib_7322_lstate(ppd, 0,
8114 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
8115 }
8116 }
Linux with added FPC-III support