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Linux 3.4.102
[linux/fpc-iii.git] / drivers / mmc / host / atmel-mci.c
blobe6f08d945709801a8f6e8dc2d097a0a32c280491
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26 #include <linux/stat.h>
27 #include <linux/types.h>
28
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/sdio.h>
31
32 #include <mach/atmel-mci.h>
33 #include <linux/atmel-mci.h>
34 #include <linux/atmel_pdc.h>
35
36 #include <asm/io.h>
37 #include <asm/unaligned.h>
38
39 #include <mach/cpu.h>
40 #include <mach/board.h>
41
42 #include "atmel-mci-regs.h"
43
44 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
45 #define ATMCI_DMA_THRESHOLD 16
46
47 enum {
48 EVENT_CMD_COMPLETE = 0,
49 EVENT_XFER_COMPLETE,
50 EVENT_DATA_COMPLETE,
51 EVENT_DATA_ERROR,
52 };
53
54 enum atmel_mci_state {
55 STATE_IDLE = 0,
56 STATE_SENDING_CMD,
57 STATE_SENDING_DATA,
58 STATE_DATA_BUSY,
59 STATE_SENDING_STOP,
60 STATE_DATA_ERROR,
61 };
62
63 enum atmci_xfer_dir {
64 XFER_RECEIVE = 0,
65 XFER_TRANSMIT,
66 };
67
68 enum atmci_pdc_buf {
69 PDC_FIRST_BUF = 0,
70 PDC_SECOND_BUF,
71 };
72
73 struct atmel_mci_caps {
74 bool has_dma;
75 bool has_pdc;
76 bool has_cfg_reg;
77 bool has_cstor_reg;
78 bool has_highspeed;
79 bool has_rwproof;
80 bool has_odd_clk_div;
81 };
82
83 struct atmel_mci_dma {
84 struct dma_chan *chan;
85 struct dma_async_tx_descriptor *data_desc;
86 };
87
88 /**
89 * struct atmel_mci - MMC controller state shared between all slots
90 * @lock: Spinlock protecting the queue and associated data.
91 * @regs: Pointer to MMIO registers.
92 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
93 * @pio_offset: Offset into the current scatterlist entry.
94 * @cur_slot: The slot which is currently using the controller.
95 * @mrq: The request currently being processed on @cur_slot,
96 * or NULL if the controller is idle.
97 * @cmd: The command currently being sent to the card, or NULL.
98 * @data: The data currently being transferred, or NULL if no data
99 * transfer is in progress.
100 * @data_size: just data->blocks * data->blksz.
101 * @dma: DMA client state.
102 * @data_chan: DMA channel being used for the current data transfer.
103 * @cmd_status: Snapshot of SR taken upon completion of the current
104 * command. Only valid when EVENT_CMD_COMPLETE is pending.
105 * @data_status: Snapshot of SR taken upon completion of the current
106 * data transfer. Only valid when EVENT_DATA_COMPLETE or
107 * EVENT_DATA_ERROR is pending.
108 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
109 * to be sent.
110 * @tasklet: Tasklet running the request state machine.
111 * @pending_events: Bitmask of events flagged by the interrupt handler
112 * to be processed by the tasklet.
113 * @completed_events: Bitmask of events which the state machine has
114 * processed.
115 * @state: Tasklet state.
116 * @queue: List of slots waiting for access to the controller.
117 * @need_clock_update: Update the clock rate before the next request.
118 * @need_reset: Reset controller before next request.
119 * @mode_reg: Value of the MR register.
120 * @cfg_reg: Value of the CFG register.
121 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
122 * rate and timeout calculations.
123 * @mapbase: Physical address of the MMIO registers.
124 * @mck: The peripheral bus clock hooked up to the MMC controller.
125 * @pdev: Platform device associated with the MMC controller.
126 * @slot: Slots sharing this MMC controller.
127 * @caps: MCI capabilities depending on MCI version.
128 * @prepare_data: function to setup MCI before data transfer which
129 * depends on MCI capabilities.
130 * @submit_data: function to start data transfer which depends on MCI
131 * capabilities.
132 * @stop_transfer: function to stop data transfer which depends on MCI
133 * capabilities.
134 *
135 * Locking
136 * =======
137 *
138 * @lock is a softirq-safe spinlock protecting @queue as well as
139 * @cur_slot, @mrq and @state. These must always be updated
140 * at the same time while holding @lock.
141 *
142 * @lock also protects mode_reg and need_clock_update since these are
143 * used to synchronize mode register updates with the queue
144 * processing.
145 *
146 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
147 * and must always be written at the same time as the slot is added to
148 * @queue.
149 *
150 * @pending_events and @completed_events are accessed using atomic bit
151 * operations, so they don't need any locking.
152 *
153 * None of the fields touched by the interrupt handler need any
154 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
155 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
156 * interrupts must be disabled and @data_status updated with a
157 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
158 * CMDRDY interrupt must be disabled and @cmd_status updated with a
159 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
160 * bytes_xfered field of @data must be written. This is ensured by
161 * using barriers.
162 */
163 struct atmel_mci {
164 spinlock_t lock;
165 void __iomem *regs;
166
167 struct scatterlist *sg;
168 unsigned int sg_len;
169 unsigned int pio_offset;
170
171 struct atmel_mci_slot *cur_slot;
172 struct mmc_request *mrq;
173 struct mmc_command *cmd;
174 struct mmc_data *data;
175 unsigned int data_size;
176
177 struct atmel_mci_dma dma;
178 struct dma_chan *data_chan;
179 struct dma_slave_config dma_conf;
180
181 u32 cmd_status;
182 u32 data_status;
183 u32 stop_cmdr;
184
185 struct tasklet_struct tasklet;
186 unsigned long pending_events;
187 unsigned long completed_events;
188 enum atmel_mci_state state;
189 struct list_head queue;
190
191 bool need_clock_update;
192 bool need_reset;
193 u32 mode_reg;
194 u32 cfg_reg;
195 unsigned long bus_hz;
196 unsigned long mapbase;
197 struct clk *mck;
198 struct platform_device *pdev;
199
200 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
201
202 struct atmel_mci_caps caps;
203
204 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
205 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
206 void (*stop_transfer)(struct atmel_mci *host);
207 };
208
209 /**
210 * struct atmel_mci_slot - MMC slot state
211 * @mmc: The mmc_host representing this slot.
212 * @host: The MMC controller this slot is using.
213 * @sdc_reg: Value of SDCR to be written before using this slot.
214 * @sdio_irq: SDIO irq mask for this slot.
215 * @mrq: mmc_request currently being processed or waiting to be
216 * processed, or NULL when the slot is idle.
217 * @queue_node: List node for placing this node in the @queue list of
218 * &struct atmel_mci.
219 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
220 * @flags: Random state bits associated with the slot.
221 * @detect_pin: GPIO pin used for card detection, or negative if not
222 * available.
223 * @wp_pin: GPIO pin used for card write protect sending, or negative
224 * if not available.
225 * @detect_is_active_high: The state of the detect pin when it is active.
226 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
227 */
228 struct atmel_mci_slot {
229 struct mmc_host *mmc;
230 struct atmel_mci *host;
231
232 u32 sdc_reg;
233 u32 sdio_irq;
234
235 struct mmc_request *mrq;
236 struct list_head queue_node;
237
238 unsigned int clock;
239 unsigned long flags;
240 #define ATMCI_CARD_PRESENT 0
241 #define ATMCI_CARD_NEED_INIT 1
242 #define ATMCI_SHUTDOWN 2
243 #define ATMCI_SUSPENDED 3
244
245 int detect_pin;
246 int wp_pin;
247 bool detect_is_active_high;
248
249 struct timer_list detect_timer;
250 };
251
252 #define atmci_test_and_clear_pending(host, event) \
253 test_and_clear_bit(event, &host->pending_events)
254 #define atmci_set_completed(host, event) \
255 set_bit(event, &host->completed_events)
256 #define atmci_set_pending(host, event) \
257 set_bit(event, &host->pending_events)
258
259 /*
260 * The debugfs stuff below is mostly optimized away when
261 * CONFIG_DEBUG_FS is not set.
262 */
263 static int atmci_req_show(struct seq_file *s, void *v)
264 {
265 struct atmel_mci_slot *slot = s->private;
266 struct mmc_request *mrq;
267 struct mmc_command *cmd;
268 struct mmc_command *stop;
269 struct mmc_data *data;
270
271 /* Make sure we get a consistent snapshot */
272 spin_lock_bh(&slot->host->lock);
273 mrq = slot->mrq;
274
275 if (mrq) {
276 cmd = mrq->cmd;
277 data = mrq->data;
278 stop = mrq->stop;
279
280 if (cmd)
281 seq_printf(s,
282 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
283 cmd->opcode, cmd->arg, cmd->flags,
284 cmd->resp[0], cmd->resp[1], cmd->resp[2],
285 cmd->resp[3], cmd->error);
286 if (data)
287 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
288 data->bytes_xfered, data->blocks,
289 data->blksz, data->flags, data->error);
290 if (stop)
291 seq_printf(s,
292 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
293 stop->opcode, stop->arg, stop->flags,
294 stop->resp[0], stop->resp[1], stop->resp[2],
295 stop->resp[3], stop->error);
296 }
297
298 spin_unlock_bh(&slot->host->lock);
299
300 return 0;
301 }
302
303 static int atmci_req_open(struct inode *inode, struct file *file)
304 {
305 return single_open(file, atmci_req_show, inode->i_private);
306 }
307
308 static const struct file_operations atmci_req_fops = {
309 .owner = THIS_MODULE,
310 .open = atmci_req_open,
311 .read = seq_read,
312 .llseek = seq_lseek,
313 .release = single_release,
314 };
315
316 static void atmci_show_status_reg(struct seq_file *s,
317 const char *regname, u32 value)
318 {
319 static const char *sr_bit[] = {
320 [0] = "CMDRDY",
321 [1] = "RXRDY",
322 [2] = "TXRDY",
323 [3] = "BLKE",
324 [4] = "DTIP",
325 [5] = "NOTBUSY",
326 [6] = "ENDRX",
327 [7] = "ENDTX",
328 [8] = "SDIOIRQA",
329 [9] = "SDIOIRQB",
330 [12] = "SDIOWAIT",
331 [14] = "RXBUFF",
332 [15] = "TXBUFE",
333 [16] = "RINDE",
334 [17] = "RDIRE",
335 [18] = "RCRCE",
336 [19] = "RENDE",
337 [20] = "RTOE",
338 [21] = "DCRCE",
339 [22] = "DTOE",
340 [23] = "CSTOE",
341 [24] = "BLKOVRE",
342 [25] = "DMADONE",
343 [26] = "FIFOEMPTY",
344 [27] = "XFRDONE",
345 [30] = "OVRE",
346 [31] = "UNRE",
347 };
348 unsigned int i;
349
350 seq_printf(s, "%s:\t0x%08x", regname, value);
351 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
352 if (value & (1 << i)) {
353 if (sr_bit[i])
354 seq_printf(s, " %s", sr_bit[i]);
355 else
356 seq_puts(s, " UNKNOWN");
357 }
358 }
359 seq_putc(s, '\n');
360 }
361
362 static int atmci_regs_show(struct seq_file *s, void *v)
363 {
364 struct atmel_mci *host = s->private;
365 u32 *buf;
366
367 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
368 if (!buf)
369 return -ENOMEM;
370
371 /*
372 * Grab a more or less consistent snapshot. Note that we're
373 * not disabling interrupts, so IMR and SR may not be
374 * consistent.
375 */
376 spin_lock_bh(&host->lock);
377 clk_enable(host->mck);
378 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
379 clk_disable(host->mck);
380 spin_unlock_bh(&host->lock);
381
382 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
383 buf[ATMCI_MR / 4],
384 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
385 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
386 buf[ATMCI_MR / 4] & 0xff);
387 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
388 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
389 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
390 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
391 buf[ATMCI_BLKR / 4],
392 buf[ATMCI_BLKR / 4] & 0xffff,
393 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
394 if (host->caps.has_cstor_reg)
395 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
396
397 /* Don't read RSPR and RDR; it will consume the data there */
398
399 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
400 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
401
402 if (host->caps.has_dma) {
403 u32 val;
404
405 val = buf[ATMCI_DMA / 4];
406 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
407 val, val & 3,
408 ((val >> 4) & 3) ?
409 1 << (((val >> 4) & 3) + 1) : 1,
410 val & ATMCI_DMAEN ? " DMAEN" : "");
411 }
412 if (host->caps.has_cfg_reg) {
413 u32 val;
414
415 val = buf[ATMCI_CFG / 4];
416 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
417 val,
418 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
419 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
420 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
421 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
422 }
423
424 kfree(buf);
425
426 return 0;
427 }
428
429 static int atmci_regs_open(struct inode *inode, struct file *file)
430 {
431 return single_open(file, atmci_regs_show, inode->i_private);
432 }
433
434 static const struct file_operations atmci_regs_fops = {
435 .owner = THIS_MODULE,
436 .open = atmci_regs_open,
437 .read = seq_read,
438 .llseek = seq_lseek,
439 .release = single_release,
440 };
441
442 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
443 {
444 struct mmc_host *mmc = slot->mmc;
445 struct atmel_mci *host = slot->host;
446 struct dentry *root;
447 struct dentry *node;
448
449 root = mmc->debugfs_root;
450 if (!root)
451 return;
452
453 node = debugfs_create_file("regs", S_IRUSR, root, host,
454 &atmci_regs_fops);
455 if (IS_ERR(node))
456 return;
457 if (!node)
458 goto err;
459
460 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
461 if (!node)
462 goto err;
463
464 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
465 if (!node)
466 goto err;
467
468 node = debugfs_create_x32("pending_events", S_IRUSR, root,
469 (u32 *)&host->pending_events);
470 if (!node)
471 goto err;
472
473 node = debugfs_create_x32("completed_events", S_IRUSR, root,
474 (u32 *)&host->completed_events);
475 if (!node)
476 goto err;
477
478 return;
479
480 err:
481 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
482 }
483
484 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
485 unsigned int ns)
486 {
487 /*
488 * It is easier here to use us instead of ns for the timeout,
489 * it prevents from overflows during calculation.
490 */
491 unsigned int us = DIV_ROUND_UP(ns, 1000);
492
493 /* Maximum clock frequency is host->bus_hz/2 */
494 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
495 }
496
497 static void atmci_set_timeout(struct atmel_mci *host,
498 struct atmel_mci_slot *slot, struct mmc_data *data)
499 {
500 static unsigned dtomul_to_shift[] = {
501 0, 4, 7, 8, 10, 12, 16, 20
502 };
503 unsigned timeout;
504 unsigned dtocyc;
505 unsigned dtomul;
506
507 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
508 + data->timeout_clks;
509
510 for (dtomul = 0; dtomul < 8; dtomul++) {
511 unsigned shift = dtomul_to_shift[dtomul];
512 dtocyc = (timeout + (1 << shift) - 1) >> shift;
513 if (dtocyc < 15)
514 break;
515 }
516
517 if (dtomul >= 8) {
518 dtomul = 7;
519 dtocyc = 15;
520 }
521
522 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
523 dtocyc << dtomul_to_shift[dtomul]);
524 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
525 }
526
527 /*
528 * Return mask with command flags to be enabled for this command.
529 */
530 static u32 atmci_prepare_command(struct mmc_host *mmc,
531 struct mmc_command *cmd)
532 {
533 struct mmc_data *data;
534 u32 cmdr;
535
536 cmd->error = -EINPROGRESS;
537
538 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
539
540 if (cmd->flags & MMC_RSP_PRESENT) {
541 if (cmd->flags & MMC_RSP_136)
542 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
543 else
544 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
545 }
546
547 /*
548 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
549 * it's too difficult to determine whether this is an ACMD or
550 * not. Better make it 64.
551 */
552 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
553
554 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
555 cmdr |= ATMCI_CMDR_OPDCMD;
556
557 data = cmd->data;
558 if (data) {
559 cmdr |= ATMCI_CMDR_START_XFER;
560
561 if (cmd->opcode == SD_IO_RW_EXTENDED) {
562 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
563 } else {
564 if (data->flags & MMC_DATA_STREAM)
565 cmdr |= ATMCI_CMDR_STREAM;
566 else if (data->blocks > 1)
567 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
568 else
569 cmdr |= ATMCI_CMDR_BLOCK;
570 }
571
572 if (data->flags & MMC_DATA_READ)
573 cmdr |= ATMCI_CMDR_TRDIR_READ;
574 }
575
576 return cmdr;
577 }
578
579 static void atmci_send_command(struct atmel_mci *host,
580 struct mmc_command *cmd, u32 cmd_flags)
581 {
582 WARN_ON(host->cmd);
583 host->cmd = cmd;
584
585 dev_vdbg(&host->pdev->dev,
586 "start command: ARGR=0x%08x CMDR=0x%08x\n",
587 cmd->arg, cmd_flags);
588
589 atmci_writel(host, ATMCI_ARGR, cmd->arg);
590 atmci_writel(host, ATMCI_CMDR, cmd_flags);
591 }
592
593 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
594 {
595 atmci_send_command(host, data->stop, host->stop_cmdr);
596 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
597 }
598
599 /*
600 * Configure given PDC buffer taking care of alignement issues.
601 * Update host->data_size and host->sg.
602 */
603 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
604 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
605 {
606 u32 pointer_reg, counter_reg;
607
608 if (dir == XFER_RECEIVE) {
609 pointer_reg = ATMEL_PDC_RPR;
610 counter_reg = ATMEL_PDC_RCR;
611 } else {
612 pointer_reg = ATMEL_PDC_TPR;
613 counter_reg = ATMEL_PDC_TCR;
614 }
615
616 if (buf_nb == PDC_SECOND_BUF) {
617 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
618 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
619 }
620
621 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
622 if (host->data_size <= sg_dma_len(host->sg)) {
623 if (host->data_size & 0x3) {
624 /* If size is different from modulo 4, transfer bytes */
625 atmci_writel(host, counter_reg, host->data_size);
626 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
627 } else {
628 /* Else transfer 32-bits words */
629 atmci_writel(host, counter_reg, host->data_size / 4);
630 }
631 host->data_size = 0;
632 } else {
633 /* We assume the size of a page is 32-bits aligned */
634 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
635 host->data_size -= sg_dma_len(host->sg);
636 if (host->data_size)
637 host->sg = sg_next(host->sg);
638 }
639 }
640
641 /*
642 * Configure PDC buffer according to the data size ie configuring one or two
643 * buffers. Don't use this function if you want to configure only the second
644 * buffer. In this case, use atmci_pdc_set_single_buf.
645 */
646 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
647 {
648 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
649 if (host->data_size)
650 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
651 }
652
653 /*
654 * Unmap sg lists, called when transfer is finished.
655 */
656 static void atmci_pdc_cleanup(struct atmel_mci *host)
657 {
658 struct mmc_data *data = host->data;
659
660 if (data)
661 dma_unmap_sg(&host->pdev->dev,
662 data->sg, data->sg_len,
663 ((data->flags & MMC_DATA_WRITE)
664 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
665 }
666
667 /*
668 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
669 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
670 * interrupt needed for both transfer directions.
671 */
672 static void atmci_pdc_complete(struct atmel_mci *host)
673 {
674 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
675 atmci_pdc_cleanup(host);
676
677 /*
678 * If the card was removed, data will be NULL. No point trying
679 * to send the stop command or waiting for NBUSY in this case.
680 */
681 if (host->data) {
682 atmci_set_pending(host, EVENT_XFER_COMPLETE);
683 tasklet_schedule(&host->tasklet);
684 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
685 }
686 }
687
688 static void atmci_dma_cleanup(struct atmel_mci *host)
689 {
690 struct mmc_data *data = host->data;
691
692 if (data)
693 dma_unmap_sg(host->dma.chan->device->dev,
694 data->sg, data->sg_len,
695 ((data->flags & MMC_DATA_WRITE)
696 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
697 }
698
699 /*
700 * This function is called by the DMA driver from tasklet context.
701 */
702 static void atmci_dma_complete(void *arg)
703 {
704 struct atmel_mci *host = arg;
705 struct mmc_data *data = host->data;
706
707 dev_vdbg(&host->pdev->dev, "DMA complete\n");
708
709 if (host->caps.has_dma)
710 /* Disable DMA hardware handshaking on MCI */
711 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
712
713 atmci_dma_cleanup(host);
714
715 /*
716 * If the card was removed, data will be NULL. No point trying
717 * to send the stop command or waiting for NBUSY in this case.
718 */
719 if (data) {
720 atmci_set_pending(host, EVENT_XFER_COMPLETE);
721 tasklet_schedule(&host->tasklet);
722
723 /*
724 * Regardless of what the documentation says, we have
725 * to wait for NOTBUSY even after block read
726 * operations.
727 *
728 * When the DMA transfer is complete, the controller
729 * may still be reading the CRC from the card, i.e.
730 * the data transfer is still in progress and we
731 * haven't seen all the potential error bits yet.
732 *
733 * The interrupt handler will schedule a different
734 * tasklet to finish things up when the data transfer
735 * is completely done.
736 *
737 * We may not complete the mmc request here anyway
738 * because the mmc layer may call back and cause us to
739 * violate the "don't submit new operations from the
740 * completion callback" rule of the dma engine
741 * framework.
742 */
743 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
744 }
745 }
746
747 /*
748 * Returns a mask of interrupt flags to be enabled after the whole
749 * request has been prepared.
750 */
751 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
752 {
753 u32 iflags;
754
755 data->error = -EINPROGRESS;
756
757 host->sg = data->sg;
758 host->sg_len = data->sg_len;
759 host->data = data;
760 host->data_chan = NULL;
761
762 iflags = ATMCI_DATA_ERROR_FLAGS;
763
764 /*
765 * Errata: MMC data write operation with less than 12
766 * bytes is impossible.
767 *
768 * Errata: MCI Transmit Data Register (TDR) FIFO
769 * corruption when length is not multiple of 4.
770 */
771 if (data->blocks * data->blksz < 12
772 || (data->blocks * data->blksz) & 3)
773 host->need_reset = true;
774
775 host->pio_offset = 0;
776 if (data->flags & MMC_DATA_READ)
777 iflags |= ATMCI_RXRDY;
778 else
779 iflags |= ATMCI_TXRDY;
780
781 return iflags;
782 }
783
784 /*
785 * Set interrupt flags and set block length into the MCI mode register even
786 * if this value is also accessible in the MCI block register. It seems to be
787 * necessary before the High Speed MCI version. It also map sg and configure
788 * PDC registers.
789 */
790 static u32
791 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
792 {
793 u32 iflags, tmp;
794 unsigned int sg_len;
795 enum dma_data_direction dir;
796
797 data->error = -EINPROGRESS;
798
799 host->data = data;
800 host->sg = data->sg;
801 iflags = ATMCI_DATA_ERROR_FLAGS;
802
803 /* Enable pdc mode */
804 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
805
806 if (data->flags & MMC_DATA_READ) {
807 dir = DMA_FROM_DEVICE;
808 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
809 } else {
810 dir = DMA_TO_DEVICE;
811 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE;
812 }
813
814 /* Set BLKLEN */
815 tmp = atmci_readl(host, ATMCI_MR);
816 tmp &= 0x0000ffff;
817 tmp |= ATMCI_BLKLEN(data->blksz);
818 atmci_writel(host, ATMCI_MR, tmp);
819
820 /* Configure PDC */
821 host->data_size = data->blocks * data->blksz;
822 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
823 if (host->data_size)
824 atmci_pdc_set_both_buf(host,
825 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
826
827 return iflags;
828 }
829
830 static u32
831 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
832 {
833 struct dma_chan *chan;
834 struct dma_async_tx_descriptor *desc;
835 struct scatterlist *sg;
836 unsigned int i;
837 enum dma_data_direction direction;
838 enum dma_transfer_direction slave_dirn;
839 unsigned int sglen;
840 u32 iflags;
841
842 data->error = -EINPROGRESS;
843
844 WARN_ON(host->data);
845 host->sg = NULL;
846 host->data = data;
847
848 iflags = ATMCI_DATA_ERROR_FLAGS;
849
850 /*
851 * We don't do DMA on "complex" transfers, i.e. with
852 * non-word-aligned buffers or lengths. Also, we don't bother
853 * with all the DMA setup overhead for short transfers.
854 */
855 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
856 return atmci_prepare_data(host, data);
857 if (data->blksz & 3)
858 return atmci_prepare_data(host, data);
859
860 for_each_sg(data->sg, sg, data->sg_len, i) {
861 if (sg->offset & 3 || sg->length & 3)
862 return atmci_prepare_data(host, data);
863 }
864
865 /* If we don't have a channel, we can't do DMA */
866 chan = host->dma.chan;
867 if (chan)
868 host->data_chan = chan;
869
870 if (!chan)
871 return -ENODEV;
872
873 if (host->caps.has_dma)
874 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
875
876 if (data->flags & MMC_DATA_READ) {
877 direction = DMA_FROM_DEVICE;
878 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
879 } else {
880 direction = DMA_TO_DEVICE;
881 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
882 }
883
884 sglen = dma_map_sg(chan->device->dev, data->sg,
885 data->sg_len, direction);
886
887 dmaengine_slave_config(chan, &host->dma_conf);
888 desc = dmaengine_prep_slave_sg(chan,
889 data->sg, sglen, slave_dirn,
890 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
891 if (!desc)
892 goto unmap_exit;
893
894 host->dma.data_desc = desc;
895 desc->callback = atmci_dma_complete;
896 desc->callback_param = host;
897
898 return iflags;
899 unmap_exit:
900 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
901 return -ENOMEM;
902 }
903
904 static void
905 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
906 {
907 return;
908 }
909
910 /*
911 * Start PDC according to transfer direction.
912 */
913 static void
914 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
915 {
916 if (data->flags & MMC_DATA_READ)
917 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
918 else
919 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
920 }
921
922 static void
923 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
924 {
925 struct dma_chan *chan = host->data_chan;
926 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
927
928 if (chan) {
929 dmaengine_submit(desc);
930 dma_async_issue_pending(chan);
931 }
932 }
933
934 static void atmci_stop_transfer(struct atmel_mci *host)
935 {
936 atmci_set_pending(host, EVENT_XFER_COMPLETE);
937 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
938 }
939
940 /*
941 * Stop data transfer because error(s) occured.
942 */
943 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
944 {
945 atmci_set_pending(host, EVENT_XFER_COMPLETE);
946 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
947 }
948
949 static void atmci_stop_transfer_dma(struct atmel_mci *host)
950 {
951 struct dma_chan *chan = host->data_chan;
952
953 if (chan) {
954 dmaengine_terminate_all(chan);
955 atmci_dma_cleanup(host);
956 } else {
957 /* Data transfer was stopped by the interrupt handler */
958 atmci_set_pending(host, EVENT_XFER_COMPLETE);
959 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
960 }
961 }
962
963 /*
964 * Start a request: prepare data if needed, prepare the command and activate
965 * interrupts.
966 */
967 static void atmci_start_request(struct atmel_mci *host,
968 struct atmel_mci_slot *slot)
969 {
970 struct mmc_request *mrq;
971 struct mmc_command *cmd;
972 struct mmc_data *data;
973 u32 iflags;
974 u32 cmdflags;
975
976 mrq = slot->mrq;
977 host->cur_slot = slot;
978 host->mrq = mrq;
979
980 host->pending_events = 0;
981 host->completed_events = 0;
982 host->data_status = 0;
983
984 if (host->need_reset) {
985 iflags = atmci_readl(host, ATMCI_IMR);
986 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
987 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
988 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
989 atmci_writel(host, ATMCI_MR, host->mode_reg);
990 if (host->caps.has_cfg_reg)
991 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
992 atmci_writel(host, ATMCI_IER, iflags);
993 host->need_reset = false;
994 }
995 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
996
997 iflags = atmci_readl(host, ATMCI_IMR);
998 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
999 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1000 iflags);
1001
1002 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1003 /* Send init sequence (74 clock cycles) */
1004 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1005 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1006 cpu_relax();
1007 }
1008 iflags = 0;
1009 data = mrq->data;
1010 if (data) {
1011 atmci_set_timeout(host, slot, data);
1012
1013 /* Must set block count/size before sending command */
1014 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1015 | ATMCI_BLKLEN(data->blksz));
1016 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1017 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1018
1019 iflags |= host->prepare_data(host, data);
1020 }
1021
1022 iflags |= ATMCI_CMDRDY;
1023 cmd = mrq->cmd;
1024 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1025
1026 /*
1027 * DMA transfer should be started before sending the command to avoid
1028 * unexpected errors especially for read operations in SDIO mode.
1029 * Unfortunately, in PDC mode, command has to be sent before starting
1030 * the transfer.
1031 */
1032 if (host->submit_data != &atmci_submit_data_dma)
1033 atmci_send_command(host, cmd, cmdflags);
1034
1035 if (data)
1036 host->submit_data(host, data);
1037
1038 if (host->submit_data == &atmci_submit_data_dma)
1039 atmci_send_command(host, cmd, cmdflags);
1040
1041 if (mrq->stop) {
1042 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1043 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1044 if (!(data->flags & MMC_DATA_WRITE))
1045 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1046 if (data->flags & MMC_DATA_STREAM)
1047 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1048 else
1049 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1050 }
1051
1052 /*
1053 * We could have enabled interrupts earlier, but I suspect
1054 * that would open up a nice can of interesting race
1055 * conditions (e.g. command and data complete, but stop not
1056 * prepared yet.)
1057 */
1058 atmci_writel(host, ATMCI_IER, iflags);
1059 }
1060
1061 static void atmci_queue_request(struct atmel_mci *host,
1062 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1063 {
1064 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1065 host->state);
1066
1067 spin_lock_bh(&host->lock);
1068 slot->mrq = mrq;
1069 if (host->state == STATE_IDLE) {
1070 host->state = STATE_SENDING_CMD;
1071 atmci_start_request(host, slot);
1072 } else {
1073 list_add_tail(&slot->queue_node, &host->queue);
1074 }
1075 spin_unlock_bh(&host->lock);
1076 }
1077
1078 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1079 {
1080 struct atmel_mci_slot *slot = mmc_priv(mmc);
1081 struct atmel_mci *host = slot->host;
1082 struct mmc_data *data;
1083
1084 WARN_ON(slot->mrq);
1085
1086 /*
1087 * We may "know" the card is gone even though there's still an
1088 * electrical connection. If so, we really need to communicate
1089 * this to the MMC core since there won't be any more
1090 * interrupts as the card is completely removed. Otherwise,
1091 * the MMC core might believe the card is still there even
1092 * though the card was just removed very slowly.
1093 */
1094 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1095 mrq->cmd->error = -ENOMEDIUM;
1096 mmc_request_done(mmc, mrq);
1097 return;
1098 }
1099
1100 /* We don't support multiple blocks of weird lengths. */
1101 data = mrq->data;
1102 if (data && data->blocks > 1 && data->blksz & 3) {
1103 mrq->cmd->error = -EINVAL;
1104 mmc_request_done(mmc, mrq);
1105 }
1106
1107 atmci_queue_request(host, slot, mrq);
1108 }
1109
1110 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1111 {
1112 struct atmel_mci_slot *slot = mmc_priv(mmc);
1113 struct atmel_mci *host = slot->host;
1114 unsigned int i;
1115
1116 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1117 switch (ios->bus_width) {
1118 case MMC_BUS_WIDTH_1:
1119 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1120 break;
1121 case MMC_BUS_WIDTH_4:
1122 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1123 break;
1124 }
1125
1126 if (ios->clock) {
1127 unsigned int clock_min = ~0U;
1128 u32 clkdiv;
1129
1130 spin_lock_bh(&host->lock);
1131 if (!host->mode_reg) {
1132 clk_enable(host->mck);
1133 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1134 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1135 if (host->caps.has_cfg_reg)
1136 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1137 }
1138
1139 /*
1140 * Use mirror of ios->clock to prevent race with mmc
1141 * core ios update when finding the minimum.
1142 */
1143 slot->clock = ios->clock;
1144 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1145 if (host->slot[i] && host->slot[i]->clock
1146 && host->slot[i]->clock < clock_min)
1147 clock_min = host->slot[i]->clock;
1148 }
1149
1150 /* Calculate clock divider */
1151 if (host->caps.has_odd_clk_div) {
1152 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1153 if (clkdiv > 511) {
1154 dev_warn(&mmc->class_dev,
1155 "clock %u too slow; using %lu\n",
1156 clock_min, host->bus_hz / (511 + 2));
1157 clkdiv = 511;
1158 }
1159 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1160 | ATMCI_MR_CLKODD(clkdiv & 1);
1161 } else {
1162 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1163 if (clkdiv > 255) {
1164 dev_warn(&mmc->class_dev,
1165 "clock %u too slow; using %lu\n",
1166 clock_min, host->bus_hz / (2 * 256));
1167 clkdiv = 255;
1168 }
1169 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1170 }
1171
1172 /*
1173 * WRPROOF and RDPROOF prevent overruns/underruns by
1174 * stopping the clock when the FIFO is full/empty.
1175 * This state is not expected to last for long.
1176 */
1177 if (host->caps.has_rwproof)
1178 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1179
1180 if (host->caps.has_cfg_reg) {
1181 /* setup High Speed mode in relation with card capacity */
1182 if (ios->timing == MMC_TIMING_SD_HS)
1183 host->cfg_reg |= ATMCI_CFG_HSMODE;
1184 else
1185 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1186 }
1187
1188 if (list_empty(&host->queue)) {
1189 atmci_writel(host, ATMCI_MR, host->mode_reg);
1190 if (host->caps.has_cfg_reg)
1191 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1192 } else {
1193 host->need_clock_update = true;
1194 }
1195
1196 spin_unlock_bh(&host->lock);
1197 } else {
1198 bool any_slot_active = false;
1199
1200 spin_lock_bh(&host->lock);
1201 slot->clock = 0;
1202 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1203 if (host->slot[i] && host->slot[i]->clock) {
1204 any_slot_active = true;
1205 break;
1206 }
1207 }
1208 if (!any_slot_active) {
1209 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1210 if (host->mode_reg) {
1211 atmci_readl(host, ATMCI_MR);
1212 clk_disable(host->mck);
1213 }
1214 host->mode_reg = 0;
1215 }
1216 spin_unlock_bh(&host->lock);
1217 }
1218
1219 switch (ios->power_mode) {
1220 case MMC_POWER_UP:
1221 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1222 break;
1223 default:
1224 /*
1225 * TODO: None of the currently available AVR32-based
1226 * boards allow MMC power to be turned off. Implement
1227 * power control when this can be tested properly.
1228 *
1229 * We also need to hook this into the clock management
1230 * somehow so that newly inserted cards aren't
1231 * subjected to a fast clock before we have a chance
1232 * to figure out what the maximum rate is. Currently,
1233 * there's no way to avoid this, and there never will
1234 * be for boards that don't support power control.
1235 */
1236 break;
1237 }
1238 }
1239
1240 static int atmci_get_ro(struct mmc_host *mmc)
1241 {
1242 int read_only = -ENOSYS;
1243 struct atmel_mci_slot *slot = mmc_priv(mmc);
1244
1245 if (gpio_is_valid(slot->wp_pin)) {
1246 read_only = gpio_get_value(slot->wp_pin);
1247 dev_dbg(&mmc->class_dev, "card is %s\n",
1248 read_only ? "read-only" : "read-write");
1249 }
1250
1251 return read_only;
1252 }
1253
1254 static int atmci_get_cd(struct mmc_host *mmc)
1255 {
1256 int present = -ENOSYS;
1257 struct atmel_mci_slot *slot = mmc_priv(mmc);
1258
1259 if (gpio_is_valid(slot->detect_pin)) {
1260 present = !(gpio_get_value(slot->detect_pin) ^
1261 slot->detect_is_active_high);
1262 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1263 present ? "" : "not ");
1264 }
1265
1266 return present;
1267 }
1268
1269 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1270 {
1271 struct atmel_mci_slot *slot = mmc_priv(mmc);
1272 struct atmel_mci *host = slot->host;
1273
1274 if (enable)
1275 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1276 else
1277 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1278 }
1279
1280 static const struct mmc_host_ops atmci_ops = {
1281 .request = atmci_request,
1282 .set_ios = atmci_set_ios,
1283 .get_ro = atmci_get_ro,
1284 .get_cd = atmci_get_cd,
1285 .enable_sdio_irq = atmci_enable_sdio_irq,
1286 };
1287
1288 /* Called with host->lock held */
1289 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1290 __releases(&host->lock)
1291 __acquires(&host->lock)
1292 {
1293 struct atmel_mci_slot *slot = NULL;
1294 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1295
1296 WARN_ON(host->cmd || host->data);
1297
1298 /*
1299 * Update the MMC clock rate if necessary. This may be
1300 * necessary if set_ios() is called when a different slot is
1301 * busy transferring data.
1302 */
1303 if (host->need_clock_update) {
1304 atmci_writel(host, ATMCI_MR, host->mode_reg);
1305 if (host->caps.has_cfg_reg)
1306 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1307 }
1308
1309 host->cur_slot->mrq = NULL;
1310 host->mrq = NULL;
1311 if (!list_empty(&host->queue)) {
1312 slot = list_entry(host->queue.next,
1313 struct atmel_mci_slot, queue_node);
1314 list_del(&slot->queue_node);
1315 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1316 mmc_hostname(slot->mmc));
1317 host->state = STATE_SENDING_CMD;
1318 atmci_start_request(host, slot);
1319 } else {
1320 dev_vdbg(&host->pdev->dev, "list empty\n");
1321 host->state = STATE_IDLE;
1322 }
1323
1324 spin_unlock(&host->lock);
1325 mmc_request_done(prev_mmc, mrq);
1326 spin_lock(&host->lock);
1327 }
1328
1329 static void atmci_command_complete(struct atmel_mci *host,
1330 struct mmc_command *cmd)
1331 {
1332 u32 status = host->cmd_status;
1333
1334 /* Read the response from the card (up to 16 bytes) */
1335 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1336 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1337 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1338 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1339
1340 if (status & ATMCI_RTOE)
1341 cmd->error = -ETIMEDOUT;
1342 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1343 cmd->error = -EILSEQ;
1344 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1345 cmd->error = -EIO;
1346 else
1347 cmd->error = 0;
1348
1349 if (cmd->error) {
1350 dev_dbg(&host->pdev->dev,
1351 "command error: status=0x%08x\n", status);
1352
1353 if (cmd->data) {
1354 host->stop_transfer(host);
1355 host->data = NULL;
1356 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY
1357 | ATMCI_TXRDY | ATMCI_RXRDY
1358 | ATMCI_DATA_ERROR_FLAGS);
1359 }
1360 }
1361 }
1362
1363 static void atmci_detect_change(unsigned long data)
1364 {
1365 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1366 bool present;
1367 bool present_old;
1368
1369 /*
1370 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1371 * freeing the interrupt. We must not re-enable the interrupt
1372 * if it has been freed, and if we're shutting down, it
1373 * doesn't really matter whether the card is present or not.
1374 */
1375 smp_rmb();
1376 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1377 return;
1378
1379 enable_irq(gpio_to_irq(slot->detect_pin));
1380 present = !(gpio_get_value(slot->detect_pin) ^
1381 slot->detect_is_active_high);
1382 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1383
1384 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1385 present, present_old);
1386
1387 if (present != present_old) {
1388 struct atmel_mci *host = slot->host;
1389 struct mmc_request *mrq;
1390
1391 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1392 present ? "inserted" : "removed");
1393
1394 spin_lock(&host->lock);
1395
1396 if (!present)
1397 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1398 else
1399 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1400
1401 /* Clean up queue if present */
1402 mrq = slot->mrq;
1403 if (mrq) {
1404 if (mrq == host->mrq) {
1405 /*
1406 * Reset controller to terminate any ongoing
1407 * commands or data transfers.
1408 */
1409 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1410 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1411 atmci_writel(host, ATMCI_MR, host->mode_reg);
1412 if (host->caps.has_cfg_reg)
1413 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1414
1415 host->data = NULL;
1416 host->cmd = NULL;
1417
1418 switch (host->state) {
1419 case STATE_IDLE:
1420 break;
1421 case STATE_SENDING_CMD:
1422 mrq->cmd->error = -ENOMEDIUM;
1423 if (!mrq->data)
1424 break;
1425 /* fall through */
1426 case STATE_SENDING_DATA:
1427 mrq->data->error = -ENOMEDIUM;
1428 host->stop_transfer(host);
1429 break;
1430 case STATE_DATA_BUSY:
1431 case STATE_DATA_ERROR:
1432 if (mrq->data->error == -EINPROGRESS)
1433 mrq->data->error = -ENOMEDIUM;
1434 if (!mrq->stop)
1435 break;
1436 /* fall through */
1437 case STATE_SENDING_STOP:
1438 mrq->stop->error = -ENOMEDIUM;
1439 break;
1440 }
1441
1442 atmci_request_end(host, mrq);
1443 } else {
1444 list_del(&slot->queue_node);
1445 mrq->cmd->error = -ENOMEDIUM;
1446 if (mrq->data)
1447 mrq->data->error = -ENOMEDIUM;
1448 if (mrq->stop)
1449 mrq->stop->error = -ENOMEDIUM;
1450
1451 spin_unlock(&host->lock);
1452 mmc_request_done(slot->mmc, mrq);
1453 spin_lock(&host->lock);
1454 }
1455 }
1456 spin_unlock(&host->lock);
1457
1458 mmc_detect_change(slot->mmc, 0);
1459 }
1460 }
1461
1462 static void atmci_tasklet_func(unsigned long priv)
1463 {
1464 struct atmel_mci *host = (struct atmel_mci *)priv;
1465 struct mmc_request *mrq = host->mrq;
1466 struct mmc_data *data = host->data;
1467 struct mmc_command *cmd = host->cmd;
1468 enum atmel_mci_state state = host->state;
1469 enum atmel_mci_state prev_state;
1470 u32 status;
1471
1472 spin_lock(&host->lock);
1473
1474 state = host->state;
1475
1476 dev_vdbg(&host->pdev->dev,
1477 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1478 state, host->pending_events, host->completed_events,
1479 atmci_readl(host, ATMCI_IMR));
1480
1481 do {
1482 prev_state = state;
1483
1484 switch (state) {
1485 case STATE_IDLE:
1486 break;
1487
1488 case STATE_SENDING_CMD:
1489 if (!atmci_test_and_clear_pending(host,
1490 EVENT_CMD_COMPLETE))
1491 break;
1492
1493 host->cmd = NULL;
1494 atmci_set_completed(host, EVENT_CMD_COMPLETE);
1495 atmci_command_complete(host, mrq->cmd);
1496 if (!mrq->data || cmd->error) {
1497 atmci_request_end(host, host->mrq);
1498 goto unlock;
1499 }
1500
1501 prev_state = state = STATE_SENDING_DATA;
1502 /* fall through */
1503
1504 case STATE_SENDING_DATA:
1505 if (atmci_test_and_clear_pending(host,
1506 EVENT_DATA_ERROR)) {
1507 host->stop_transfer(host);
1508 if (data->stop)
1509 atmci_send_stop_cmd(host, data);
1510 state = STATE_DATA_ERROR;
1511 break;
1512 }
1513
1514 if (!atmci_test_and_clear_pending(host,
1515 EVENT_XFER_COMPLETE))
1516 break;
1517
1518 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1519 prev_state = state = STATE_DATA_BUSY;
1520 /* fall through */
1521
1522 case STATE_DATA_BUSY:
1523 if (!atmci_test_and_clear_pending(host,
1524 EVENT_DATA_COMPLETE))
1525 break;
1526
1527 host->data = NULL;
1528 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1529 status = host->data_status;
1530 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
1531 if (status & ATMCI_DTOE) {
1532 dev_dbg(&host->pdev->dev,
1533 "data timeout error\n");
1534 data->error = -ETIMEDOUT;
1535 } else if (status & ATMCI_DCRCE) {
1536 dev_dbg(&host->pdev->dev,
1537 "data CRC error\n");
1538 data->error = -EILSEQ;
1539 } else {
1540 dev_dbg(&host->pdev->dev,
1541 "data FIFO error (status=%08x)\n",
1542 status);
1543 data->error = -EIO;
1544 }
1545 } else {
1546 data->bytes_xfered = data->blocks * data->blksz;
1547 data->error = 0;
1548 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS);
1549 }
1550
1551 if (!data->stop) {
1552 atmci_request_end(host, host->mrq);
1553 goto unlock;
1554 }
1555
1556 prev_state = state = STATE_SENDING_STOP;
1557 if (!data->error)
1558 atmci_send_stop_cmd(host, data);
1559 /* fall through */
1560
1561 case STATE_SENDING_STOP:
1562 if (!atmci_test_and_clear_pending(host,
1563 EVENT_CMD_COMPLETE))
1564 break;
1565
1566 host->cmd = NULL;
1567 atmci_command_complete(host, mrq->stop);
1568 atmci_request_end(host, host->mrq);
1569 goto unlock;
1570
1571 case STATE_DATA_ERROR:
1572 if (!atmci_test_and_clear_pending(host,
1573 EVENT_XFER_COMPLETE))
1574 break;
1575
1576 state = STATE_DATA_BUSY;
1577 break;
1578 }
1579 } while (state != prev_state);
1580
1581 host->state = state;
1582
1583 unlock:
1584 spin_unlock(&host->lock);
1585 }
1586
1587 static void atmci_read_data_pio(struct atmel_mci *host)
1588 {
1589 struct scatterlist *sg = host->sg;
1590 void *buf = sg_virt(sg);
1591 unsigned int offset = host->pio_offset;
1592 struct mmc_data *data = host->data;
1593 u32 value;
1594 u32 status;
1595 unsigned int nbytes = 0;
1596
1597 do {
1598 value = atmci_readl(host, ATMCI_RDR);
1599 if (likely(offset + 4 <= sg->length)) {
1600 put_unaligned(value, (u32 *)(buf + offset));
1601
1602 offset += 4;
1603 nbytes += 4;
1604
1605 if (offset == sg->length) {
1606 flush_dcache_page(sg_page(sg));
1607 host->sg = sg = sg_next(sg);
1608 host->sg_len--;
1609 if (!sg || !host->sg_len)
1610 goto done;
1611
1612 offset = 0;
1613 buf = sg_virt(sg);
1614 }
1615 } else {
1616 unsigned int remaining = sg->length - offset;
1617 memcpy(buf + offset, &value, remaining);
1618 nbytes += remaining;
1619
1620 flush_dcache_page(sg_page(sg));
1621 host->sg = sg = sg_next(sg);
1622 host->sg_len--;
1623 if (!sg || !host->sg_len)
1624 goto done;
1625
1626 offset = 4 - remaining;
1627 buf = sg_virt(sg);
1628 memcpy(buf, (u8 *)&value + remaining, offset);
1629 nbytes += offset;
1630 }
1631
1632 status = atmci_readl(host, ATMCI_SR);
1633 if (status & ATMCI_DATA_ERROR_FLAGS) {
1634 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1635 | ATMCI_DATA_ERROR_FLAGS));
1636 host->data_status = status;
1637 data->bytes_xfered += nbytes;
1638 smp_wmb();
1639 atmci_set_pending(host, EVENT_DATA_ERROR);
1640 tasklet_schedule(&host->tasklet);
1641 return;
1642 }
1643 } while (status & ATMCI_RXRDY);
1644
1645 host->pio_offset = offset;
1646 data->bytes_xfered += nbytes;
1647
1648 return;
1649
1650 done:
1651 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1652 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1653 data->bytes_xfered += nbytes;
1654 smp_wmb();
1655 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1656 }
1657
1658 static void atmci_write_data_pio(struct atmel_mci *host)
1659 {
1660 struct scatterlist *sg = host->sg;
1661 void *buf = sg_virt(sg);
1662 unsigned int offset = host->pio_offset;
1663 struct mmc_data *data = host->data;
1664 u32 value;
1665 u32 status;
1666 unsigned int nbytes = 0;
1667
1668 do {
1669 if (likely(offset + 4 <= sg->length)) {
1670 value = get_unaligned((u32 *)(buf + offset));
1671 atmci_writel(host, ATMCI_TDR, value);
1672
1673 offset += 4;
1674 nbytes += 4;
1675 if (offset == sg->length) {
1676 host->sg = sg = sg_next(sg);
1677 host->sg_len--;
1678 if (!sg || !host->sg_len)
1679 goto done;
1680
1681 offset = 0;
1682 buf = sg_virt(sg);
1683 }
1684 } else {
1685 unsigned int remaining = sg->length - offset;
1686
1687 value = 0;
1688 memcpy(&value, buf + offset, remaining);
1689 nbytes += remaining;
1690
1691 host->sg = sg = sg_next(sg);
1692 host->sg_len--;
1693 if (!sg || !host->sg_len) {
1694 atmci_writel(host, ATMCI_TDR, value);
1695 goto done;
1696 }
1697
1698 offset = 4 - remaining;
1699 buf = sg_virt(sg);
1700 memcpy((u8 *)&value + remaining, buf, offset);
1701 atmci_writel(host, ATMCI_TDR, value);
1702 nbytes += offset;
1703 }
1704
1705 status = atmci_readl(host, ATMCI_SR);
1706 if (status & ATMCI_DATA_ERROR_FLAGS) {
1707 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1708 | ATMCI_DATA_ERROR_FLAGS));
1709 host->data_status = status;
1710 data->bytes_xfered += nbytes;
1711 smp_wmb();
1712 atmci_set_pending(host, EVENT_DATA_ERROR);
1713 tasklet_schedule(&host->tasklet);
1714 return;
1715 }
1716 } while (status & ATMCI_TXRDY);
1717
1718 host->pio_offset = offset;
1719 data->bytes_xfered += nbytes;
1720
1721 return;
1722
1723 done:
1724 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1725 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1726 data->bytes_xfered += nbytes;
1727 smp_wmb();
1728 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1729 }
1730
1731 static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
1732 {
1733 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
1734
1735 host->cmd_status = status;
1736 smp_wmb();
1737 atmci_set_pending(host, EVENT_CMD_COMPLETE);
1738 tasklet_schedule(&host->tasklet);
1739 }
1740
1741 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1742 {
1743 int i;
1744
1745 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1746 struct atmel_mci_slot *slot = host->slot[i];
1747 if (slot && (status & slot->sdio_irq)) {
1748 mmc_signal_sdio_irq(slot->mmc);
1749 }
1750 }
1751 }
1752
1753
1754 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1755 {
1756 struct atmel_mci *host = dev_id;
1757 u32 status, mask, pending;
1758 unsigned int pass_count = 0;
1759
1760 do {
1761 status = atmci_readl(host, ATMCI_SR);
1762 mask = atmci_readl(host, ATMCI_IMR);
1763 pending = status & mask;
1764 if (!pending)
1765 break;
1766
1767 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1768 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1769 | ATMCI_RXRDY | ATMCI_TXRDY);
1770 pending &= atmci_readl(host, ATMCI_IMR);
1771
1772 host->data_status = status;
1773 smp_wmb();
1774 atmci_set_pending(host, EVENT_DATA_ERROR);
1775 tasklet_schedule(&host->tasklet);
1776 }
1777
1778 if (pending & ATMCI_TXBUFE) {
1779 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1780 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1781 /*
1782 * We can receive this interruption before having configured
1783 * the second pdc buffer, so we need to reconfigure first and
1784 * second buffers again
1785 */
1786 if (host->data_size) {
1787 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1788 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1789 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1790 } else {
1791 atmci_pdc_complete(host);
1792 }
1793 } else if (pending & ATMCI_ENDTX) {
1794 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1795
1796 if (host->data_size) {
1797 atmci_pdc_set_single_buf(host,
1798 XFER_TRANSMIT, PDC_SECOND_BUF);
1799 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1800 }
1801 }
1802
1803 if (pending & ATMCI_RXBUFF) {
1804 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
1805 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1806 /*
1807 * We can receive this interruption before having configured
1808 * the second pdc buffer, so we need to reconfigure first and
1809 * second buffers again
1810 */
1811 if (host->data_size) {
1812 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
1813 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1814 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1815 } else {
1816 atmci_pdc_complete(host);
1817 }
1818 } else if (pending & ATMCI_ENDRX) {
1819 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1820
1821 if (host->data_size) {
1822 atmci_pdc_set_single_buf(host,
1823 XFER_RECEIVE, PDC_SECOND_BUF);
1824 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1825 }
1826 }
1827
1828
1829 if (pending & ATMCI_NOTBUSY) {
1830 atmci_writel(host, ATMCI_IDR,
1831 ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY);
1832 if (!host->data_status)
1833 host->data_status = status;
1834 smp_wmb();
1835 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1836 tasklet_schedule(&host->tasklet);
1837 }
1838 if (pending & ATMCI_RXRDY)
1839 atmci_read_data_pio(host);
1840 if (pending & ATMCI_TXRDY)
1841 atmci_write_data_pio(host);
1842
1843 if (pending & ATMCI_CMDRDY)
1844 atmci_cmd_interrupt(host, status);
1845
1846 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1847 atmci_sdio_interrupt(host, status);
1848
1849 } while (pass_count++ < 5);
1850
1851 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1852 }
1853
1854 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1855 {
1856 struct atmel_mci_slot *slot = dev_id;
1857
1858 /*
1859 * Disable interrupts until the pin has stabilized and check
1860 * the state then. Use mod_timer() since we may be in the
1861 * middle of the timer routine when this interrupt triggers.
1862 */
1863 disable_irq_nosync(irq);
1864 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
1865
1866 return IRQ_HANDLED;
1867 }
1868
1869 static int __init atmci_init_slot(struct atmel_mci *host,
1870 struct mci_slot_pdata *slot_data, unsigned int id,
1871 u32 sdc_reg, u32 sdio_irq)
1872 {
1873 struct mmc_host *mmc;
1874 struct atmel_mci_slot *slot;
1875
1876 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1877 if (!mmc)
1878 return -ENOMEM;
1879
1880 slot = mmc_priv(mmc);
1881 slot->mmc = mmc;
1882 slot->host = host;
1883 slot->detect_pin = slot_data->detect_pin;
1884 slot->wp_pin = slot_data->wp_pin;
1885 slot->detect_is_active_high = slot_data->detect_is_active_high;
1886 slot->sdc_reg = sdc_reg;
1887 slot->sdio_irq = sdio_irq;
1888
1889 mmc->ops = &atmci_ops;
1890 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1891 mmc->f_max = host->bus_hz / 2;
1892 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1893 if (sdio_irq)
1894 mmc->caps |= MMC_CAP_SDIO_IRQ;
1895 if (host->caps.has_highspeed)
1896 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1897 if (slot_data->bus_width >= 4)
1898 mmc->caps |= MMC_CAP_4_BIT_DATA;
1899
1900 mmc->max_segs = 64;
1901 mmc->max_req_size = 32768 * 512;
1902 mmc->max_blk_size = 32768;
1903 mmc->max_blk_count = 512;
1904
1905 /* Assume card is present initially */
1906 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1907 if (gpio_is_valid(slot->detect_pin)) {
1908 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1909 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1910 slot->detect_pin = -EBUSY;
1911 } else if (gpio_get_value(slot->detect_pin) ^
1912 slot->detect_is_active_high) {
1913 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1914 }
1915 }
1916
1917 if (!gpio_is_valid(slot->detect_pin))
1918 mmc->caps |= MMC_CAP_NEEDS_POLL;
1919
1920 if (gpio_is_valid(slot->wp_pin)) {
1921 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1922 dev_dbg(&mmc->class_dev, "no WP pin available\n");
1923 slot->wp_pin = -EBUSY;
1924 }
1925 }
1926
1927 host->slot[id] = slot;
1928 mmc_add_host(mmc);
1929
1930 if (gpio_is_valid(slot->detect_pin)) {
1931 int ret;
1932
1933 setup_timer(&slot->detect_timer, atmci_detect_change,
1934 (unsigned long)slot);
1935
1936 ret = request_irq(gpio_to_irq(slot->detect_pin),
1937 atmci_detect_interrupt,
1938 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1939 "mmc-detect", slot);
1940 if (ret) {
1941 dev_dbg(&mmc->class_dev,
1942 "could not request IRQ %d for detect pin\n",
1943 gpio_to_irq(slot->detect_pin));
1944 gpio_free(slot->detect_pin);
1945 slot->detect_pin = -EBUSY;
1946 }
1947 }
1948
1949 atmci_init_debugfs(slot);
1950
1951 return 0;
1952 }
1953
1954 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1955 unsigned int id)
1956 {
1957 /* Debugfs stuff is cleaned up by mmc core */
1958
1959 set_bit(ATMCI_SHUTDOWN, &slot->flags);
1960 smp_wmb();
1961
1962 mmc_remove_host(slot->mmc);
1963
1964 if (gpio_is_valid(slot->detect_pin)) {
1965 int pin = slot->detect_pin;
1966
1967 free_irq(gpio_to_irq(pin), slot);
1968 del_timer_sync(&slot->detect_timer);
1969 gpio_free(pin);
1970 }
1971 if (gpio_is_valid(slot->wp_pin))
1972 gpio_free(slot->wp_pin);
1973
1974 slot->host->slot[id] = NULL;
1975 mmc_free_host(slot->mmc);
1976 }
1977
1978 static bool atmci_filter(struct dma_chan *chan, void *slave)
1979 {
1980 struct mci_dma_data *sl = slave;
1981
1982 if (sl && find_slave_dev(sl) == chan->device->dev) {
1983 chan->private = slave_data_ptr(sl);
1984 return true;
1985 } else {
1986 return false;
1987 }
1988 }
1989
1990 static bool atmci_configure_dma(struct atmel_mci *host)
1991 {
1992 struct mci_platform_data *pdata;
1993
1994 if (host == NULL)
1995 return false;
1996
1997 pdata = host->pdev->dev.platform_data;
1998
1999 if (pdata && find_slave_dev(pdata->dma_slave)) {
2000 dma_cap_mask_t mask;
2001
2002 /* Try to grab a DMA channel */
2003 dma_cap_zero(mask);
2004 dma_cap_set(DMA_SLAVE, mask);
2005 host->dma.chan =
2006 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
2007 }
2008 if (!host->dma.chan) {
2009 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2010 return false;
2011 } else {
2012 dev_info(&host->pdev->dev,
2013 "using %s for DMA transfers\n",
2014 dma_chan_name(host->dma.chan));
2015
2016 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2017 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2018 host->dma_conf.src_maxburst = 1;
2019 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2020 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2021 host->dma_conf.dst_maxburst = 1;
2022 host->dma_conf.device_fc = false;
2023 return true;
2024 }
2025 }
2026
2027 static inline unsigned int atmci_get_version(struct atmel_mci *host)
2028 {
2029 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
2030 }
2031
2032 /*
2033 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2034 * HSMCI provides DMA support and a new config register but no more supports
2035 * PDC.
2036 */
2037 static void __init atmci_get_cap(struct atmel_mci *host)
2038 {
2039 unsigned int version;
2040
2041 version = atmci_get_version(host);
2042 dev_info(&host->pdev->dev,
2043 "version: 0x%x\n", version);
2044
2045 host->caps.has_dma = 0;
2046 host->caps.has_pdc = 1;
2047 host->caps.has_cfg_reg = 0;
2048 host->caps.has_cstor_reg = 0;
2049 host->caps.has_highspeed = 0;
2050 host->caps.has_rwproof = 0;
2051 host->caps.has_odd_clk_div = 0;
2052
2053 /* keep only major version number */
2054 switch (version & 0xf00) {
2055 case 0x500:
2056 host->caps.has_odd_clk_div = 1;
2057 case 0x400:
2058 case 0x300:
2059 #ifdef CONFIG_AT_HDMAC
2060 host->caps.has_dma = 1;
2061 #else
2062 dev_info(&host->pdev->dev,
2063 "has dma capability but dma engine is not selected, then use pio\n");
2064 #endif
2065 host->caps.has_pdc = 0;
2066 host->caps.has_cfg_reg = 1;
2067 host->caps.has_cstor_reg = 1;
2068 host->caps.has_highspeed = 1;
2069 case 0x200:
2070 host->caps.has_rwproof = 1;
2071 case 0x100:
2072 break;
2073 default:
2074 host->caps.has_pdc = 0;
2075 dev_warn(&host->pdev->dev,
2076 "Unmanaged mci version, set minimum capabilities\n");
2077 break;
2078 }
2079 }
2080
2081 static int __init atmci_probe(struct platform_device *pdev)
2082 {
2083 struct mci_platform_data *pdata;
2084 struct atmel_mci *host;
2085 struct resource *regs;
2086 unsigned int nr_slots;
2087 int irq;
2088 int ret;
2089
2090 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2091 if (!regs)
2092 return -ENXIO;
2093 pdata = pdev->dev.platform_data;
2094 if (!pdata)
2095 return -ENXIO;
2096 irq = platform_get_irq(pdev, 0);
2097 if (irq < 0)
2098 return irq;
2099
2100 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2101 if (!host)
2102 return -ENOMEM;
2103
2104 host->pdev = pdev;
2105 spin_lock_init(&host->lock);
2106 INIT_LIST_HEAD(&host->queue);
2107
2108 host->mck = clk_get(&pdev->dev, "mci_clk");
2109 if (IS_ERR(host->mck)) {
2110 ret = PTR_ERR(host->mck);
2111 goto err_clk_get;
2112 }
2113
2114 ret = -ENOMEM;
2115 host->regs = ioremap(regs->start, resource_size(regs));
2116 if (!host->regs)
2117 goto err_ioremap;
2118
2119 clk_enable(host->mck);
2120 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2121 host->bus_hz = clk_get_rate(host->mck);
2122 clk_disable(host->mck);
2123
2124 host->mapbase = regs->start;
2125
2126 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2127
2128 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2129 if (ret)
2130 goto err_request_irq;
2131
2132 /* Get MCI capabilities and set operations according to it */
2133 atmci_get_cap(host);
2134 if (host->caps.has_dma && atmci_configure_dma(host)) {
2135 host->prepare_data = &atmci_prepare_data_dma;
2136 host->submit_data = &atmci_submit_data_dma;
2137 host->stop_transfer = &atmci_stop_transfer_dma;
2138 } else if (host->caps.has_pdc) {
2139 dev_info(&pdev->dev, "using PDC\n");
2140 host->prepare_data = &atmci_prepare_data_pdc;
2141 host->submit_data = &atmci_submit_data_pdc;
2142 host->stop_transfer = &atmci_stop_transfer_pdc;
2143 } else {
2144 dev_info(&pdev->dev, "using PIO\n");
2145 host->prepare_data = &atmci_prepare_data;
2146 host->submit_data = &atmci_submit_data;
2147 host->stop_transfer = &atmci_stop_transfer;
2148 }
2149
2150 platform_set_drvdata(pdev, host);
2151
2152 /* We need at least one slot to succeed */
2153 nr_slots = 0;
2154 ret = -ENODEV;
2155 if (pdata->slot[0].bus_width) {
2156 ret = atmci_init_slot(host, &pdata->slot[0],
2157 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2158 if (!ret)
2159 nr_slots++;
2160 }
2161 if (pdata->slot[1].bus_width) {
2162 ret = atmci_init_slot(host, &pdata->slot[1],
2163 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2164 if (!ret)
2165 nr_slots++;
2166 }
2167
2168 if (!nr_slots) {
2169 dev_err(&pdev->dev, "init failed: no slot defined\n");
2170 goto err_init_slot;
2171 }
2172
2173 dev_info(&pdev->dev,
2174 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2175 host->mapbase, irq, nr_slots);
2176
2177 return 0;
2178
2179 err_init_slot:
2180 if (host->dma.chan)
2181 dma_release_channel(host->dma.chan);
2182 free_irq(irq, host);
2183 err_request_irq:
2184 iounmap(host->regs);
2185 err_ioremap:
2186 clk_put(host->mck);
2187 err_clk_get:
2188 kfree(host);
2189 return ret;
2190 }
2191
2192 static int __exit atmci_remove(struct platform_device *pdev)
2193 {
2194 struct atmel_mci *host = platform_get_drvdata(pdev);
2195 unsigned int i;
2196
2197 platform_set_drvdata(pdev, NULL);
2198
2199 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2200 if (host->slot[i])
2201 atmci_cleanup_slot(host->slot[i], i);
2202 }
2203
2204 clk_enable(host->mck);
2205 atmci_writel(host, ATMCI_IDR, ~0UL);
2206 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2207 atmci_readl(host, ATMCI_SR);
2208 clk_disable(host->mck);
2209
2210 if (host->dma.chan)
2211 dma_release_channel(host->dma.chan);
2212
2213 free_irq(platform_get_irq(pdev, 0), host);
2214 iounmap(host->regs);
2215
2216 clk_put(host->mck);
2217 kfree(host);
2218
2219 return 0;
2220 }
2221
2222 #ifdef CONFIG_PM
2223 static int atmci_suspend(struct device *dev)
2224 {
2225 struct atmel_mci *host = dev_get_drvdata(dev);
2226 int i;
2227
2228 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2229 struct atmel_mci_slot *slot = host->slot[i];
2230 int ret;
2231
2232 if (!slot)
2233 continue;
2234 ret = mmc_suspend_host(slot->mmc);
2235 if (ret < 0) {
2236 while (--i >= 0) {
2237 slot = host->slot[i];
2238 if (slot
2239 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2240 mmc_resume_host(host->slot[i]->mmc);
2241 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2242 }
2243 }
2244 return ret;
2245 } else {
2246 set_bit(ATMCI_SUSPENDED, &slot->flags);
2247 }
2248 }
2249
2250 return 0;
2251 }
2252
2253 static int atmci_resume(struct device *dev)
2254 {
2255 struct atmel_mci *host = dev_get_drvdata(dev);
2256 int i;
2257 int ret = 0;
2258
2259 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2260 struct atmel_mci_slot *slot = host->slot[i];
2261 int err;
2262
2263 slot = host->slot[i];
2264 if (!slot)
2265 continue;
2266 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2267 continue;
2268 err = mmc_resume_host(slot->mmc);
2269 if (err < 0)
2270 ret = err;
2271 else
2272 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2273 }
2274
2275 return ret;
2276 }
2277 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2278 #define ATMCI_PM_OPS (&atmci_pm)
2279 #else
2280 #define ATMCI_PM_OPS NULL
2281 #endif
2282
2283 static struct platform_driver atmci_driver = {
2284 .remove = __exit_p(atmci_remove),
2285 .driver = {
2286 .name = "atmel_mci",
2287 .pm = ATMCI_PM_OPS,
2288 },
2289 };
2290
2291 static int __init atmci_init(void)
2292 {
2293 return platform_driver_probe(&atmci_driver, atmci_probe);
2294 }
2295
2296 static void __exit atmci_exit(void)
2297 {
2298 platform_driver_unregister(&atmci_driver);
2299 }
2300
2301 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2302 module_exit(atmci_exit);
2303
2304 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2305 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2306 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support