drivers/mmc/host/sdhci-of-esdhc.c

   1 /*
   2  * Freescale eSDHC controller driver.
   3  *
   4  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
   5  * Copyright (c) 2009 MontaVista Software, Inc.
   6  *
   7  * Authors: Xiaobo Xie <X.Xie@freescale.com>
   8  *          Anton Vorontsov <avorontsov@ru.mvista.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  */
  15
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/delay.h>
  19 #include <linux/module.h>
  20 #include <linux/mmc/host.h>
  21 #include "sdhci-pltfm.h"
  22 #include "sdhci-esdhc.h"
  23
  24 static u16 esdhc_readw(struct sdhci_host *host, int reg)
  25 {
  26         u16 ret;
  27         int base = reg & ~0x3;
  28         int shift = (reg & 0x2) * 8;
  29
  30         if (unlikely(reg == SDHCI_HOST_VERSION))
  31                 ret = in_be32(host->ioaddr + base) & 0xffff;
  32         else
  33                 ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
  34         return ret;
  35 }
  36
  37 static u8 esdhc_readb(struct sdhci_host *host, int reg)
  38 {
  39         int base = reg & ~0x3;
  40         int shift = (reg & 0x3) * 8;
  41         u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
  42
  43         /*
  44          * "DMA select" locates at offset 0x28 in SD specification, but on
  45          * P5020 or P3041, it locates at 0x29.
  46          */
  47         if (reg == SDHCI_HOST_CONTROL) {
  48                 u32 dma_bits;
  49
  50                 dma_bits = in_be32(host->ioaddr + reg);
  51                 /* DMA select is 22,23 bits in Protocol Control Register */
  52                 dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
  53
  54                 /* fixup the result */
  55                 ret &= ~SDHCI_CTRL_DMA_MASK;
  56                 ret |= dma_bits;
  57         }
  58
  59         return ret;
  60 }
  61
  62 static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
  63 {
  64         if (reg == SDHCI_BLOCK_SIZE) {
  65                 /*
  66                  * Two last DMA bits are reserved, and first one is used for
  67                  * non-standard blksz of 4096 bytes that we don't support
  68                  * yet. So clear the DMA boundary bits.
  69                  */
  70                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  71         }
  72         sdhci_be32bs_writew(host, val, reg);
  73 }
  74
  75 static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
  76 {
  77         /*
  78          * "DMA select" location is offset 0x28 in SD specification, but on
  79          * P5020 or P3041, it's located at 0x29.
  80          */
  81         if (reg == SDHCI_HOST_CONTROL) {
  82                 u32 dma_bits;
  83
  84                 /* DMA select is 22,23 bits in Protocol Control Register */
  85                 dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
  86                 clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
  87                         dma_bits);
  88                 val &= ~SDHCI_CTRL_DMA_MASK;
  89                 val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
  90         }
  91
  92         /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
  93         if (reg == SDHCI_HOST_CONTROL)
  94                 val &= ~ESDHC_HOST_CONTROL_RES;
  95         sdhci_be32bs_writeb(host, val, reg);
  96 }
  97
  98 static int esdhc_of_enable_dma(struct sdhci_host *host)
  99 {
 100         setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
 101         return 0;
 102 }
 103
 104 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
 105 {
 106         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 107
 108         return pltfm_host->clock;
 109 }
 110
 111 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
 112 {
 113         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 114
 115         return pltfm_host->clock / 256 / 16;
 116 }
 117
 118 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
 119 {
 120         /* Workaround to reduce the clock frequency for p1010 esdhc */
 121         if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
 122                 if (clock > 20000000)
 123                         clock -= 5000000;
 124                 if (clock > 40000000)
 125                         clock -= 5000000;
 126         }
 127
 128         /* Set the clock */
 129         esdhc_set_clock(host, clock);
 130 }
 131
 132 #ifdef CONFIG_PM
 133 static u32 esdhc_proctl;
 134 static void esdhc_of_suspend(struct sdhci_host *host)
 135 {
 136         esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
 137 }
 138
 139 static void esdhc_of_resume(struct sdhci_host *host)
 140 {
 141         esdhc_of_enable_dma(host);
 142         sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
 143 }
 144 #endif
 145
 146 static struct sdhci_ops sdhci_esdhc_ops = {
 147         .read_l = sdhci_be32bs_readl,
 148         .read_w = esdhc_readw,
 149         .read_b = esdhc_readb,
 150         .write_l = sdhci_be32bs_writel,
 151         .write_w = esdhc_writew,
 152         .write_b = esdhc_writeb,
 153         .set_clock = esdhc_of_set_clock,
 154         .enable_dma = esdhc_of_enable_dma,
 155         .get_max_clock = esdhc_of_get_max_clock,
 156         .get_min_clock = esdhc_of_get_min_clock,
 157 #ifdef CONFIG_PM
 158         .platform_suspend = esdhc_of_suspend,
 159         .platform_resume = esdhc_of_resume,
 160 #endif
 161 };
 162
 163 static struct sdhci_pltfm_data sdhci_esdhc_pdata = {
 164         /* card detection could be handled via GPIO */
 165         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
 166                 | SDHCI_QUIRK_NO_CARD_NO_RESET,
 167         .ops = &sdhci_esdhc_ops,
 168 };
 169
 170 static int __devinit sdhci_esdhc_probe(struct platform_device *pdev)
 171 {
 172         return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
 173 }
 174
 175 static int __devexit sdhci_esdhc_remove(struct platform_device *pdev)
 176 {
 177         return sdhci_pltfm_unregister(pdev);
 178 }
 179
 180 static const struct of_device_id sdhci_esdhc_of_match[] = {
 181         { .compatible = "fsl,mpc8379-esdhc" },
 182         { .compatible = "fsl,mpc8536-esdhc" },
 183         { .compatible = "fsl,esdhc" },
 184         { }
 185 };
 186 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
 187
 188 static struct platform_driver sdhci_esdhc_driver = {
 189         .driver = {
 190                 .name = "sdhci-esdhc",
 191                 .owner = THIS_MODULE,
 192                 .of_match_table = sdhci_esdhc_of_match,
 193                 .pm = SDHCI_PLTFM_PMOPS,
 194         },
 195         .probe = sdhci_esdhc_probe,
 196         .remove = __devexit_p(sdhci_esdhc_remove),
 197 };
 198
 199 module_platform_driver(sdhci_esdhc_driver);
 200
 201 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
 202 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
 203               "Anton Vorontsov <avorontsov@ru.mvista.com>");
 204 MODULE_LICENSE("GPL v2");